From 3f81e1c795e576be40c70d39e6158aee3dafcdfd Mon Sep 17 00:00:00 2001 From: Rygnus Date: Mon, 25 Jun 2018 18:23:46 +0100 Subject: [PATCH] Add opcodes SQXTUN_S and SQXTUN_V (#184) * Add SQXTUN_S and SQXTUN_V Part 1/2 of commit * Add SQXTUN_S and SQXTUN_V (2/2) Part 2/2 of commit --- AOpCodeTable.cs | 4 +++- Instruction/AInstEmitSimdArithmetic.cs | 10 ++++++++++ 2 files changed, 13 insertions(+), 1 deletion(-) diff --git a/AOpCodeTable.cs b/AOpCodeTable.cs index 853c06a..c0c38bb 100644 --- a/AOpCodeTable.cs +++ b/AOpCodeTable.cs @@ -364,6 +364,8 @@ namespace ChocolArm64 SetA64("0x001110<<1xxxxx110000xxxxxxxxxx", AInstEmit.Smull_V, typeof(AOpCodeSimdReg)); SetA64("01011110<<100001010010xxxxxxxxxx", AInstEmit.Sqxtn_S, typeof(AOpCodeSimd)); SetA64("0x001110<<100001010010xxxxxxxxxx", AInstEmit.Sqxtn_V, typeof(AOpCodeSimd)); + SetA64("01111110<<100001001010xxxxxxxxxx", AInstEmit.Sqxtun_S, typeof(AOpCodeSimd)); + SetA64("0x101110<<100001001010xxxxxxxxxx", AInstEmit.Sqxtun_V, typeof(AOpCodeSimd)); SetA64("0>001110<<1xxxxx010001xxxxxxxxxx", AInstEmit.Sshl_V, typeof(AOpCodeSimdReg)); SetA64("0x00111100>>>xxx101001xxxxxxxxxx", AInstEmit.Sshll_V, typeof(AOpCodeSimdShImm)); SetA64("010111110>>>>xxx000001xxxxxxxxxx", AInstEmit.Sshr_S, typeof(AOpCodeSimdShImm)); @@ -560,4 +562,4 @@ namespace ChocolArm64 return AInst.Undefined; } } -} \ No newline at end of file +} diff --git a/Instruction/AInstEmitSimdArithmetic.cs b/Instruction/AInstEmitSimdArithmetic.cs index 49a5c50..8cd4654 100644 --- a/Instruction/AInstEmitSimdArithmetic.cs +++ b/Instruction/AInstEmitSimdArithmetic.cs @@ -1145,6 +1145,16 @@ namespace ChocolArm64.Instruction EmitQxtn(Context, Signed: true, Scalar: false); } + public static void Sqxtun_S(AILEmitterCtx Context) + { + EmitQxtn(Context, Signed: false, Scalar: true); + } + + public static void Sqxtun_V(AILEmitterCtx Context) + { + EmitQxtn(Context, Signed: false, Scalar: false); + } + public static void Sub_S(AILEmitterCtx Context) { EmitScalarBinaryOpZx(Context, () => Context.Emit(OpCodes.Sub));