diff --git a/ChocolArm64/AOpCodeTable.cs b/ChocolArm64/AOpCodeTable.cs index 5ea38b053..74d4915b9 100644 --- a/ChocolArm64/AOpCodeTable.cs +++ b/ChocolArm64/AOpCodeTable.cs @@ -380,8 +380,16 @@ namespace ChocolArm64 SetA64("0>001110<<100000011110xxxxxxxxxx", AInstEmit.Sqabs_V, typeof(AOpCodeSimd)); SetA64("01011110xx1xxxxx000011xxxxxxxxxx", AInstEmit.Sqadd_S, typeof(AOpCodeSimdReg)); SetA64("0>001110<<1xxxxx000011xxxxxxxxxx", AInstEmit.Sqadd_V, typeof(AOpCodeSimdReg)); + SetA64("01011110011xxxxx101101xxxxxxxxxx", AInstEmit.Sqdmulh_S, typeof(AOpCodeSimdReg)); + SetA64("01011110101xxxxx101101xxxxxxxxxx", AInstEmit.Sqdmulh_S, typeof(AOpCodeSimdReg)); + SetA64("0x001110011xxxxx101101xxxxxxxxxx", AInstEmit.Sqdmulh_V, typeof(AOpCodeSimdReg)); + SetA64("0x001110101xxxxx101101xxxxxxxxxx", AInstEmit.Sqdmulh_V, typeof(AOpCodeSimdReg)); SetA64("01111110xx100000011110xxxxxxxxxx", AInstEmit.Sqneg_S, typeof(AOpCodeSimd)); SetA64("0>101110<<100000011110xxxxxxxxxx", AInstEmit.Sqneg_V, typeof(AOpCodeSimd)); + SetA64("01111110011xxxxx101101xxxxxxxxxx", AInstEmit.Sqrdmulh_S, typeof(AOpCodeSimdReg)); + SetA64("01111110101xxxxx101101xxxxxxxxxx", AInstEmit.Sqrdmulh_S, typeof(AOpCodeSimdReg)); + SetA64("0x101110011xxxxx101101xxxxxxxxxx", AInstEmit.Sqrdmulh_V, typeof(AOpCodeSimdReg)); + SetA64("0x101110101xxxxx101101xxxxxxxxxx", AInstEmit.Sqrdmulh_V, typeof(AOpCodeSimdReg)); SetA64("0x00111100>>>xxx100111xxxxxxxxxx", AInstEmit.Sqrshrn_V, typeof(AOpCodeSimdShImm)); SetA64("01011110xx1xxxxx001011xxxxxxxxxx", AInstEmit.Sqsub_S, typeof(AOpCodeSimdReg)); SetA64("0>001110<<1xxxxx001011xxxxxxxxxx", AInstEmit.Sqsub_V, typeof(AOpCodeSimdReg)); diff --git a/ChocolArm64/Instruction/AInstEmitSimdArithmetic.cs b/ChocolArm64/Instruction/AInstEmitSimdArithmetic.cs index 559811d93..02e903f6f 100644 --- a/ChocolArm64/Instruction/AInstEmitSimdArithmetic.cs +++ b/ChocolArm64/Instruction/AInstEmitSimdArithmetic.cs @@ -158,6 +158,42 @@ namespace ChocolArm64.Instruction Context.MarkLabel(LblTrue); } + private static void EmitDoublingMultiplyHighHalf(AILEmitterCtx Context, bool Round) + { + AOpCodeSimdReg Op = (AOpCodeSimdReg)Context.CurrOp; + + int ESize = 8 << Op.Size; + + Context.Emit(OpCodes.Mul); + + if (!Round) + { + Context.EmitAsr(ESize - 1); + } + else + { + long RoundConst = 1L << (ESize - 1); + + AILLabel LblTrue = new AILLabel(); + + Context.EmitLsl(1); + + Context.EmitLdc_I8(RoundConst); + + Context.Emit(OpCodes.Add); + + Context.EmitAsr(ESize); + + Context.Emit(OpCodes.Dup); + Context.EmitLdc_I8((long)int.MinValue); + Context.Emit(OpCodes.Bne_Un_S, LblTrue); + + Context.Emit(OpCodes.Neg); + + Context.MarkLabel(LblTrue); + } + } + private static void EmitHighNarrow(AILEmitterCtx Context, Action Emit, bool Round) { AOpCodeSimdReg Op = (AOpCodeSimdReg)Context.CurrOp; @@ -1040,6 +1076,16 @@ namespace ChocolArm64.Instruction EmitVectorSaturatingBinaryOpSx(Context, SaturatingFlags.Add); } + public static void Sqdmulh_S(AILEmitterCtx Context) + { + EmitSaturatingBinaryOp(Context, () => EmitDoublingMultiplyHighHalf(Context, Round: false), SaturatingFlags.ScalarSx); + } + + public static void Sqdmulh_V(AILEmitterCtx Context) + { + EmitSaturatingBinaryOp(Context, () => EmitDoublingMultiplyHighHalf(Context, Round: false), SaturatingFlags.VectorSx); + } + public static void Sqneg_S(AILEmitterCtx Context) { EmitScalarSaturatingUnaryOpSx(Context, () => Context.Emit(OpCodes.Neg)); @@ -1050,6 +1096,16 @@ namespace ChocolArm64.Instruction EmitVectorSaturatingUnaryOpSx(Context, () => Context.Emit(OpCodes.Neg)); } + public static void Sqrdmulh_S(AILEmitterCtx Context) + { + EmitSaturatingBinaryOp(Context, () => EmitDoublingMultiplyHighHalf(Context, Round: true), SaturatingFlags.ScalarSx); + } + + public static void Sqrdmulh_V(AILEmitterCtx Context) + { + EmitSaturatingBinaryOp(Context, () => EmitDoublingMultiplyHighHalf(Context, Round: true), SaturatingFlags.VectorSx); + } + public static void Sqsub_S(AILEmitterCtx Context) { EmitScalarSaturatingBinaryOpSx(Context, SaturatingFlags.Sub); diff --git a/ChocolArm64/Instruction/AInstEmitSimdHelper.cs b/ChocolArm64/Instruction/AInstEmitSimdHelper.cs index 161c44ea2..a9af39024 100644 --- a/ChocolArm64/Instruction/AInstEmitSimdHelper.cs +++ b/ChocolArm64/Instruction/AInstEmitSimdHelper.cs @@ -804,7 +804,7 @@ namespace ChocolArm64.Instruction ScalarZx = Scalar, VectorSx = Signed, - VectorZx = 0, + VectorZx = 0 } public static void EmitScalarSaturatingUnaryOpSx(AILEmitterCtx Context, Action Emit) @@ -837,7 +837,14 @@ namespace ChocolArm64.Instruction Emit(); - EmitUnarySignedSatQAbsOrNeg(Context, Op.Size); + if (Op.Size <= 2) + { + EmitSatQ(Context, Op.Size, true, true); + } + else /* if (Op.Size == 3) */ + { + EmitUnarySignedSatQAbsOrNeg(Context); + } EmitVectorInsertTmp(Context, Index, Op.Size); } @@ -853,25 +860,25 @@ namespace ChocolArm64.Instruction public static void EmitScalarSaturatingBinaryOpSx(AILEmitterCtx Context, SaturatingFlags Flags) { - EmitSaturatingBinaryOp(Context, SaturatingFlags.ScalarSx | Flags); + EmitSaturatingBinaryOp(Context, () => { }, SaturatingFlags.ScalarSx | Flags); } public static void EmitScalarSaturatingBinaryOpZx(AILEmitterCtx Context, SaturatingFlags Flags) { - EmitSaturatingBinaryOp(Context, SaturatingFlags.ScalarZx | Flags); + EmitSaturatingBinaryOp(Context, () => { }, SaturatingFlags.ScalarZx | Flags); } public static void EmitVectorSaturatingBinaryOpSx(AILEmitterCtx Context, SaturatingFlags Flags) { - EmitSaturatingBinaryOp(Context, SaturatingFlags.VectorSx | Flags); + EmitSaturatingBinaryOp(Context, () => { }, SaturatingFlags.VectorSx | Flags); } public static void EmitVectorSaturatingBinaryOpZx(AILEmitterCtx Context, SaturatingFlags Flags) { - EmitSaturatingBinaryOp(Context, SaturatingFlags.VectorZx | Flags); + EmitSaturatingBinaryOp(Context, () => { }, SaturatingFlags.VectorZx | Flags); } - public static void EmitSaturatingBinaryOp(AILEmitterCtx Context, SaturatingFlags Flags) + public static void EmitSaturatingBinaryOp(AILEmitterCtx Context, Action Emit, SaturatingFlags Flags) { AOpCodeSimd Op = (AOpCodeSimd)Context.CurrOp; @@ -940,6 +947,20 @@ namespace ChocolArm64.Instruction EmitVectorInsertTmp(Context, Index, Op.Size); } } + else + { + for (int Index = 0; Index < Elems; Index++) + { + EmitVectorExtract(Context, Op.Rn, Index, Op.Size, Signed); + EmitVectorExtract(Context, ((AOpCodeSimdReg)Op).Rm, Index, Op.Size, Signed); + + Emit(); + + EmitSatQ(Context, Op.Size, true, Signed); + + EmitVectorInsertTmp(Context, Index, Op.Size); + } + } Context.EmitLdvectmp(); Context.EmitStvec(Op.Rd); @@ -1080,29 +1101,17 @@ namespace ChocolArm64.Instruction } } - // TSrc (8bit, 16bit, 32bit, 64bit) == TDst (8bit, 16bit, 32bit, 64bit); signed. - public static void EmitUnarySignedSatQAbsOrNeg(AILEmitterCtx Context, int Size) + // TSrc (64bit) == TDst (64bit); signed. + public static void EmitUnarySignedSatQAbsOrNeg(AILEmitterCtx Context) { - int ESize = 8 << Size; + if (((AOpCodeSimd)Context.CurrOp).Size < 3) + { + throw new InvalidOperationException(); + } - long TMaxValue = (1L << (ESize - 1)) - 1L; - long TMinValue = -(1L << (ESize - 1)); + Context.EmitLdarg(ATranslatedSub.StateArgIdx); - AILLabel LblFalse = new AILLabel(); - - Context.Emit(OpCodes.Dup); - Context.Emit(OpCodes.Neg); - Context.EmitLdc_I8(TMinValue); - Context.Emit(OpCodes.Ceq); - Context.Emit(OpCodes.Brfalse_S, LblFalse); - - Context.Emit(OpCodes.Pop); - - EmitSetFpsrQCFlag(Context); - - Context.EmitLdc_I8(TMaxValue); - - Context.MarkLabel(LblFalse); + ASoftFallback.EmitCall(Context, nameof(ASoftFallback.UnarySignedSatQAbsOrNeg)); } // TSrcs (64bit) == TDst (64bit); signed, unsigned. @@ -1150,22 +1159,6 @@ namespace ChocolArm64.Instruction : nameof(ASoftFallback.BinaryUnsignedSatQAcc)); } - public static void EmitSetFpsrQCFlag(AILEmitterCtx Context) - { - const int QCFlagBit = 27; - - Context.EmitLdarg(ATranslatedSub.StateArgIdx); - - Context.EmitLdarg(ATranslatedSub.StateArgIdx); - Context.EmitCallPropGet(typeof(AThreadState), nameof(AThreadState.Fpsr)); - - Context.EmitLdc_I4(1 << QCFlagBit); - - Context.Emit(OpCodes.Or); - - Context.EmitCallPropSet(typeof(AThreadState), nameof(AThreadState.Fpsr)); - } - public static void EmitScalarSet(AILEmitterCtx Context, int Reg, int Size) { EmitVectorZeroAll(Context, Reg); diff --git a/ChocolArm64/Instruction/ASoftFallback.cs b/ChocolArm64/Instruction/ASoftFallback.cs index a4d12dd61..408985781 100644 --- a/ChocolArm64/Instruction/ASoftFallback.cs +++ b/ChocolArm64/Instruction/ASoftFallback.cs @@ -11,6 +11,107 @@ namespace ChocolArm64.Instruction Context.EmitCall(typeof(ASoftFallback), MthdName); } +#region "Saturating" + public static long SignedSrcSignedDstSatQ(long op, int Size, AThreadState State) + { + int ESize = 8 << Size; + + long TMaxValue = (1L << (ESize - 1)) - 1L; + long TMinValue = -(1L << (ESize - 1)); + + if (op > TMaxValue) + { + SetFpsrQCFlag(State); + + return TMaxValue; + } + else if (op < TMinValue) + { + SetFpsrQCFlag(State); + + return TMinValue; + } + else + { + return op; + } + } + + public static ulong SignedSrcUnsignedDstSatQ(long op, int Size, AThreadState State) + { + int ESize = 8 << Size; + + ulong TMaxValue = (1UL << ESize) - 1UL; + ulong TMinValue = 0UL; + + if (op > (long)TMaxValue) + { + SetFpsrQCFlag(State); + + return TMaxValue; + } + else if (op < (long)TMinValue) + { + SetFpsrQCFlag(State); + + return TMinValue; + } + else + { + return (ulong)op; + } + } + + public static long UnsignedSrcSignedDstSatQ(ulong op, int Size, AThreadState State) + { + int ESize = 8 << Size; + + long TMaxValue = (1L << (ESize - 1)) - 1L; + + if (op > (ulong)TMaxValue) + { + SetFpsrQCFlag(State); + + return TMaxValue; + } + else + { + return (long)op; + } + } + + public static ulong UnsignedSrcUnsignedDstSatQ(ulong op, int Size, AThreadState State) + { + int ESize = 8 << Size; + + ulong TMaxValue = (1UL << ESize) - 1UL; + + if (op > TMaxValue) + { + SetFpsrQCFlag(State); + + return TMaxValue; + } + else + { + return op; + } + } + + public static long UnarySignedSatQAbsOrNeg(long op, AThreadState State) + { + if (op == long.MinValue) + { + SetFpsrQCFlag(State); + + return long.MaxValue; + } + else + { + return op; + } + } + public static long BinarySignedSatQAdd(long op1, long op2, AThreadState State) { long Add = op1 + op2; @@ -185,99 +286,15 @@ namespace ChocolArm64.Instruction } } - public static long SignedSrcSignedDstSatQ(long op, int Size, AThreadState State) - { - int ESize = 8 << Size; - - long TMaxValue = (1L << (ESize - 1)) - 1L; - long TMinValue = -(1L << (ESize - 1)); - - if (op > TMaxValue) - { - SetFpsrQCFlag(State); - - return TMaxValue; - } - else if (op < TMinValue) - { - SetFpsrQCFlag(State); - - return TMinValue; - } - else - { - return op; - } - } - - public static ulong SignedSrcUnsignedDstSatQ(long op, int Size, AThreadState State) - { - int ESize = 8 << Size; - - ulong TMaxValue = (1UL << ESize) - 1UL; - ulong TMinValue = 0UL; - - if (op > (long)TMaxValue) - { - SetFpsrQCFlag(State); - - return TMaxValue; - } - else if (op < (long)TMinValue) - { - SetFpsrQCFlag(State); - - return TMinValue; - } - else - { - return (ulong)op; - } - } - - public static long UnsignedSrcSignedDstSatQ(ulong op, int Size, AThreadState State) - { - int ESize = 8 << Size; - - long TMaxValue = (1L << (ESize - 1)) - 1L; - - if (op > (ulong)TMaxValue) - { - SetFpsrQCFlag(State); - - return TMaxValue; - } - else - { - return (long)op; - } - } - - public static ulong UnsignedSrcUnsignedDstSatQ(ulong op, int Size, AThreadState State) - { - int ESize = 8 << Size; - - ulong TMaxValue = (1UL << ESize) - 1UL; - - if (op > TMaxValue) - { - SetFpsrQCFlag(State); - - return TMaxValue; - } - else - { - return op; - } - } - private static void SetFpsrQCFlag(AThreadState State) { const int QCFlagBit = 27; State.Fpsr |= 1 << QCFlagBit; } +#endregion +#region "Count" public static ulong CountLeadingSigns(ulong Value, int Size) { Value ^= Value >> 1; @@ -325,7 +342,9 @@ namespace ChocolArm64.Instruction return (Value >> 4) + (Value & 0x0f); } +#endregion +#region "Crc32" private const uint Crc32RevPoly = 0xedb88320; private const uint Crc32cRevPoly = 0x82f63b78; @@ -384,7 +403,9 @@ namespace ChocolArm64.Instruction return Crc; } +#endregion +#region "Reverse" public static uint ReverseBits8(uint Value) { Value = ((Value & 0xaa) >> 1) | ((Value & 0x55) << 1); @@ -453,7 +474,9 @@ namespace ChocolArm64.Instruction throw new ArgumentException(nameof(Size)); } +#endregion +#region "MultiplyHigh" public static long SMulHi128(long LHS, long RHS) { long Result = (long)UMulHi128((ulong)LHS, (ulong)RHS); @@ -479,5 +502,6 @@ namespace ChocolArm64.Instruction return LHigh * RHigh + Z0 + (Z1 >> 32); } +#endregion } } diff --git a/Ryujinx.LLE/Luea.csproj b/Ryujinx.LLE/Luea.csproj index de1c5f61d..5c5715681 100644 --- a/Ryujinx.LLE/Luea.csproj +++ b/Ryujinx.LLE/Luea.csproj @@ -1,9 +1,9 @@ - Exe netcoreapp2.1 win10-x64;osx-x64;linux-x64 + Exe diff --git a/Ryujinx.ShaderTools/Ryujinx.ShaderTools.csproj b/Ryujinx.ShaderTools/Ryujinx.ShaderTools.csproj index 24f31efef..18452f0a6 100644 --- a/Ryujinx.ShaderTools/Ryujinx.ShaderTools.csproj +++ b/Ryujinx.ShaderTools/Ryujinx.ShaderTools.csproj @@ -1,13 +1,13 @@ + + netcoreapp2.1 + win10-x64;osx-x64;linux-x64 + Exe + + - - Exe - netcoreapp2.1 - win10-x64;osx-x64;linux-x64 - - diff --git a/Ryujinx.Tests/Cpu/CpuTestAlu.cs b/Ryujinx.Tests/Cpu/CpuTestAlu.cs index 564fadec2..c89cb646e 100644 --- a/Ryujinx.Tests/Cpu/CpuTestAlu.cs +++ b/Ryujinx.Tests/Cpu/CpuTestAlu.cs @@ -9,7 +9,7 @@ namespace Ryujinx.Tests.Cpu using Tester; using Tester.Types; - [Category("Alu"), Ignore("Tested: first half of 2018.")] + [Category("Alu"), Ignore("Tested: second half of 2018.")] public sealed class CpuTestAlu : CpuTest { #if Alu diff --git a/Ryujinx.Tests/Cpu/CpuTestAluImm.cs b/Ryujinx.Tests/Cpu/CpuTestAluImm.cs index 5d1f0b6ba..d436d65f8 100644 --- a/Ryujinx.Tests/Cpu/CpuTestAluImm.cs +++ b/Ryujinx.Tests/Cpu/CpuTestAluImm.cs @@ -9,7 +9,7 @@ namespace Ryujinx.Tests.Cpu using Tester; using Tester.Types; - [Category("AluImm"), Ignore("Tested: first half of 2018.")] + [Category("AluImm"), Ignore("Tested: second half of 2018.")] public sealed class CpuTestAluImm : CpuTest { #if AluImm diff --git a/Ryujinx.Tests/Cpu/CpuTestAluRs.cs b/Ryujinx.Tests/Cpu/CpuTestAluRs.cs index b81f7100c..880794cf8 100644 --- a/Ryujinx.Tests/Cpu/CpuTestAluRs.cs +++ b/Ryujinx.Tests/Cpu/CpuTestAluRs.cs @@ -9,7 +9,7 @@ namespace Ryujinx.Tests.Cpu using Tester; using Tester.Types; - [Category("AluRs"), Ignore("Tested: first half of 2018.")] + [Category("AluRs"), Ignore("Tested: second half of 2018.")] public sealed class CpuTestAluRs : CpuTest { #if AluRs diff --git a/Ryujinx.Tests/Cpu/CpuTestAluRx.cs b/Ryujinx.Tests/Cpu/CpuTestAluRx.cs index 26169bca6..d6cf8dc40 100644 --- a/Ryujinx.Tests/Cpu/CpuTestAluRx.cs +++ b/Ryujinx.Tests/Cpu/CpuTestAluRx.cs @@ -9,7 +9,7 @@ namespace Ryujinx.Tests.Cpu using Tester; using Tester.Types; - [Category("AluRx"), Ignore("Tested: first half of 2018.")] + [Category("AluRx"), Ignore("Tested: second half of 2018.")] public sealed class CpuTestAluRx : CpuTest { #if AluRx diff --git a/Ryujinx.Tests/Cpu/CpuTestBfm.cs b/Ryujinx.Tests/Cpu/CpuTestBfm.cs index 2952bca4c..0a2f9ad3a 100644 --- a/Ryujinx.Tests/Cpu/CpuTestBfm.cs +++ b/Ryujinx.Tests/Cpu/CpuTestBfm.cs @@ -9,7 +9,7 @@ namespace Ryujinx.Tests.Cpu using Tester; using Tester.Types; - [Category("Bfm"), Ignore("Tested: first half of 2018.")] + [Category("Bfm"), Ignore("Tested: second half of 2018.")] public sealed class CpuTestBfm : CpuTest { #if Bfm diff --git a/Ryujinx.Tests/Cpu/CpuTestCcmpImm.cs b/Ryujinx.Tests/Cpu/CpuTestCcmpImm.cs index 38d73878a..7ba44ed9c 100644 --- a/Ryujinx.Tests/Cpu/CpuTestCcmpImm.cs +++ b/Ryujinx.Tests/Cpu/CpuTestCcmpImm.cs @@ -9,7 +9,7 @@ namespace Ryujinx.Tests.Cpu using Tester; using Tester.Types; - [Category("CcmpImm"), Ignore("Tested: first half of 2018.")] + [Category("CcmpImm"), Ignore("Tested: second half of 2018.")] public sealed class CpuTestCcmpImm : CpuTest { #if CcmpImm diff --git a/Ryujinx.Tests/Cpu/CpuTestCcmpReg.cs b/Ryujinx.Tests/Cpu/CpuTestCcmpReg.cs index eb1c3abf2..82556464c 100644 --- a/Ryujinx.Tests/Cpu/CpuTestCcmpReg.cs +++ b/Ryujinx.Tests/Cpu/CpuTestCcmpReg.cs @@ -9,7 +9,7 @@ namespace Ryujinx.Tests.Cpu using Tester; using Tester.Types; - [Category("CcmpReg"), Ignore("Tested: first half of 2018.")] + [Category("CcmpReg"), Ignore("Tested: second half of 2018.")] public sealed class CpuTestCcmpReg : CpuTest { #if CcmpReg diff --git a/Ryujinx.Tests/Cpu/CpuTestCsel.cs b/Ryujinx.Tests/Cpu/CpuTestCsel.cs index 9dd61957f..fef56fee2 100644 --- a/Ryujinx.Tests/Cpu/CpuTestCsel.cs +++ b/Ryujinx.Tests/Cpu/CpuTestCsel.cs @@ -9,7 +9,7 @@ namespace Ryujinx.Tests.Cpu using Tester; using Tester.Types; - [Category("Csel"), Ignore("Tested: first half of 2018.")] + [Category("Csel"), Ignore("Tested: second half of 2018.")] public sealed class CpuTestCsel : CpuTest { #if Csel diff --git a/Ryujinx.Tests/Cpu/CpuTestMov.cs b/Ryujinx.Tests/Cpu/CpuTestMov.cs index 9c7e3255a..db544f865 100644 --- a/Ryujinx.Tests/Cpu/CpuTestMov.cs +++ b/Ryujinx.Tests/Cpu/CpuTestMov.cs @@ -9,7 +9,7 @@ namespace Ryujinx.Tests.Cpu using Tester; using Tester.Types; - [Category("Mov"), Ignore("Tested: first half of 2018.")] + [Category("Mov"), Ignore("Tested: second half of 2018.")] public sealed class CpuTestMov : CpuTest { #if Mov diff --git a/Ryujinx.Tests/Cpu/CpuTestMul.cs b/Ryujinx.Tests/Cpu/CpuTestMul.cs index 9bdc1fa65..19b8ecd0a 100644 --- a/Ryujinx.Tests/Cpu/CpuTestMul.cs +++ b/Ryujinx.Tests/Cpu/CpuTestMul.cs @@ -9,7 +9,7 @@ namespace Ryujinx.Tests.Cpu using Tester; using Tester.Types; - [Category("Mul"), Ignore("Tested: first half of 2018.")] + [Category("Mul"), Ignore("Tested: second half of 2018.")] public sealed class CpuTestMul : CpuTest { #if Mul diff --git a/Ryujinx.Tests/Cpu/CpuTestSimd.cs b/Ryujinx.Tests/Cpu/CpuTestSimd.cs index 88c5981cd..bb60273a7 100644 --- a/Ryujinx.Tests/Cpu/CpuTestSimd.cs +++ b/Ryujinx.Tests/Cpu/CpuTestSimd.cs @@ -90,7 +90,7 @@ namespace Ryujinx.Tests.Cpu private const int RndCnt = 1; [Test, Description("ABS , ")] - public void Abs_S_D([Values(0u)] uint Rd, + public void Abs_S_D([Values(0u)] uint Rd, [Values(1u, 0u)] uint Rn, [ValueSource("_1D_")] [Random(RndCnt)] ulong Z, [ValueSource("_1D_")] [Random(RndCnt)] ulong A) @@ -115,7 +115,7 @@ namespace Ryujinx.Tests.Cpu } [Test, Description("ABS ., .")] - public void Abs_V_8B_4H_2S([Values(0u)] uint Rd, + public void Abs_V_8B_4H_2S([Values(0u)] uint Rd, [Values(1u, 0u)] uint Rn, [ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong Z, [ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong A, @@ -142,7 +142,7 @@ namespace Ryujinx.Tests.Cpu } [Test, Description("ABS ., .")] - public void Abs_V_16B_8H_4S_2D([Values(0u)] uint Rd, + public void Abs_V_16B_8H_4S_2D([Values(0u)] uint Rd, [Values(1u, 0u)] uint Rn, [ValueSource("_8B4H2S1D_")] [Random(RndCnt)] ulong Z, [ValueSource("_8B4H2S1D_")] [Random(RndCnt)] ulong A, @@ -169,7 +169,7 @@ namespace Ryujinx.Tests.Cpu } [Test, Description("ADDP , .")] - public void Addp_S_2DD([Values(0u)] uint Rd, + public void Addp_S_2DD([Values(0u)] uint Rd, [Values(1u, 0u)] uint Rn, [ValueSource("_1D_")] [Random(RndCnt)] ulong Z, [ValueSource("_1D_")] [Random(RndCnt)] ulong A) @@ -194,7 +194,7 @@ namespace Ryujinx.Tests.Cpu } [Test, Description("ADDV , .")] - public void Addv_V_8BB_4HH([Values(0u)] uint Rd, + public void Addv_V_8BB_4HH([Values(0u)] uint Rd, [Values(1u, 0u)] uint Rn, [ValueSource("_8B4H_")] [Random(RndCnt)] ulong Z, [ValueSource("_8B4H_")] [Random(RndCnt)] ulong A, @@ -221,7 +221,7 @@ namespace Ryujinx.Tests.Cpu } [Test, Description("ADDV , .")] - public void Addv_V_16BB_8HH_4SS([Values(0u)] uint Rd, + public void Addv_V_16BB_8HH_4SS([Values(0u)] uint Rd, [Values(1u, 0u)] uint Rn, [ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong Z, [ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong A, @@ -248,7 +248,7 @@ namespace Ryujinx.Tests.Cpu } [Test, Description("CLS ., .")] - public void Cls_V_8B_4H_2S([Values(0u)] uint Rd, + public void Cls_V_8B_4H_2S([Values(0u)] uint Rd, [Values(1u, 0u)] uint Rn, [ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong Z, [ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong A, @@ -275,7 +275,7 @@ namespace Ryujinx.Tests.Cpu } [Test, Description("CLS ., .")] - public void Cls_V_16B_8H_4S([Values(0u)] uint Rd, + public void Cls_V_16B_8H_4S([Values(0u)] uint Rd, [Values(1u, 0u)] uint Rn, [ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong Z, [ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong A, @@ -302,7 +302,7 @@ namespace Ryujinx.Tests.Cpu } [Test, Description("CLZ ., .")] - public void Clz_V_8B_4H_2S([Values(0u)] uint Rd, + public void Clz_V_8B_4H_2S([Values(0u)] uint Rd, [Values(1u, 0u)] uint Rn, [ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong Z, [ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong A, @@ -329,7 +329,7 @@ namespace Ryujinx.Tests.Cpu } [Test, Description("CLZ ., .")] - public void Clz_V_16B_8H_4S([Values(0u)] uint Rd, + public void Clz_V_16B_8H_4S([Values(0u)] uint Rd, [Values(1u, 0u)] uint Rn, [ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong Z, [ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong A, @@ -356,7 +356,7 @@ namespace Ryujinx.Tests.Cpu } [Test, Description("CMEQ , , #0")] - public void Cmeq_S_D([Values(0u)] uint Rd, + public void Cmeq_S_D([Values(0u)] uint Rd, [Values(1u, 0u)] uint Rn, [ValueSource("_1D_")] [Random(RndCnt)] ulong Z, [ValueSource("_1D_")] [Random(RndCnt)] ulong A) @@ -381,7 +381,7 @@ namespace Ryujinx.Tests.Cpu } [Test, Description("CMEQ ., ., #0")] - public void Cmeq_V_8B_4H_2S([Values(0u)] uint Rd, + public void Cmeq_V_8B_4H_2S([Values(0u)] uint Rd, [Values(1u, 0u)] uint Rn, [ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong Z, [ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong A, @@ -408,7 +408,7 @@ namespace Ryujinx.Tests.Cpu } [Test, Description("CMEQ ., ., #0")] - public void Cmeq_V_16B_8H_4S_2D([Values(0u)] uint Rd, + public void Cmeq_V_16B_8H_4S_2D([Values(0u)] uint Rd, [Values(1u, 0u)] uint Rn, [ValueSource("_8B4H2S1D_")] [Random(RndCnt)] ulong Z, [ValueSource("_8B4H2S1D_")] [Random(RndCnt)] ulong A, @@ -435,7 +435,7 @@ namespace Ryujinx.Tests.Cpu } [Test, Description("CMGE , , #0")] - public void Cmge_S_D([Values(0u)] uint Rd, + public void Cmge_S_D([Values(0u)] uint Rd, [Values(1u, 0u)] uint Rn, [ValueSource("_1D_")] [Random(RndCnt)] ulong Z, [ValueSource("_1D_")] [Random(RndCnt)] ulong A) @@ -460,7 +460,7 @@ namespace Ryujinx.Tests.Cpu } [Test, Description("CMGE ., ., #0")] - public void Cmge_V_8B_4H_2S([Values(0u)] uint Rd, + public void Cmge_V_8B_4H_2S([Values(0u)] uint Rd, [Values(1u, 0u)] uint Rn, [ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong Z, [ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong A, @@ -487,7 +487,7 @@ namespace Ryujinx.Tests.Cpu } [Test, Description("CMGE ., ., #0")] - public void Cmge_V_16B_8H_4S_2D([Values(0u)] uint Rd, + public void Cmge_V_16B_8H_4S_2D([Values(0u)] uint Rd, [Values(1u, 0u)] uint Rn, [ValueSource("_8B4H2S1D_")] [Random(RndCnt)] ulong Z, [ValueSource("_8B4H2S1D_")] [Random(RndCnt)] ulong A, @@ -514,7 +514,7 @@ namespace Ryujinx.Tests.Cpu } [Test, Description("CMGT , , #0")] - public void Cmgt_S_D([Values(0u)] uint Rd, + public void Cmgt_S_D([Values(0u)] uint Rd, [Values(1u, 0u)] uint Rn, [ValueSource("_1D_")] [Random(RndCnt)] ulong Z, [ValueSource("_1D_")] [Random(RndCnt)] ulong A) @@ -539,7 +539,7 @@ namespace Ryujinx.Tests.Cpu } [Test, Description("CMGT ., ., #0")] - public void Cmgt_V_8B_4H_2S([Values(0u)] uint Rd, + public void Cmgt_V_8B_4H_2S([Values(0u)] uint Rd, [Values(1u, 0u)] uint Rn, [ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong Z, [ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong A, @@ -566,7 +566,7 @@ namespace Ryujinx.Tests.Cpu } [Test, Description("CMGT ., ., #0")] - public void Cmgt_V_16B_8H_4S_2D([Values(0u)] uint Rd, + public void Cmgt_V_16B_8H_4S_2D([Values(0u)] uint Rd, [Values(1u, 0u)] uint Rn, [ValueSource("_8B4H2S1D_")] [Random(RndCnt)] ulong Z, [ValueSource("_8B4H2S1D_")] [Random(RndCnt)] ulong A, @@ -593,7 +593,7 @@ namespace Ryujinx.Tests.Cpu } [Test, Description("CMLE , , #0")] - public void Cmle_S_D([Values(0u)] uint Rd, + public void Cmle_S_D([Values(0u)] uint Rd, [Values(1u, 0u)] uint Rn, [ValueSource("_1D_")] [Random(RndCnt)] ulong Z, [ValueSource("_1D_")] [Random(RndCnt)] ulong A) @@ -618,7 +618,7 @@ namespace Ryujinx.Tests.Cpu } [Test, Description("CMLE ., ., #0")] - public void Cmle_V_8B_4H_2S([Values(0u)] uint Rd, + public void Cmle_V_8B_4H_2S([Values(0u)] uint Rd, [Values(1u, 0u)] uint Rn, [ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong Z, [ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong A, @@ -645,7 +645,7 @@ namespace Ryujinx.Tests.Cpu } [Test, Description("CMLE ., ., #0")] - public void Cmle_V_16B_8H_4S_2D([Values(0u)] uint Rd, + public void Cmle_V_16B_8H_4S_2D([Values(0u)] uint Rd, [Values(1u, 0u)] uint Rn, [ValueSource("_8B4H2S1D_")] [Random(RndCnt)] ulong Z, [ValueSource("_8B4H2S1D_")] [Random(RndCnt)] ulong A, @@ -672,7 +672,7 @@ namespace Ryujinx.Tests.Cpu } [Test, Description("CMLT , , #0")] - public void Cmlt_S_D([Values(0u)] uint Rd, + public void Cmlt_S_D([Values(0u)] uint Rd, [Values(1u, 0u)] uint Rn, [ValueSource("_1D_")] [Random(RndCnt)] ulong Z, [ValueSource("_1D_")] [Random(RndCnt)] ulong A) @@ -697,7 +697,7 @@ namespace Ryujinx.Tests.Cpu } [Test, Description("CMLT ., ., #0")] - public void Cmlt_V_8B_4H_2S([Values(0u)] uint Rd, + public void Cmlt_V_8B_4H_2S([Values(0u)] uint Rd, [Values(1u, 0u)] uint Rn, [ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong Z, [ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong A, @@ -724,7 +724,7 @@ namespace Ryujinx.Tests.Cpu } [Test, Description("CMLT ., ., #0")] - public void Cmlt_V_16B_8H_4S_2D([Values(0u)] uint Rd, + public void Cmlt_V_16B_8H_4S_2D([Values(0u)] uint Rd, [Values(1u, 0u)] uint Rn, [ValueSource("_8B4H2S1D_")] [Random(RndCnt)] ulong Z, [ValueSource("_8B4H2S1D_")] [Random(RndCnt)] ulong A, @@ -751,7 +751,7 @@ namespace Ryujinx.Tests.Cpu } [Test, Description("CNT ., .")] - public void Cnt_V_8B([Values(0u)] uint Rd, + public void Cnt_V_8B([Values(0u)] uint Rd, [Values(1u, 0u)] uint Rn, [ValueSource("_8B_")] [Random(RndCnt)] ulong Z, [ValueSource("_8B_")] [Random(RndCnt)] ulong A) @@ -776,7 +776,7 @@ namespace Ryujinx.Tests.Cpu } [Test, Description("CNT ., .")] - public void Cnt_V_16B([Values(0u)] uint Rd, + public void Cnt_V_16B([Values(0u)] uint Rd, [Values(1u, 0u)] uint Rn, [ValueSource("_8B_")] [Random(RndCnt)] ulong Z, [ValueSource("_8B_")] [Random(RndCnt)] ulong A) @@ -801,7 +801,7 @@ namespace Ryujinx.Tests.Cpu } [Test, Description("NEG , ")] - public void Neg_S_D([Values(0u)] uint Rd, + public void Neg_S_D([Values(0u)] uint Rd, [Values(1u, 0u)] uint Rn, [ValueSource("_1D_")] [Random(RndCnt)] ulong Z, [ValueSource("_1D_")] [Random(RndCnt)] ulong A) @@ -826,7 +826,7 @@ namespace Ryujinx.Tests.Cpu } [Test, Description("NEG ., .")] - public void Neg_V_8B_4H_2S([Values(0u)] uint Rd, + public void Neg_V_8B_4H_2S([Values(0u)] uint Rd, [Values(1u, 0u)] uint Rn, [ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong Z, [ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong A, @@ -853,7 +853,7 @@ namespace Ryujinx.Tests.Cpu } [Test, Description("NEG ., .")] - public void Neg_V_16B_8H_4S_2D([Values(0u)] uint Rd, + public void Neg_V_16B_8H_4S_2D([Values(0u)] uint Rd, [Values(1u, 0u)] uint Rn, [ValueSource("_8B4H2S1D_")] [Random(RndCnt)] ulong Z, [ValueSource("_8B4H2S1D_")] [Random(RndCnt)] ulong A, @@ -880,7 +880,7 @@ namespace Ryujinx.Tests.Cpu } [Test, Description("NOT ., .")] - public void Not_V_8B([Values(0u)] uint Rd, + public void Not_V_8B([Values(0u)] uint Rd, [Values(1u, 0u)] uint Rn, [ValueSource("_8B_")] [Random(RndCnt)] ulong Z, [ValueSource("_8B_")] [Random(RndCnt)] ulong A) @@ -905,7 +905,7 @@ namespace Ryujinx.Tests.Cpu } [Test, Description("NOT ., .")] - public void Not_V_16B([Values(0u)] uint Rd, + public void Not_V_16B([Values(0u)] uint Rd, [Values(1u, 0u)] uint Rn, [ValueSource("_8B_")] [Random(RndCnt)] ulong Z, [ValueSource("_8B_")] [Random(RndCnt)] ulong A) @@ -930,7 +930,7 @@ namespace Ryujinx.Tests.Cpu } [Test, Description("RBIT ., .")] - public void Rbit_V_8B([Values(0u)] uint Rd, + public void Rbit_V_8B([Values(0u)] uint Rd, [Values(1u, 0u)] uint Rn, [ValueSource("_8B_")] [Random(RndCnt)] ulong Z, [ValueSource("_8B_")] [Random(RndCnt)] ulong A) @@ -955,7 +955,7 @@ namespace Ryujinx.Tests.Cpu } [Test, Description("RBIT ., .")] - public void Rbit_V_16B([Values(0u)] uint Rd, + public void Rbit_V_16B([Values(0u)] uint Rd, [Values(1u, 0u)] uint Rn, [ValueSource("_8B_")] [Random(RndCnt)] ulong Z, [ValueSource("_8B_")] [Random(RndCnt)] ulong A) @@ -980,7 +980,7 @@ namespace Ryujinx.Tests.Cpu } [Test, Description("REV16 ., .")] - public void Rev16_V_8B([Values(0u)] uint Rd, + public void Rev16_V_8B([Values(0u)] uint Rd, [Values(1u, 0u)] uint Rn, [ValueSource("_8B_")] [Random(RndCnt)] ulong Z, [ValueSource("_8B_")] [Random(RndCnt)] ulong A) @@ -1005,7 +1005,7 @@ namespace Ryujinx.Tests.Cpu } [Test, Description("REV16 ., .")] - public void Rev16_V_16B([Values(0u)] uint Rd, + public void Rev16_V_16B([Values(0u)] uint Rd, [Values(1u, 0u)] uint Rn, [ValueSource("_8B_")] [Random(RndCnt)] ulong Z, [ValueSource("_8B_")] [Random(RndCnt)] ulong A) @@ -1030,7 +1030,7 @@ namespace Ryujinx.Tests.Cpu } [Test, Description("REV32 ., .")] - public void Rev32_V_8B_4H([Values(0u)] uint Rd, + public void Rev32_V_8B_4H([Values(0u)] uint Rd, [Values(1u, 0u)] uint Rn, [ValueSource("_8B4H_")] [Random(RndCnt)] ulong Z, [ValueSource("_8B4H_")] [Random(RndCnt)] ulong A, @@ -1057,7 +1057,7 @@ namespace Ryujinx.Tests.Cpu } [Test, Description("REV32 ., .")] - public void Rev32_V_16B_8H([Values(0u)] uint Rd, + public void Rev32_V_16B_8H([Values(0u)] uint Rd, [Values(1u, 0u)] uint Rn, [ValueSource("_8B4H_")] [Random(RndCnt)] ulong Z, [ValueSource("_8B4H_")] [Random(RndCnt)] ulong A, @@ -1084,7 +1084,7 @@ namespace Ryujinx.Tests.Cpu } [Test, Description("REV64 ., .")] - public void Rev64_V_8B_4H_2S([Values(0u)] uint Rd, + public void Rev64_V_8B_4H_2S([Values(0u)] uint Rd, [Values(1u, 0u)] uint Rn, [ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong Z, [ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong A, @@ -1111,7 +1111,7 @@ namespace Ryujinx.Tests.Cpu } [Test, Description("REV64 ., .")] - public void Rev64_V_16B_8H_4S([Values(0u)] uint Rd, + public void Rev64_V_16B_8H_4S([Values(0u)] uint Rd, [Values(1u, 0u)] uint Rn, [ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong Z, [ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong A, @@ -1138,7 +1138,7 @@ namespace Ryujinx.Tests.Cpu } [Test, Description("SQABS , ")] - public void Sqabs_S_B_H_S_D([Values(0u)] uint Rd, + public void Sqabs_S_B_H_S_D([Values(0u)] uint Rd, [Values(1u, 0u)] uint Rn, [ValueSource("_1B1H1S1D_")] [Random(RndCnt)] ulong Z, [ValueSource("_1B1H1S1D_")] [Random(RndCnt)] ulong A, @@ -1169,7 +1169,7 @@ namespace Ryujinx.Tests.Cpu } [Test, Description("SQABS ., .")] - public void Sqabs_V_8B_4H_2S([Values(0u)] uint Rd, + public void Sqabs_V_8B_4H_2S([Values(0u)] uint Rd, [Values(1u, 0u)] uint Rn, [ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong Z, [ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong A, @@ -1200,7 +1200,7 @@ namespace Ryujinx.Tests.Cpu } [Test, Description("SQABS ., .")] - public void Sqabs_V_16B_8H_4S_2D([Values(0u)] uint Rd, + public void Sqabs_V_16B_8H_4S_2D([Values(0u)] uint Rd, [Values(1u, 0u)] uint Rn, [ValueSource("_8B4H2S1D_")] [Random(RndCnt)] ulong Z, [ValueSource("_8B4H2S1D_")] [Random(RndCnt)] ulong A, @@ -1231,7 +1231,7 @@ namespace Ryujinx.Tests.Cpu } [Test, Description("SQNEG , ")] - public void Sqneg_S_B_H_S_D([Values(0u)] uint Rd, + public void Sqneg_S_B_H_S_D([Values(0u)] uint Rd, [Values(1u, 0u)] uint Rn, [ValueSource("_1B1H1S1D_")] [Random(RndCnt)] ulong Z, [ValueSource("_1B1H1S1D_")] [Random(RndCnt)] ulong A, @@ -1262,7 +1262,7 @@ namespace Ryujinx.Tests.Cpu } [Test, Description("SQNEG ., .")] - public void Sqneg_V_8B_4H_2S([Values(0u)] uint Rd, + public void Sqneg_V_8B_4H_2S([Values(0u)] uint Rd, [Values(1u, 0u)] uint Rn, [ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong Z, [ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong A, @@ -1293,7 +1293,7 @@ namespace Ryujinx.Tests.Cpu } [Test, Description("SQNEG ., .")] - public void Sqneg_V_16B_8H_4S_2D([Values(0u)] uint Rd, + public void Sqneg_V_16B_8H_4S_2D([Values(0u)] uint Rd, [Values(1u, 0u)] uint Rn, [ValueSource("_8B4H2S1D_")] [Random(RndCnt)] ulong Z, [ValueSource("_8B4H2S1D_")] [Random(RndCnt)] ulong A, @@ -1324,7 +1324,7 @@ namespace Ryujinx.Tests.Cpu } [Test, Description("SQXTN , ")] - public void Sqxtn_S_HB_SH_DS([Values(0u)] uint Rd, + public void Sqxtn_S_HB_SH_DS([Values(0u)] uint Rd, [Values(1u, 0u)] uint Rn, [ValueSource("_1H1S1D_")] [Random(RndCnt)] ulong Z, [ValueSource("_1H1S1D_")] [Random(RndCnt)] ulong A, @@ -1355,7 +1355,7 @@ namespace Ryujinx.Tests.Cpu } [Test, Description("SQXTN{2} ., .")] - public void Sqxtn_V_8H8B_4S4H_2D2S([Values(0u)] uint Rd, + public void Sqxtn_V_8H8B_4S4H_2D2S([Values(0u)] uint Rd, [Values(1u, 0u)] uint Rn, [ValueSource("_4H2S1D_")] [Random(RndCnt)] ulong Z, [ValueSource("_4H2S1D_")] [Random(RndCnt)] ulong A, @@ -1386,7 +1386,7 @@ namespace Ryujinx.Tests.Cpu } [Test, Description("SQXTN{2} ., .")] - public void Sqxtn_V_8H16B_4S8H_2D4S([Values(0u)] uint Rd, + public void Sqxtn_V_8H16B_4S8H_2D4S([Values(0u)] uint Rd, [Values(1u, 0u)] uint Rn, [ValueSource("_4H2S1D_")] [Random(RndCnt)] ulong Z, [ValueSource("_4H2S1D_")] [Random(RndCnt)] ulong A, @@ -1417,7 +1417,7 @@ namespace Ryujinx.Tests.Cpu } [Test, Description("SQXTUN , ")] - public void Sqxtun_S_HB_SH_DS([Values(0u)] uint Rd, + public void Sqxtun_S_HB_SH_DS([Values(0u)] uint Rd, [Values(1u, 0u)] uint Rn, [ValueSource("_1H1S1D_")] [Random(RndCnt)] ulong Z, [ValueSource("_1H1S1D_")] [Random(RndCnt)] ulong A, @@ -1448,7 +1448,7 @@ namespace Ryujinx.Tests.Cpu } [Test, Description("SQXTUN{2} ., .")] - public void Sqxtun_V_8H8B_4S4H_2D2S([Values(0u)] uint Rd, + public void Sqxtun_V_8H8B_4S4H_2D2S([Values(0u)] uint Rd, [Values(1u, 0u)] uint Rn, [ValueSource("_4H2S1D_")] [Random(RndCnt)] ulong Z, [ValueSource("_4H2S1D_")] [Random(RndCnt)] ulong A, @@ -1479,7 +1479,7 @@ namespace Ryujinx.Tests.Cpu } [Test, Description("SQXTUN{2} ., .")] - public void Sqxtun_V_8H16B_4S8H_2D4S([Values(0u)] uint Rd, + public void Sqxtun_V_8H16B_4S8H_2D4S([Values(0u)] uint Rd, [Values(1u, 0u)] uint Rn, [ValueSource("_4H2S1D_")] [Random(RndCnt)] ulong Z, [ValueSource("_4H2S1D_")] [Random(RndCnt)] ulong A, @@ -1510,7 +1510,7 @@ namespace Ryujinx.Tests.Cpu } [Test, Description("SUQADD , ")] - public void Suqadd_S_B_H_S_D([Values(0u)] uint Rd, + public void Suqadd_S_B_H_S_D([Values(0u)] uint Rd, [Values(1u, 0u)] uint Rn, [ValueSource("_1B1H1S1D_")] [Random(RndCnt)] ulong Z, [ValueSource("_1B1H1S1D_")] [Random(RndCnt)] ulong A, @@ -1541,7 +1541,7 @@ namespace Ryujinx.Tests.Cpu } [Test, Description("SUQADD ., .")] - public void Suqadd_V_8B_4H_2S([Values(0u)] uint Rd, + public void Suqadd_V_8B_4H_2S([Values(0u)] uint Rd, [Values(1u, 0u)] uint Rn, [ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong Z, [ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong A, @@ -1572,7 +1572,7 @@ namespace Ryujinx.Tests.Cpu } [Test, Description("SUQADD ., .")] - public void Suqadd_V_16B_8H_4S_2D([Values(0u)] uint Rd, + public void Suqadd_V_16B_8H_4S_2D([Values(0u)] uint Rd, [Values(1u, 0u)] uint Rn, [ValueSource("_8B4H2S1D_")] [Random(RndCnt)] ulong Z, [ValueSource("_8B4H2S1D_")] [Random(RndCnt)] ulong A, @@ -1603,7 +1603,7 @@ namespace Ryujinx.Tests.Cpu } [Test, Description("UQXTN , ")] - public void Uqxtn_S_HB_SH_DS([Values(0u)] uint Rd, + public void Uqxtn_S_HB_SH_DS([Values(0u)] uint Rd, [Values(1u, 0u)] uint Rn, [ValueSource("_1H1S1D_")] [Random(RndCnt)] ulong Z, [ValueSource("_1H1S1D_")] [Random(RndCnt)] ulong A, @@ -1634,7 +1634,7 @@ namespace Ryujinx.Tests.Cpu } [Test, Description("UQXTN{2} ., .")] - public void Uqxtn_V_8H8B_4S4H_2D2S([Values(0u)] uint Rd, + public void Uqxtn_V_8H8B_4S4H_2D2S([Values(0u)] uint Rd, [Values(1u, 0u)] uint Rn, [ValueSource("_4H2S1D_")] [Random(RndCnt)] ulong Z, [ValueSource("_4H2S1D_")] [Random(RndCnt)] ulong A, @@ -1665,7 +1665,7 @@ namespace Ryujinx.Tests.Cpu } [Test, Description("UQXTN{2} ., .")] - public void Uqxtn_V_8H16B_4S8H_2D4S([Values(0u)] uint Rd, + public void Uqxtn_V_8H16B_4S8H_2D4S([Values(0u)] uint Rd, [Values(1u, 0u)] uint Rn, [ValueSource("_4H2S1D_")] [Random(RndCnt)] ulong Z, [ValueSource("_4H2S1D_")] [Random(RndCnt)] ulong A, @@ -1696,7 +1696,7 @@ namespace Ryujinx.Tests.Cpu } [Test, Description("USQADD , ")] - public void Usqadd_S_B_H_S_D([Values(0u)] uint Rd, + public void Usqadd_S_B_H_S_D([Values(0u)] uint Rd, [Values(1u, 0u)] uint Rn, [ValueSource("_1B1H1S1D_")] [Random(RndCnt)] ulong Z, [ValueSource("_1B1H1S1D_")] [Random(RndCnt)] ulong A, @@ -1727,7 +1727,7 @@ namespace Ryujinx.Tests.Cpu } [Test, Description("USQADD ., .")] - public void Usqadd_V_8B_4H_2S([Values(0u)] uint Rd, + public void Usqadd_V_8B_4H_2S([Values(0u)] uint Rd, [Values(1u, 0u)] uint Rn, [ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong Z, [ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong A, @@ -1758,7 +1758,7 @@ namespace Ryujinx.Tests.Cpu } [Test, Description("USQADD ., .")] - public void Usqadd_V_16B_8H_4S_2D([Values(0u)] uint Rd, + public void Usqadd_V_16B_8H_4S_2D([Values(0u)] uint Rd, [Values(1u, 0u)] uint Rn, [ValueSource("_8B4H2S1D_")] [Random(RndCnt)] ulong Z, [ValueSource("_8B4H2S1D_")] [Random(RndCnt)] ulong A, @@ -1789,7 +1789,7 @@ namespace Ryujinx.Tests.Cpu } [Test, Description("XTN{2} ., .")] - public void Xtn_V_8H8B_4S4H_2D2S([Values(0u)] uint Rd, + public void Xtn_V_8H8B_4S4H_2D2S([Values(0u)] uint Rd, [Values(1u, 0u)] uint Rn, [ValueSource("_4H2S1D_")] [Random(RndCnt)] ulong Z, [ValueSource("_4H2S1D_")] [Random(RndCnt)] ulong A, @@ -1816,7 +1816,7 @@ namespace Ryujinx.Tests.Cpu } [Test, Description("XTN{2} ., .")] - public void Xtn_V_8H16B_4S8H_2D4S([Values(0u)] uint Rd, + public void Xtn_V_8H16B_4S8H_2D4S([Values(0u)] uint Rd, [Values(1u, 0u)] uint Rn, [ValueSource("_4H2S1D_")] [Random(RndCnt)] ulong Z, [ValueSource("_4H2S1D_")] [Random(RndCnt)] ulong A, diff --git a/Ryujinx.Tests/Cpu/CpuTestSimdReg.cs b/Ryujinx.Tests/Cpu/CpuTestSimdReg.cs index e6cfcbde5..c1cf812e4 100644 --- a/Ryujinx.Tests/Cpu/CpuTestSimdReg.cs +++ b/Ryujinx.Tests/Cpu/CpuTestSimdReg.cs @@ -39,6 +39,21 @@ namespace Ryujinx.Tests.Cpu 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul }; } + private static ulong[] _1H1S_() + { + return new ulong[] { 0x0000000000000000ul, 0x0000000000007FFFul, + 0x0000000000008000ul, 0x000000000000FFFFul, + 0x000000007FFFFFFFul, 0x0000000080000000ul, + 0x00000000FFFFFFFFul }; + } + + private static ulong[] _4H2S_() + { + return new ulong[] { 0x0000000000000000ul, 0x7FFF7FFF7FFF7FFFul, + 0x8000800080008000ul, 0x7FFFFFFF7FFFFFFFul, + 0x8000000080000000ul, 0xFFFFFFFFFFFFFFFFul }; + } + private static ulong[] _4H2S1D_() { return new ulong[] { 0x0000000000000000ul, 0x7FFF7FFF7FFF7FFFul, @@ -74,7 +89,7 @@ namespace Ryujinx.Tests.Cpu private const int RndCnt = 4; [Test, Pairwise, Description("ADD , , ")] - public void Add_S_D([Values(0u)] uint Rd, + public void Add_S_D([Values(0u)] uint Rd, [Values(1u, 0u)] uint Rn, [Values(2u, 0u)] uint Rm, [ValueSource("_1D_")] [Random(RndCnt)] ulong Z, @@ -103,7 +118,7 @@ namespace Ryujinx.Tests.Cpu } [Test, Pairwise, Description("ADD ., ., .")] - public void Add_V_8B_4H_2S([Values(0u)] uint Rd, + public void Add_V_8B_4H_2S([Values(0u)] uint Rd, [Values(1u, 0u)] uint Rn, [Values(2u, 0u)] uint Rm, [ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong Z, @@ -134,7 +149,7 @@ namespace Ryujinx.Tests.Cpu } [Test, Pairwise, Description("ADD ., ., .")] - public void Add_V_16B_8H_4S_2D([Values(0u)] uint Rd, + public void Add_V_16B_8H_4S_2D([Values(0u)] uint Rd, [Values(1u, 0u)] uint Rn, [Values(2u, 0u)] uint Rm, [ValueSource("_8B4H2S1D_")] [Random(RndCnt)] ulong Z, @@ -165,7 +180,7 @@ namespace Ryujinx.Tests.Cpu } [Test, Pairwise, Description("ADDHN{2} ., ., .")] - public void Addhn_V_8H8B_4S4H_2D2S([Values(0u)] uint Rd, + public void Addhn_V_8H8B_4S4H_2D2S([Values(0u)] uint Rd, [Values(1u, 0u)] uint Rn, [Values(2u, 0u)] uint Rm, [ValueSource("_4H2S1D_")] [Random(RndCnt)] ulong Z, @@ -196,7 +211,7 @@ namespace Ryujinx.Tests.Cpu } [Test, Pairwise, Description("ADDHN{2} ., ., .")] - public void Addhn_V_8H16B_4S8H_2D4S([Values(0u)] uint Rd, + public void Addhn_V_8H16B_4S8H_2D4S([Values(0u)] uint Rd, [Values(1u, 0u)] uint Rn, [Values(2u, 0u)] uint Rm, [ValueSource("_4H2S1D_")] [Random(RndCnt)] ulong Z, @@ -227,7 +242,7 @@ namespace Ryujinx.Tests.Cpu } [Test, Pairwise, Description("ADDP ., ., .")] - public void Addp_V_8B_4H_2S([Values(0u)] uint Rd, + public void Addp_V_8B_4H_2S([Values(0u)] uint Rd, [Values(1u, 0u)] uint Rn, [Values(2u, 0u)] uint Rm, [ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong Z, @@ -258,7 +273,7 @@ namespace Ryujinx.Tests.Cpu } [Test, Pairwise, Description("ADDP ., ., .")] - public void Addp_V_16B_8H_4S_2D([Values(0u)] uint Rd, + public void Addp_V_16B_8H_4S_2D([Values(0u)] uint Rd, [Values(1u, 0u)] uint Rn, [Values(2u, 0u)] uint Rm, [ValueSource("_8B4H2S1D_")] [Random(RndCnt)] ulong Z, @@ -289,7 +304,7 @@ namespace Ryujinx.Tests.Cpu } [Test, Pairwise, Description("AND ., ., .")] - public void And_V_8B([Values(0u)] uint Rd, + public void And_V_8B([Values(0u)] uint Rd, [Values(1u, 0u)] uint Rn, [Values(2u, 0u)] uint Rm, [ValueSource("_8B_")] [Random(RndCnt)] ulong Z, @@ -318,7 +333,7 @@ namespace Ryujinx.Tests.Cpu } [Test, Pairwise, Description("AND ., ., .")] - public void And_V_16B([Values(0u)] uint Rd, + public void And_V_16B([Values(0u)] uint Rd, [Values(1u, 0u)] uint Rn, [Values(2u, 0u)] uint Rm, [ValueSource("_8B_")] [Random(RndCnt)] ulong Z, @@ -347,7 +362,7 @@ namespace Ryujinx.Tests.Cpu } [Test, Pairwise, Description("BIC ., ., .")] - public void Bic_V_8B([Values(0u)] uint Rd, + public void Bic_V_8B([Values(0u)] uint Rd, [Values(1u, 0u)] uint Rn, [Values(2u, 0u)] uint Rm, [ValueSource("_8B_")] [Random(RndCnt)] ulong Z, @@ -376,7 +391,7 @@ namespace Ryujinx.Tests.Cpu } [Test, Pairwise, Description("BIC ., ., .")] - public void Bic_V_16B([Values(0u)] uint Rd, + public void Bic_V_16B([Values(0u)] uint Rd, [Values(1u, 0u)] uint Rn, [Values(2u, 0u)] uint Rm, [ValueSource("_8B_")] [Random(RndCnt)] ulong Z, @@ -405,7 +420,7 @@ namespace Ryujinx.Tests.Cpu } [Test, Pairwise, Description("BIF ., ., .")] - public void Bif_V_8B([Values(0u)] uint Rd, + public void Bif_V_8B([Values(0u)] uint Rd, [Values(1u, 0u)] uint Rn, [Values(2u, 0u)] uint Rm, [ValueSource("_8B_")] [Random(RndCnt)] ulong Z, @@ -434,7 +449,7 @@ namespace Ryujinx.Tests.Cpu } [Test, Pairwise, Description("BIF ., ., .")] - public void Bif_V_16B([Values(0u)] uint Rd, + public void Bif_V_16B([Values(0u)] uint Rd, [Values(1u, 0u)] uint Rn, [Values(2u, 0u)] uint Rm, [ValueSource("_8B_")] [Random(RndCnt)] ulong Z, @@ -463,7 +478,7 @@ namespace Ryujinx.Tests.Cpu } [Test, Pairwise, Description("BIT ., ., .")] - public void Bit_V_8B([Values(0u)] uint Rd, + public void Bit_V_8B([Values(0u)] uint Rd, [Values(1u, 0u)] uint Rn, [Values(2u, 0u)] uint Rm, [ValueSource("_8B_")] [Random(RndCnt)] ulong Z, @@ -492,7 +507,7 @@ namespace Ryujinx.Tests.Cpu } [Test, Pairwise, Description("BIT ., ., .")] - public void Bit_V_16B([Values(0u)] uint Rd, + public void Bit_V_16B([Values(0u)] uint Rd, [Values(1u, 0u)] uint Rn, [Values(2u, 0u)] uint Rm, [ValueSource("_8B_")] [Random(RndCnt)] ulong Z, @@ -521,7 +536,7 @@ namespace Ryujinx.Tests.Cpu } [Test, Pairwise, Description("BSL ., ., .")] - public void Bsl_V_8B([Values(0u)] uint Rd, + public void Bsl_V_8B([Values(0u)] uint Rd, [Values(1u, 0u)] uint Rn, [Values(2u, 0u)] uint Rm, [ValueSource("_8B_")] [Random(RndCnt)] ulong Z, @@ -550,7 +565,7 @@ namespace Ryujinx.Tests.Cpu } [Test, Pairwise, Description("BSL ., ., .")] - public void Bsl_V_16B([Values(0u)] uint Rd, + public void Bsl_V_16B([Values(0u)] uint Rd, [Values(1u, 0u)] uint Rn, [Values(2u, 0u)] uint Rm, [ValueSource("_8B_")] [Random(RndCnt)] ulong Z, @@ -579,7 +594,7 @@ namespace Ryujinx.Tests.Cpu } [Test, Pairwise, Description("CMEQ , , ")] - public void Cmeq_S_D([Values(0u)] uint Rd, + public void Cmeq_S_D([Values(0u)] uint Rd, [Values(1u, 0u)] uint Rn, [Values(2u, 0u)] uint Rm, [ValueSource("_1D_")] [Random(RndCnt)] ulong Z, @@ -608,7 +623,7 @@ namespace Ryujinx.Tests.Cpu } [Test, Pairwise, Description("CMEQ ., ., .")] - public void Cmeq_V_8B_4H_2S([Values(0u)] uint Rd, + public void Cmeq_V_8B_4H_2S([Values(0u)] uint Rd, [Values(1u, 0u)] uint Rn, [Values(2u, 0u)] uint Rm, [ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong Z, @@ -639,7 +654,7 @@ namespace Ryujinx.Tests.Cpu } [Test, Pairwise, Description("CMEQ ., ., .")] - public void Cmeq_V_16B_8H_4S_2D([Values(0u)] uint Rd, + public void Cmeq_V_16B_8H_4S_2D([Values(0u)] uint Rd, [Values(1u, 0u)] uint Rn, [Values(2u, 0u)] uint Rm, [ValueSource("_8B4H2S1D_")] [Random(RndCnt)] ulong Z, @@ -670,7 +685,7 @@ namespace Ryujinx.Tests.Cpu } [Test, Pairwise, Description("CMGE , , ")] - public void Cmge_S_D([Values(0u)] uint Rd, + public void Cmge_S_D([Values(0u)] uint Rd, [Values(1u, 0u)] uint Rn, [Values(2u, 0u)] uint Rm, [ValueSource("_1D_")] [Random(RndCnt)] ulong Z, @@ -699,7 +714,7 @@ namespace Ryujinx.Tests.Cpu } [Test, Pairwise, Description("CMGE ., ., .")] - public void Cmge_V_8B_4H_2S([Values(0u)] uint Rd, + public void Cmge_V_8B_4H_2S([Values(0u)] uint Rd, [Values(1u, 0u)] uint Rn, [Values(2u, 0u)] uint Rm, [ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong Z, @@ -730,7 +745,7 @@ namespace Ryujinx.Tests.Cpu } [Test, Pairwise, Description("CMGE ., ., .")] - public void Cmge_V_16B_8H_4S_2D([Values(0u)] uint Rd, + public void Cmge_V_16B_8H_4S_2D([Values(0u)] uint Rd, [Values(1u, 0u)] uint Rn, [Values(2u, 0u)] uint Rm, [ValueSource("_8B4H2S1D_")] [Random(RndCnt)] ulong Z, @@ -761,7 +776,7 @@ namespace Ryujinx.Tests.Cpu } [Test, Pairwise, Description("CMGT , , ")] - public void Cmgt_S_D([Values(0u)] uint Rd, + public void Cmgt_S_D([Values(0u)] uint Rd, [Values(1u, 0u)] uint Rn, [Values(2u, 0u)] uint Rm, [ValueSource("_1D_")] [Random(RndCnt)] ulong Z, @@ -790,7 +805,7 @@ namespace Ryujinx.Tests.Cpu } [Test, Pairwise, Description("CMGT ., ., .")] - public void Cmgt_V_8B_4H_2S([Values(0u)] uint Rd, + public void Cmgt_V_8B_4H_2S([Values(0u)] uint Rd, [Values(1u, 0u)] uint Rn, [Values(2u, 0u)] uint Rm, [ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong Z, @@ -821,7 +836,7 @@ namespace Ryujinx.Tests.Cpu } [Test, Pairwise, Description("CMGT ., ., .")] - public void Cmgt_V_16B_8H_4S_2D([Values(0u)] uint Rd, + public void Cmgt_V_16B_8H_4S_2D([Values(0u)] uint Rd, [Values(1u, 0u)] uint Rn, [Values(2u, 0u)] uint Rm, [ValueSource("_8B4H2S1D_")] [Random(RndCnt)] ulong Z, @@ -852,7 +867,7 @@ namespace Ryujinx.Tests.Cpu } [Test, Pairwise, Description("CMHI , , ")] - public void Cmhi_S_D([Values(0u)] uint Rd, + public void Cmhi_S_D([Values(0u)] uint Rd, [Values(1u, 0u)] uint Rn, [Values(2u, 0u)] uint Rm, [ValueSource("_1D_")] [Random(RndCnt)] ulong Z, @@ -881,7 +896,7 @@ namespace Ryujinx.Tests.Cpu } [Test, Pairwise, Description("CMHI ., ., .")] - public void Cmhi_V_8B_4H_2S([Values(0u)] uint Rd, + public void Cmhi_V_8B_4H_2S([Values(0u)] uint Rd, [Values(1u, 0u)] uint Rn, [Values(2u, 0u)] uint Rm, [ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong Z, @@ -912,7 +927,7 @@ namespace Ryujinx.Tests.Cpu } [Test, Pairwise, Description("CMHI ., ., .")] - public void Cmhi_V_16B_8H_4S_2D([Values(0u)] uint Rd, + public void Cmhi_V_16B_8H_4S_2D([Values(0u)] uint Rd, [Values(1u, 0u)] uint Rn, [Values(2u, 0u)] uint Rm, [ValueSource("_8B4H2S1D_")] [Random(RndCnt)] ulong Z, @@ -943,7 +958,7 @@ namespace Ryujinx.Tests.Cpu } [Test, Pairwise, Description("CMHS , , ")] - public void Cmhs_S_D([Values(0u)] uint Rd, + public void Cmhs_S_D([Values(0u)] uint Rd, [Values(1u, 0u)] uint Rn, [Values(2u, 0u)] uint Rm, [ValueSource("_1D_")] [Random(RndCnt)] ulong Z, @@ -972,7 +987,7 @@ namespace Ryujinx.Tests.Cpu } [Test, Pairwise, Description("CMHS ., ., .")] - public void Cmhs_V_8B_4H_2S([Values(0u)] uint Rd, + public void Cmhs_V_8B_4H_2S([Values(0u)] uint Rd, [Values(1u, 0u)] uint Rn, [Values(2u, 0u)] uint Rm, [ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong Z, @@ -1003,7 +1018,7 @@ namespace Ryujinx.Tests.Cpu } [Test, Pairwise, Description("CMHS ., ., .")] - public void Cmhs_V_16B_8H_4S_2D([Values(0u)] uint Rd, + public void Cmhs_V_16B_8H_4S_2D([Values(0u)] uint Rd, [Values(1u, 0u)] uint Rn, [Values(2u, 0u)] uint Rm, [ValueSource("_8B4H2S1D_")] [Random(RndCnt)] ulong Z, @@ -1034,7 +1049,7 @@ namespace Ryujinx.Tests.Cpu } [Test, Pairwise, Description("CMTST , , ")] - public void Cmtst_S_D([Values(0u)] uint Rd, + public void Cmtst_S_D([Values(0u)] uint Rd, [Values(1u, 0u)] uint Rn, [Values(2u, 0u)] uint Rm, [ValueSource("_1D_")] [Random(RndCnt)] ulong Z, @@ -1063,7 +1078,7 @@ namespace Ryujinx.Tests.Cpu } [Test, Pairwise, Description("CMTST ., ., .")] - public void Cmtst_V_8B_4H_2S([Values(0u)] uint Rd, + public void Cmtst_V_8B_4H_2S([Values(0u)] uint Rd, [Values(1u, 0u)] uint Rn, [Values(2u, 0u)] uint Rm, [ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong Z, @@ -1094,7 +1109,7 @@ namespace Ryujinx.Tests.Cpu } [Test, Pairwise, Description("CMTST ., ., .")] - public void Cmtst_V_16B_8H_4S_2D([Values(0u)] uint Rd, + public void Cmtst_V_16B_8H_4S_2D([Values(0u)] uint Rd, [Values(1u, 0u)] uint Rn, [Values(2u, 0u)] uint Rm, [ValueSource("_8B4H2S1D_")] [Random(RndCnt)] ulong Z, @@ -1125,7 +1140,7 @@ namespace Ryujinx.Tests.Cpu } [Test, Pairwise, Description("EOR ., ., .")] - public void Eor_V_8B([Values(0u)] uint Rd, + public void Eor_V_8B([Values(0u)] uint Rd, [Values(1u, 0u)] uint Rn, [Values(2u, 0u)] uint Rm, [ValueSource("_8B_")] [Random(RndCnt)] ulong Z, @@ -1154,7 +1169,7 @@ namespace Ryujinx.Tests.Cpu } [Test, Pairwise, Description("EOR ., ., .")] - public void Eor_V_16B([Values(0u)] uint Rd, + public void Eor_V_16B([Values(0u)] uint Rd, [Values(1u, 0u)] uint Rn, [Values(2u, 0u)] uint Rm, [ValueSource("_8B_")] [Random(RndCnt)] ulong Z, @@ -1183,7 +1198,7 @@ namespace Ryujinx.Tests.Cpu } [Test, Pairwise, Description("ORN ., ., .")] - public void Orn_V_8B([Values(0u)] uint Rd, + public void Orn_V_8B([Values(0u)] uint Rd, [Values(1u, 0u)] uint Rn, [Values(2u, 0u)] uint Rm, [ValueSource("_8B_")] [Random(RndCnt)] ulong Z, @@ -1212,7 +1227,7 @@ namespace Ryujinx.Tests.Cpu } [Test, Pairwise, Description("ORN ., ., .")] - public void Orn_V_16B([Values(0u)] uint Rd, + public void Orn_V_16B([Values(0u)] uint Rd, [Values(1u, 0u)] uint Rn, [Values(2u, 0u)] uint Rm, [ValueSource("_8B_")] [Random(RndCnt)] ulong Z, @@ -1241,7 +1256,7 @@ namespace Ryujinx.Tests.Cpu } [Test, Pairwise, Description("ORR ., ., .")] - public void Orr_V_8B([Values(0u)] uint Rd, + public void Orr_V_8B([Values(0u)] uint Rd, [Values(1u, 0u)] uint Rn, [Values(2u, 0u)] uint Rm, [ValueSource("_8B_")] [Random(RndCnt)] ulong Z, @@ -1270,7 +1285,7 @@ namespace Ryujinx.Tests.Cpu } [Test, Pairwise, Description("ORR ., ., .")] - public void Orr_V_16B([Values(0u)] uint Rd, + public void Orr_V_16B([Values(0u)] uint Rd, [Values(1u, 0u)] uint Rn, [Values(2u, 0u)] uint Rm, [ValueSource("_8B_")] [Random(RndCnt)] ulong Z, @@ -1299,7 +1314,7 @@ namespace Ryujinx.Tests.Cpu } [Test, Pairwise, Description("RADDHN{2} ., ., .")] - public void Raddhn_V_8H8B_4S4H_2D2S([Values(0u)] uint Rd, + public void Raddhn_V_8H8B_4S4H_2D2S([Values(0u)] uint Rd, [Values(1u, 0u)] uint Rn, [Values(2u, 0u)] uint Rm, [ValueSource("_4H2S1D_")] [Random(RndCnt)] ulong Z, @@ -1330,7 +1345,7 @@ namespace Ryujinx.Tests.Cpu } [Test, Pairwise, Description("RADDHN{2} ., ., .")] - public void Raddhn_V_8H16B_4S8H_2D4S([Values(0u)] uint Rd, + public void Raddhn_V_8H16B_4S8H_2D4S([Values(0u)] uint Rd, [Values(1u, 0u)] uint Rn, [Values(2u, 0u)] uint Rm, [ValueSource("_4H2S1D_")] [Random(RndCnt)] ulong Z, @@ -1361,7 +1376,7 @@ namespace Ryujinx.Tests.Cpu } [Test, Pairwise, Description("RSUBHN{2} ., ., .")] - public void Rsubhn_V_8H8B_4S4H_2D2S([Values(0u)] uint Rd, + public void Rsubhn_V_8H8B_4S4H_2D2S([Values(0u)] uint Rd, [Values(1u, 0u)] uint Rn, [Values(2u, 0u)] uint Rm, [ValueSource("_4H2S1D_")] [Random(RndCnt)] ulong Z, @@ -1392,7 +1407,7 @@ namespace Ryujinx.Tests.Cpu } [Test, Pairwise, Description("RSUBHN{2} ., ., .")] - public void Rsubhn_V_8H16B_4S8H_2D4S([Values(0u)] uint Rd, + public void Rsubhn_V_8H16B_4S8H_2D4S([Values(0u)] uint Rd, [Values(1u, 0u)] uint Rn, [Values(2u, 0u)] uint Rm, [ValueSource("_4H2S1D_")] [Random(RndCnt)] ulong Z, @@ -1423,7 +1438,7 @@ namespace Ryujinx.Tests.Cpu } [Test, Pairwise, Description("SABA ., ., .")] - public void Saba_V_8B_4H_2S([Values(0u)] uint Rd, + public void Saba_V_8B_4H_2S([Values(0u)] uint Rd, [Values(1u, 0u)] uint Rn, [Values(2u, 0u)] uint Rm, [ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong Z, @@ -1454,7 +1469,7 @@ namespace Ryujinx.Tests.Cpu } [Test, Pairwise, Description("SABA ., ., .")] - public void Saba_V_16B_8H_4S([Values(0u)] uint Rd, + public void Saba_V_16B_8H_4S([Values(0u)] uint Rd, [Values(1u, 0u)] uint Rn, [Values(2u, 0u)] uint Rm, [ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong Z, @@ -1485,7 +1500,7 @@ namespace Ryujinx.Tests.Cpu } [Test, Pairwise, Description("SABAL{2} ., ., .")] - public void Sabal_V_8B8H_4H4S_2S2D([Values(0u)] uint Rd, + public void Sabal_V_8B8H_4H4S_2S2D([Values(0u)] uint Rd, [Values(1u, 0u)] uint Rn, [Values(2u, 0u)] uint Rm, [ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong Z, @@ -1516,7 +1531,7 @@ namespace Ryujinx.Tests.Cpu } [Test, Pairwise, Description("SABAL{2} ., ., .")] - public void Sabal_V_16B8H_8H4S_4S2D([Values(0u)] uint Rd, + public void Sabal_V_16B8H_8H4S_4S2D([Values(0u)] uint Rd, [Values(1u, 0u)] uint Rn, [Values(2u, 0u)] uint Rm, [ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong Z, @@ -1547,7 +1562,7 @@ namespace Ryujinx.Tests.Cpu } [Test, Pairwise, Description("SABD ., ., .")] - public void Sabd_V_8B_4H_2S([Values(0u)] uint Rd, + public void Sabd_V_8B_4H_2S([Values(0u)] uint Rd, [Values(1u, 0u)] uint Rn, [Values(2u, 0u)] uint Rm, [ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong Z, @@ -1578,7 +1593,7 @@ namespace Ryujinx.Tests.Cpu } [Test, Pairwise, Description("SABD ., ., .")] - public void Sabd_V_16B_8H_4S([Values(0u)] uint Rd, + public void Sabd_V_16B_8H_4S([Values(0u)] uint Rd, [Values(1u, 0u)] uint Rn, [Values(2u, 0u)] uint Rm, [ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong Z, @@ -1609,7 +1624,7 @@ namespace Ryujinx.Tests.Cpu } [Test, Pairwise, Description("SABDL{2} ., ., .")] - public void Sabdl_V_8B8H_4H4S_2S2D([Values(0u)] uint Rd, + public void Sabdl_V_8B8H_4H4S_2S2D([Values(0u)] uint Rd, [Values(1u, 0u)] uint Rn, [Values(2u, 0u)] uint Rm, [ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong Z, @@ -1640,7 +1655,7 @@ namespace Ryujinx.Tests.Cpu } [Test, Pairwise, Description("SABDL{2} ., ., .")] - public void Sabdl_V_16B8H_8H4S_4S2D([Values(0u)] uint Rd, + public void Sabdl_V_16B8H_8H4S_4S2D([Values(0u)] uint Rd, [Values(1u, 0u)] uint Rn, [Values(2u, 0u)] uint Rm, [ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong Z, @@ -1671,7 +1686,7 @@ namespace Ryujinx.Tests.Cpu } [Test, Pairwise, Description("SADDW{2} ., ., .")] - public void Saddw_V_8B8H8H_4H4S4S_2S2D2D([Values(0u)] uint Rd, + public void Saddw_V_8B8H8H_4H4S4S_2S2D2D([Values(0u)] uint Rd, [Values(1u, 0u)] uint Rn, [Values(2u, 0u)] uint Rm, [ValueSource("_8B4H2S1D_")] [Random(RndCnt)] ulong Z, @@ -1702,7 +1717,7 @@ namespace Ryujinx.Tests.Cpu } [Test, Pairwise, Description("SADDW{2} ., ., .")] - public void Saddw_V_16B8H8H_8H4S4S_4S2D2D([Values(0u)] uint Rd, + public void Saddw_V_16B8H8H_8H4S4S_4S2D2D([Values(0u)] uint Rd, [Values(1u, 0u)] uint Rn, [Values(2u, 0u)] uint Rm, [ValueSource("_8B4H2S1D_")] [Random(RndCnt)] ulong Z, @@ -1733,7 +1748,7 @@ namespace Ryujinx.Tests.Cpu } [Test, Pairwise, Description("SQADD , , ")] - public void Sqadd_S_B_H_S_D([Values(0u)] uint Rd, + public void Sqadd_S_B_H_S_D([Values(0u)] uint Rd, [Values(1u, 0u)] uint Rn, [Values(2u, 0u)] uint Rm, [ValueSource("_1B1H1S1D_")] [Random(RndCnt)] ulong Z, @@ -1768,7 +1783,7 @@ namespace Ryujinx.Tests.Cpu } [Test, Pairwise, Description("SQADD ., ., .")] - public void Sqadd_V_8B_4H_2S([Values(0u)] uint Rd, + public void Sqadd_V_8B_4H_2S([Values(0u)] uint Rd, [Values(1u, 0u)] uint Rn, [Values(2u, 0u)] uint Rm, [ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong Z, @@ -1803,7 +1818,7 @@ namespace Ryujinx.Tests.Cpu } [Test, Pairwise, Description("SQADD ., ., .")] - public void Sqadd_V_16B_8H_4S_2D([Values(0u)] uint Rd, + public void Sqadd_V_16B_8H_4S_2D([Values(0u)] uint Rd, [Values(1u, 0u)] uint Rn, [Values(2u, 0u)] uint Rm, [ValueSource("_8B4H2S1D_")] [Random(RndCnt)] ulong Z, @@ -1837,8 +1852,218 @@ namespace Ryujinx.Tests.Cpu Assert.That(ThreadState.Fpsr, Is.EqualTo((int)Shared.FPSR.ToUInt32())); } + [Test, Pairwise, Description("SQDMULH , , ")] + public void Sqdmulh_S_H_S([Values(0u)] uint Rd, + [Values(1u, 0u)] uint Rn, + [Values(2u, 0u)] uint Rm, + [ValueSource("_1H1S_")] [Random(RndCnt)] ulong Z, + [ValueSource("_1H1S_")] [Random(RndCnt)] ulong A, + [ValueSource("_1H1S_")] [Random(RndCnt)] ulong B, + [Values(0b01u, 0b10u)] uint size) // + { + uint Opcode = 0x5E20B400; // SQDMULH B0, B0, B0 (RESERVED) + Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); + Opcode |= ((size & 3) << 22); + Bits Op = new Bits(Opcode); + + int Fpsr = (int)TestContext.CurrentContext.Random.NextUInt(); + + Vector128 V0 = MakeVectorE0E1(Z, Z); + Vector128 V1 = MakeVectorE0(A); + Vector128 V2 = MakeVectorE0(B); + AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, V2: V2, Fpsr: Fpsr); + + AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z)); + AArch64.V(1, new Bits(A)); + AArch64.V(2, new Bits(B)); + Shared.FPSR = new Bits((uint)Fpsr); + SimdFp.Sqdmulh_S(Op[23, 22], Op[20, 16], Op[9, 5], Op[4, 0]); + + Assert.Multiple(() => + { + Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64())); + Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64())); + }); + Assert.That(ThreadState.Fpsr, Is.EqualTo((int)Shared.FPSR.ToUInt32())); + } + + [Test, Pairwise, Description("SQDMULH ., ., .")] + public void Sqdmulh_V_4H_2S([Values(0u)] uint Rd, + [Values(1u, 0u)] uint Rn, + [Values(2u, 0u)] uint Rm, + [ValueSource("_4H2S_")] [Random(RndCnt)] ulong Z, + [ValueSource("_4H2S_")] [Random(RndCnt)] ulong A, + [ValueSource("_4H2S_")] [Random(RndCnt)] ulong B, + [Values(0b01u, 0b10u)] uint size) // <4H, 2S> + { + uint Opcode = 0x0E20B400; // SQDMULH V0.8B, V0.8B, V0.8B (RESERVED) + Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); + Opcode |= ((size & 3) << 22); + Bits Op = new Bits(Opcode); + + int Fpsr = (int)TestContext.CurrentContext.Random.NextUInt(); + + Vector128 V0 = MakeVectorE0E1(Z, Z); + Vector128 V1 = MakeVectorE0(A); + Vector128 V2 = MakeVectorE0(B); + AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, V2: V2, Fpsr: Fpsr); + + AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z)); + AArch64.V(1, new Bits(A)); + AArch64.V(2, new Bits(B)); + Shared.FPSR = new Bits((uint)Fpsr); + SimdFp.Sqdmulh_V(Op[30], Op[23, 22], Op[20, 16], Op[9, 5], Op[4, 0]); + + Assert.Multiple(() => + { + Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64())); + Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64())); + }); + Assert.That(ThreadState.Fpsr, Is.EqualTo((int)Shared.FPSR.ToUInt32())); + } + + [Test, Pairwise, Description("SQDMULH ., ., .")] + public void Sqdmulh_V_8H_4S([Values(0u)] uint Rd, + [Values(1u, 0u)] uint Rn, + [Values(2u, 0u)] uint Rm, + [ValueSource("_4H2S_")] [Random(RndCnt)] ulong Z, + [ValueSource("_4H2S_")] [Random(RndCnt)] ulong A, + [ValueSource("_4H2S_")] [Random(RndCnt)] ulong B, + [Values(0b01u, 0b10u)] uint size) // <8H, 4S> + { + uint Opcode = 0x4E20B400; // SQDMULH V0.16B, V0.16B, V0.16B (RESERVED) + Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); + Opcode |= ((size & 3) << 22); + Bits Op = new Bits(Opcode); + + int Fpsr = (int)TestContext.CurrentContext.Random.NextUInt(); + + Vector128 V0 = MakeVectorE0E1(Z, Z); + Vector128 V1 = MakeVectorE0E1(A, A); + Vector128 V2 = MakeVectorE0E1(B, B); + AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, V2: V2, Fpsr: Fpsr); + + AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z)); + AArch64.Vpart(1, 0, new Bits(A)); AArch64.Vpart(1, 1, new Bits(A)); + AArch64.Vpart(2, 0, new Bits(B)); AArch64.Vpart(2, 1, new Bits(B)); + Shared.FPSR = new Bits((uint)Fpsr); + SimdFp.Sqdmulh_V(Op[30], Op[23, 22], Op[20, 16], Op[9, 5], Op[4, 0]); + + Assert.Multiple(() => + { + Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64())); + Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64())); + }); + Assert.That(ThreadState.Fpsr, Is.EqualTo((int)Shared.FPSR.ToUInt32())); + } + + [Test, Pairwise, Description("SQRDMULH , , ")] + public void Sqrdmulh_S_H_S([Values(0u)] uint Rd, + [Values(1u, 0u)] uint Rn, + [Values(2u, 0u)] uint Rm, + [ValueSource("_1H1S_")] [Random(RndCnt)] ulong Z, + [ValueSource("_1H1S_")] [Random(RndCnt)] ulong A, + [ValueSource("_1H1S_")] [Random(RndCnt)] ulong B, + [Values(0b01u, 0b10u)] uint size) // + { + uint Opcode = 0x7E20B400; // SQRDMULH B0, B0, B0 (RESERVED) + Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); + Opcode |= ((size & 3) << 22); + Bits Op = new Bits(Opcode); + + int Fpsr = (int)TestContext.CurrentContext.Random.NextUInt(); + + Vector128 V0 = MakeVectorE0E1(Z, Z); + Vector128 V1 = MakeVectorE0(A); + Vector128 V2 = MakeVectorE0(B); + AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, V2: V2, Fpsr: Fpsr); + + AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z)); + AArch64.V(1, new Bits(A)); + AArch64.V(2, new Bits(B)); + Shared.FPSR = new Bits((uint)Fpsr); + SimdFp.Sqrdmulh_S(Op[23, 22], Op[20, 16], Op[9, 5], Op[4, 0]); + + Assert.Multiple(() => + { + Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64())); + Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64())); + }); + Assert.That(ThreadState.Fpsr, Is.EqualTo((int)Shared.FPSR.ToUInt32())); + } + + [Test, Pairwise, Description("SQRDMULH ., ., .")] + public void Sqrdmulh_V_4H_2S([Values(0u)] uint Rd, + [Values(1u, 0u)] uint Rn, + [Values(2u, 0u)] uint Rm, + [ValueSource("_4H2S_")] [Random(RndCnt)] ulong Z, + [ValueSource("_4H2S_")] [Random(RndCnt)] ulong A, + [ValueSource("_4H2S_")] [Random(RndCnt)] ulong B, + [Values(0b01u, 0b10u)] uint size) // <4H, 2S> + { + uint Opcode = 0x2E20B400; // SQRDMULH V0.8B, V0.8B, V0.8B (RESERVED) + Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); + Opcode |= ((size & 3) << 22); + Bits Op = new Bits(Opcode); + + int Fpsr = (int)TestContext.CurrentContext.Random.NextUInt(); + + Vector128 V0 = MakeVectorE0E1(Z, Z); + Vector128 V1 = MakeVectorE0(A); + Vector128 V2 = MakeVectorE0(B); + AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, V2: V2, Fpsr: Fpsr); + + AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z)); + AArch64.V(1, new Bits(A)); + AArch64.V(2, new Bits(B)); + Shared.FPSR = new Bits((uint)Fpsr); + SimdFp.Sqrdmulh_V(Op[30], Op[23, 22], Op[20, 16], Op[9, 5], Op[4, 0]); + + Assert.Multiple(() => + { + Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64())); + Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64())); + }); + Assert.That(ThreadState.Fpsr, Is.EqualTo((int)Shared.FPSR.ToUInt32())); + } + + [Test, Pairwise, Description("SQRDMULH ., ., .")] + public void Sqrdmulh_V_8H_4S([Values(0u)] uint Rd, + [Values(1u, 0u)] uint Rn, + [Values(2u, 0u)] uint Rm, + [ValueSource("_4H2S_")] [Random(RndCnt)] ulong Z, + [ValueSource("_4H2S_")] [Random(RndCnt)] ulong A, + [ValueSource("_4H2S_")] [Random(RndCnt)] ulong B, + [Values(0b01u, 0b10u)] uint size) // <8H, 4S> + { + uint Opcode = 0x6E20B400; // SQRDMULH V0.16B, V0.16B, V0.16B (RESERVED) + Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); + Opcode |= ((size & 3) << 22); + Bits Op = new Bits(Opcode); + + int Fpsr = (int)TestContext.CurrentContext.Random.NextUInt(); + + Vector128 V0 = MakeVectorE0E1(Z, Z); + Vector128 V1 = MakeVectorE0E1(A, A); + Vector128 V2 = MakeVectorE0E1(B, B); + AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, V2: V2, Fpsr: Fpsr); + + AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z)); + AArch64.Vpart(1, 0, new Bits(A)); AArch64.Vpart(1, 1, new Bits(A)); + AArch64.Vpart(2, 0, new Bits(B)); AArch64.Vpart(2, 1, new Bits(B)); + Shared.FPSR = new Bits((uint)Fpsr); + SimdFp.Sqrdmulh_V(Op[30], Op[23, 22], Op[20, 16], Op[9, 5], Op[4, 0]); + + Assert.Multiple(() => + { + Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64())); + Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64())); + }); + Assert.That(ThreadState.Fpsr, Is.EqualTo((int)Shared.FPSR.ToUInt32())); + } + [Test, Pairwise, Description("SQSUB , , ")] - public void Sqsub_S_B_H_S_D([Values(0u)] uint Rd, + public void Sqsub_S_B_H_S_D([Values(0u)] uint Rd, [Values(1u, 0u)] uint Rn, [Values(2u, 0u)] uint Rm, [ValueSource("_1B1H1S1D_")] [Random(RndCnt)] ulong Z, @@ -1873,7 +2098,7 @@ namespace Ryujinx.Tests.Cpu } [Test, Pairwise, Description("SQSUB ., ., .")] - public void Sqsub_V_8B_4H_2S([Values(0u)] uint Rd, + public void Sqsub_V_8B_4H_2S([Values(0u)] uint Rd, [Values(1u, 0u)] uint Rn, [Values(2u, 0u)] uint Rm, [ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong Z, @@ -1908,7 +2133,7 @@ namespace Ryujinx.Tests.Cpu } [Test, Pairwise, Description("SQSUB ., ., .")] - public void Sqsub_V_16B_8H_4S_2D([Values(0u)] uint Rd, + public void Sqsub_V_16B_8H_4S_2D([Values(0u)] uint Rd, [Values(1u, 0u)] uint Rn, [Values(2u, 0u)] uint Rm, [ValueSource("_8B4H2S1D_")] [Random(RndCnt)] ulong Z, @@ -1943,7 +2168,7 @@ namespace Ryujinx.Tests.Cpu } [Test, Pairwise, Description("SSUBW{2} ., ., .")] - public void Ssubw_V_8B8H8H_4H4S4S_2S2D2D([Values(0u)] uint Rd, + public void Ssubw_V_8B8H8H_4H4S4S_2S2D2D([Values(0u)] uint Rd, [Values(1u, 0u)] uint Rn, [Values(2u, 0u)] uint Rm, [ValueSource("_8B4H2S1D_")] [Random(RndCnt)] ulong Z, @@ -1974,7 +2199,7 @@ namespace Ryujinx.Tests.Cpu } [Test, Pairwise, Description("SSUBW{2} ., ., .")] - public void Ssubw_V_16B8H8H_8H4S4S_4S2D2D([Values(0u)] uint Rd, + public void Ssubw_V_16B8H8H_8H4S4S_4S2D2D([Values(0u)] uint Rd, [Values(1u, 0u)] uint Rn, [Values(2u, 0u)] uint Rm, [ValueSource("_8B4H2S1D_")] [Random(RndCnt)] ulong Z, @@ -2005,7 +2230,7 @@ namespace Ryujinx.Tests.Cpu } [Test, Pairwise, Description("SUB , , ")] - public void Sub_S_D([Values(0u)] uint Rd, + public void Sub_S_D([Values(0u)] uint Rd, [Values(1u, 0u)] uint Rn, [Values(2u, 0u)] uint Rm, [ValueSource("_1D_")] [Random(RndCnt)] ulong Z, @@ -2034,7 +2259,7 @@ namespace Ryujinx.Tests.Cpu } [Test, Pairwise, Description("SUB ., ., .")] - public void Sub_V_8B_4H_2S([Values(0u)] uint Rd, + public void Sub_V_8B_4H_2S([Values(0u)] uint Rd, [Values(1u, 0u)] uint Rn, [Values(2u, 0u)] uint Rm, [ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong Z, @@ -2065,7 +2290,7 @@ namespace Ryujinx.Tests.Cpu } [Test, Pairwise, Description("SUB ., ., .")] - public void Sub_V_16B_8H_4S_2D([Values(0u)] uint Rd, + public void Sub_V_16B_8H_4S_2D([Values(0u)] uint Rd, [Values(1u, 0u)] uint Rn, [Values(2u, 0u)] uint Rm, [ValueSource("_8B4H2S1D_")] [Random(RndCnt)] ulong Z, @@ -2096,7 +2321,7 @@ namespace Ryujinx.Tests.Cpu } [Test, Pairwise, Description("SUBHN{2} ., ., .")] - public void Subhn_V_8H8B_4S4H_2D2S([Values(0u)] uint Rd, + public void Subhn_V_8H8B_4S4H_2D2S([Values(0u)] uint Rd, [Values(1u, 0u)] uint Rn, [Values(2u, 0u)] uint Rm, [ValueSource("_4H2S1D_")] [Random(RndCnt)] ulong Z, @@ -2127,7 +2352,7 @@ namespace Ryujinx.Tests.Cpu } [Test, Pairwise, Description("SUBHN{2} ., ., .")] - public void Subhn_V_8H16B_4S8H_2D4S([Values(0u)] uint Rd, + public void Subhn_V_8H16B_4S8H_2D4S([Values(0u)] uint Rd, [Values(1u, 0u)] uint Rn, [Values(2u, 0u)] uint Rm, [ValueSource("_4H2S1D_")] [Random(RndCnt)] ulong Z, @@ -2158,7 +2383,7 @@ namespace Ryujinx.Tests.Cpu } [Test, Pairwise, Description("TRN1 ., ., .")] - public void Trn1_V_8B_4H_2S([Values(0u)] uint Rd, + public void Trn1_V_8B_4H_2S([Values(0u)] uint Rd, [Values(1u, 0u)] uint Rn, [Values(2u, 0u)] uint Rm, [ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong Z, @@ -2189,7 +2414,7 @@ namespace Ryujinx.Tests.Cpu } [Test, Pairwise, Description("TRN1 ., ., .")] - public void Trn1_V_16B_8H_4S_2D([Values(0u)] uint Rd, + public void Trn1_V_16B_8H_4S_2D([Values(0u)] uint Rd, [Values(1u, 0u)] uint Rn, [Values(2u, 0u)] uint Rm, [ValueSource("_8B4H2S1D_")] [Random(RndCnt)] ulong Z, @@ -2220,7 +2445,7 @@ namespace Ryujinx.Tests.Cpu } [Test, Pairwise, Description("TRN2 ., ., .")] - public void Trn2_V_8B_4H_2S([Values(0u)] uint Rd, + public void Trn2_V_8B_4H_2S([Values(0u)] uint Rd, [Values(1u, 0u)] uint Rn, [Values(2u, 0u)] uint Rm, [ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong Z, @@ -2251,7 +2476,7 @@ namespace Ryujinx.Tests.Cpu } [Test, Pairwise, Description("TRN2 ., ., .")] - public void Trn2_V_16B_8H_4S_2D([Values(0u)] uint Rd, + public void Trn2_V_16B_8H_4S_2D([Values(0u)] uint Rd, [Values(1u, 0u)] uint Rn, [Values(2u, 0u)] uint Rm, [ValueSource("_8B4H2S1D_")] [Random(RndCnt)] ulong Z, @@ -2282,7 +2507,7 @@ namespace Ryujinx.Tests.Cpu } [Test, Pairwise, Description("UABA ., ., .")] - public void Uaba_V_8B_4H_2S([Values(0u)] uint Rd, + public void Uaba_V_8B_4H_2S([Values(0u)] uint Rd, [Values(1u, 0u)] uint Rn, [Values(2u, 0u)] uint Rm, [ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong Z, @@ -2313,7 +2538,7 @@ namespace Ryujinx.Tests.Cpu } [Test, Pairwise, Description("UABA ., ., .")] - public void Uaba_V_16B_8H_4S([Values(0u)] uint Rd, + public void Uaba_V_16B_8H_4S([Values(0u)] uint Rd, [Values(1u, 0u)] uint Rn, [Values(2u, 0u)] uint Rm, [ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong Z, @@ -2344,7 +2569,7 @@ namespace Ryujinx.Tests.Cpu } [Test, Pairwise, Description("UABAL{2} ., ., .")] - public void Uabal_V_8B8H_4H4S_2S2D([Values(0u)] uint Rd, + public void Uabal_V_8B8H_4H4S_2S2D([Values(0u)] uint Rd, [Values(1u, 0u)] uint Rn, [Values(2u, 0u)] uint Rm, [ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong Z, @@ -2375,7 +2600,7 @@ namespace Ryujinx.Tests.Cpu } [Test, Pairwise, Description("UABAL{2} ., ., .")] - public void Uabal_V_16B8H_8H4S_4S2D([Values(0u)] uint Rd, + public void Uabal_V_16B8H_8H4S_4S2D([Values(0u)] uint Rd, [Values(1u, 0u)] uint Rn, [Values(2u, 0u)] uint Rm, [ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong Z, @@ -2406,7 +2631,7 @@ namespace Ryujinx.Tests.Cpu } [Test, Pairwise, Description("UABD ., ., .")] - public void Uabd_V_8B_4H_2S([Values(0u)] uint Rd, + public void Uabd_V_8B_4H_2S([Values(0u)] uint Rd, [Values(1u, 0u)] uint Rn, [Values(2u, 0u)] uint Rm, [ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong Z, @@ -2437,7 +2662,7 @@ namespace Ryujinx.Tests.Cpu } [Test, Pairwise, Description("UABD ., ., .")] - public void Uabd_V_16B_8H_4S([Values(0u)] uint Rd, + public void Uabd_V_16B_8H_4S([Values(0u)] uint Rd, [Values(1u, 0u)] uint Rn, [Values(2u, 0u)] uint Rm, [ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong Z, @@ -2468,7 +2693,7 @@ namespace Ryujinx.Tests.Cpu } [Test, Pairwise, Description("UABDL{2} ., ., .")] - public void Uabdl_V_8B8H_4H4S_2S2D([Values(0u)] uint Rd, + public void Uabdl_V_8B8H_4H4S_2S2D([Values(0u)] uint Rd, [Values(1u, 0u)] uint Rn, [Values(2u, 0u)] uint Rm, [ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong Z, @@ -2499,7 +2724,7 @@ namespace Ryujinx.Tests.Cpu } [Test, Pairwise, Description("UABDL{2} ., ., .")] - public void Uabdl_V_16B8H_8H4S_4S2D([Values(0u)] uint Rd, + public void Uabdl_V_16B8H_8H4S_4S2D([Values(0u)] uint Rd, [Values(1u, 0u)] uint Rn, [Values(2u, 0u)] uint Rm, [ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong Z, @@ -2530,7 +2755,7 @@ namespace Ryujinx.Tests.Cpu } [Test, Pairwise, Description("UADDW{2} ., ., .")] - public void Uaddw_V_8B8H8H_4H4S4S_2S2D2D([Values(0u)] uint Rd, + public void Uaddw_V_8B8H8H_4H4S4S_2S2D2D([Values(0u)] uint Rd, [Values(1u, 0u)] uint Rn, [Values(2u, 0u)] uint Rm, [ValueSource("_8B4H2S1D_")] [Random(RndCnt)] ulong Z, @@ -2561,7 +2786,7 @@ namespace Ryujinx.Tests.Cpu } [Test, Pairwise, Description("UADDW{2} ., ., .")] - public void Uaddw_V_16B8H8H_8H4S4S_4S2D2D([Values(0u)] uint Rd, + public void Uaddw_V_16B8H8H_8H4S4S_4S2D2D([Values(0u)] uint Rd, [Values(1u, 0u)] uint Rn, [Values(2u, 0u)] uint Rm, [ValueSource("_8B4H2S1D_")] [Random(RndCnt)] ulong Z, @@ -2592,7 +2817,7 @@ namespace Ryujinx.Tests.Cpu } [Test, Pairwise, Description("UQADD , , ")] - public void Uqadd_S_B_H_S_D([Values(0u)] uint Rd, + public void Uqadd_S_B_H_S_D([Values(0u)] uint Rd, [Values(1u, 0u)] uint Rn, [Values(2u, 0u)] uint Rm, [ValueSource("_1B1H1S1D_")] [Random(RndCnt)] ulong Z, @@ -2627,7 +2852,7 @@ namespace Ryujinx.Tests.Cpu } [Test, Pairwise, Description("UQADD ., ., .")] - public void Uqadd_V_8B_4H_2S([Values(0u)] uint Rd, + public void Uqadd_V_8B_4H_2S([Values(0u)] uint Rd, [Values(1u, 0u)] uint Rn, [Values(2u, 0u)] uint Rm, [ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong Z, @@ -2662,7 +2887,7 @@ namespace Ryujinx.Tests.Cpu } [Test, Pairwise, Description("UQADD ., ., .")] - public void Uqadd_V_16B_8H_4S_2D([Values(0u)] uint Rd, + public void Uqadd_V_16B_8H_4S_2D([Values(0u)] uint Rd, [Values(1u, 0u)] uint Rn, [Values(2u, 0u)] uint Rm, [ValueSource("_8B4H2S1D_")] [Random(RndCnt)] ulong Z, @@ -2697,7 +2922,7 @@ namespace Ryujinx.Tests.Cpu } [Test, Pairwise, Description("UQSUB , , ")] - public void Uqsub_S_B_H_S_D([Values(0u)] uint Rd, + public void Uqsub_S_B_H_S_D([Values(0u)] uint Rd, [Values(1u, 0u)] uint Rn, [Values(2u, 0u)] uint Rm, [ValueSource("_1B1H1S1D_")] [Random(RndCnt)] ulong Z, @@ -2732,7 +2957,7 @@ namespace Ryujinx.Tests.Cpu } [Test, Pairwise, Description("UQSUB ., ., .")] - public void Uqsub_V_8B_4H_2S([Values(0u)] uint Rd, + public void Uqsub_V_8B_4H_2S([Values(0u)] uint Rd, [Values(1u, 0u)] uint Rn, [Values(2u, 0u)] uint Rm, [ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong Z, @@ -2767,7 +2992,7 @@ namespace Ryujinx.Tests.Cpu } [Test, Pairwise, Description("UQSUB ., ., .")] - public void Uqsub_V_16B_8H_4S_2D([Values(0u)] uint Rd, + public void Uqsub_V_16B_8H_4S_2D([Values(0u)] uint Rd, [Values(1u, 0u)] uint Rn, [Values(2u, 0u)] uint Rm, [ValueSource("_8B4H2S1D_")] [Random(RndCnt)] ulong Z, @@ -2802,7 +3027,7 @@ namespace Ryujinx.Tests.Cpu } [Test, Pairwise, Description("USUBW{2} ., ., .")] - public void Usubw_V_8B8H8H_4H4S4S_2S2D2D([Values(0u)] uint Rd, + public void Usubw_V_8B8H8H_4H4S4S_2S2D2D([Values(0u)] uint Rd, [Values(1u, 0u)] uint Rn, [Values(2u, 0u)] uint Rm, [ValueSource("_8B4H2S1D_")] [Random(RndCnt)] ulong Z, @@ -2833,7 +3058,7 @@ namespace Ryujinx.Tests.Cpu } [Test, Pairwise, Description("USUBW{2} ., ., .")] - public void Usubw_V_16B8H8H_8H4S4S_4S2D2D([Values(0u)] uint Rd, + public void Usubw_V_16B8H8H_8H4S4S_4S2D2D([Values(0u)] uint Rd, [Values(1u, 0u)] uint Rn, [Values(2u, 0u)] uint Rm, [ValueSource("_8B4H2S1D_")] [Random(RndCnt)] ulong Z, @@ -2864,7 +3089,7 @@ namespace Ryujinx.Tests.Cpu } [Test, Pairwise, Description("UZP1 ., ., .")] - public void Uzp1_V_8B_4H_2S([Values(0u)] uint Rd, + public void Uzp1_V_8B_4H_2S([Values(0u)] uint Rd, [Values(1u, 0u)] uint Rn, [Values(2u, 0u)] uint Rm, [ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong Z, @@ -2895,7 +3120,7 @@ namespace Ryujinx.Tests.Cpu } [Test, Pairwise, Description("UZP1 ., ., .")] - public void Uzp1_V_16B_8H_4S_2D([Values(0u)] uint Rd, + public void Uzp1_V_16B_8H_4S_2D([Values(0u)] uint Rd, [Values(1u, 0u)] uint Rn, [Values(2u, 0u)] uint Rm, [ValueSource("_8B4H2S1D_")] [Random(RndCnt)] ulong Z, @@ -2926,7 +3151,7 @@ namespace Ryujinx.Tests.Cpu } [Test, Pairwise, Description("UZP2 ., ., .")] - public void Uzp2_V_8B_4H_2S([Values(0u)] uint Rd, + public void Uzp2_V_8B_4H_2S([Values(0u)] uint Rd, [Values(1u, 0u)] uint Rn, [Values(2u, 0u)] uint Rm, [ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong Z, @@ -2957,7 +3182,7 @@ namespace Ryujinx.Tests.Cpu } [Test, Pairwise, Description("UZP2 ., ., .")] - public void Uzp2_V_16B_8H_4S_2D([Values(0u)] uint Rd, + public void Uzp2_V_16B_8H_4S_2D([Values(0u)] uint Rd, [Values(1u, 0u)] uint Rn, [Values(2u, 0u)] uint Rm, [ValueSource("_8B4H2S1D_")] [Random(RndCnt)] ulong Z, @@ -2988,7 +3213,7 @@ namespace Ryujinx.Tests.Cpu } [Test, Pairwise, Description("ZIP1 ., ., .")] - public void Zip1_V_8B_4H_2S([Values(0u)] uint Rd, + public void Zip1_V_8B_4H_2S([Values(0u)] uint Rd, [Values(1u, 0u)] uint Rn, [Values(2u, 0u)] uint Rm, [ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong Z, @@ -3019,7 +3244,7 @@ namespace Ryujinx.Tests.Cpu } [Test, Pairwise, Description("ZIP1 ., ., .")] - public void Zip1_V_16B_8H_4S_2D([Values(0u)] uint Rd, + public void Zip1_V_16B_8H_4S_2D([Values(0u)] uint Rd, [Values(1u, 0u)] uint Rn, [Values(2u, 0u)] uint Rm, [ValueSource("_8B4H2S1D_")] [Random(RndCnt)] ulong Z, @@ -3050,7 +3275,7 @@ namespace Ryujinx.Tests.Cpu } [Test, Pairwise, Description("ZIP2 ., ., .")] - public void Zip2_V_8B_4H_2S([Values(0u)] uint Rd, + public void Zip2_V_8B_4H_2S([Values(0u)] uint Rd, [Values(1u, 0u)] uint Rn, [Values(2u, 0u)] uint Rm, [ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong Z, @@ -3081,7 +3306,7 @@ namespace Ryujinx.Tests.Cpu } [Test, Pairwise, Description("ZIP2 ., ., .")] - public void Zip2_V_16B_8H_4S_2D([Values(0u)] uint Rd, + public void Zip2_V_16B_8H_4S_2D([Values(0u)] uint Rd, [Values(1u, 0u)] uint Rn, [Values(2u, 0u)] uint Rm, [ValueSource("_8B4H2S1D_")] [Random(RndCnt)] ulong Z, diff --git a/Ryujinx.Tests/Cpu/Tester/Instructions.cs b/Ryujinx.Tests/Cpu/Tester/Instructions.cs index 8b1b010f6..258737185 100644 --- a/Ryujinx.Tests/Cpu/Tester/Instructions.cs +++ b/Ryujinx.Tests/Cpu/Tester/Instructions.cs @@ -5075,6 +5075,210 @@ namespace Ryujinx.Tests.Cpu.Tester V(d, result); } + // sqdmulh_advsimd_vec.html#SQDMULH_asisdsame_only + public static void Sqdmulh_S(Bits size, Bits Rm, Bits Rn, Bits Rd) + { + const bool U = false; + + /* Decode Scalar */ + int d = (int)UInt(Rd); + int n = (int)UInt(Rn); + int m = (int)UInt(Rm); + + /* if size == '11' || size == '00' then ReservedValue(); */ + + int esize = 8 << (int)UInt(size); + int datasize = esize; + int elements = 1; + + bool rounding = (U == true); + + /* Operation */ + /* CheckFPAdvSIMDEnabled64(); */ + + Bits result = new Bits(datasize); + Bits operand1 = V(datasize, n); + Bits operand2 = V(datasize, m); + BigInteger round_const = (rounding ? (BigInteger)1 << (esize - 1) : 0); + BigInteger element1; + BigInteger element2; + BigInteger product; + bool sat; + + for (int e = 0; e <= elements - 1; e++) + { + element1 = SInt(Elem(operand1, e, esize)); + element2 = SInt(Elem(operand2, e, esize)); + + product = (2 * element1 * element2) + round_const; + + (Bits _result, bool _sat) = SignedSatQ(product >> esize, esize); + Elem(result, e, esize, _result); + sat = _sat; + + if (sat) + { + /* FPSR.QC = '1'; */ + FPSR[27] = true; // TODO: Add named fields. + } + } + + V(d, result); + } + + // sqdmulh_advsimd_vec.html#SQDMULH_asimdsame_only + public static void Sqdmulh_V(bool Q, Bits size, Bits Rm, Bits Rn, Bits Rd) + { + const bool U = false; + + /* Decode Vector */ + int d = (int)UInt(Rd); + int n = (int)UInt(Rn); + int m = (int)UInt(Rm); + + /* if size == '11' || size == '00' then ReservedValue(); */ + + int esize = 8 << (int)UInt(size); + int datasize = (Q ? 128 : 64); + int elements = datasize / esize; + + bool rounding = (U == true); + + /* Operation */ + /* CheckFPAdvSIMDEnabled64(); */ + + Bits result = new Bits(datasize); + Bits operand1 = V(datasize, n); + Bits operand2 = V(datasize, m); + BigInteger round_const = (rounding ? (BigInteger)1 << (esize - 1) : 0); + BigInteger element1; + BigInteger element2; + BigInteger product; + bool sat; + + for (int e = 0; e <= elements - 1; e++) + { + element1 = SInt(Elem(operand1, e, esize)); + element2 = SInt(Elem(operand2, e, esize)); + + product = (2 * element1 * element2) + round_const; + + (Bits _result, bool _sat) = SignedSatQ(product >> esize, esize); + Elem(result, e, esize, _result); + sat = _sat; + + if (sat) + { + /* FPSR.QC = '1'; */ + FPSR[27] = true; // TODO: Add named fields. + } + } + + V(d, result); + } + + // sqrdmulh_advsimd_vec.html#SQRDMULH_asisdsame_only + public static void Sqrdmulh_S(Bits size, Bits Rm, Bits Rn, Bits Rd) + { + const bool U = true; + + /* Decode Scalar */ + int d = (int)UInt(Rd); + int n = (int)UInt(Rn); + int m = (int)UInt(Rm); + + /* if size == '11' || size == '00' then ReservedValue(); */ + + int esize = 8 << (int)UInt(size); + int datasize = esize; + int elements = 1; + + bool rounding = (U == true); + + /* Operation */ + /* CheckFPAdvSIMDEnabled64(); */ + + Bits result = new Bits(datasize); + Bits operand1 = V(datasize, n); + Bits operand2 = V(datasize, m); + BigInteger round_const = (rounding ? (BigInteger)1 << (esize - 1) : 0); + BigInteger element1; + BigInteger element2; + BigInteger product; + bool sat; + + for (int e = 0; e <= elements - 1; e++) + { + element1 = SInt(Elem(operand1, e, esize)); + element2 = SInt(Elem(operand2, e, esize)); + + product = (2 * element1 * element2) + round_const; + + (Bits _result, bool _sat) = SignedSatQ(product >> esize, esize); + Elem(result, e, esize, _result); + sat = _sat; + + if (sat) + { + /* FPSR.QC = '1'; */ + FPSR[27] = true; // TODO: Add named fields. + } + } + + V(d, result); + } + + // sqrdmulh_advsimd_vec.html#SQRDMULH_asimdsame_only + public static void Sqrdmulh_V(bool Q, Bits size, Bits Rm, Bits Rn, Bits Rd) + { + const bool U = true; + + /* Decode Vector */ + int d = (int)UInt(Rd); + int n = (int)UInt(Rn); + int m = (int)UInt(Rm); + + /* if size == '11' || size == '00' then ReservedValue(); */ + + int esize = 8 << (int)UInt(size); + int datasize = (Q ? 128 : 64); + int elements = datasize / esize; + + bool rounding = (U == true); + + /* Operation */ + /* CheckFPAdvSIMDEnabled64(); */ + + Bits result = new Bits(datasize); + Bits operand1 = V(datasize, n); + Bits operand2 = V(datasize, m); + BigInteger round_const = (rounding ? (BigInteger)1 << (esize - 1) : 0); + BigInteger element1; + BigInteger element2; + BigInteger product; + bool sat; + + for (int e = 0; e <= elements - 1; e++) + { + element1 = SInt(Elem(operand1, e, esize)); + element2 = SInt(Elem(operand2, e, esize)); + + product = (2 * element1 * element2) + round_const; + + (Bits _result, bool _sat) = SignedSatQ(product >> esize, esize); + Elem(result, e, esize, _result); + sat = _sat; + + if (sat) + { + /* FPSR.QC = '1'; */ + FPSR[27] = true; // TODO: Add named fields. + } + } + + V(d, result); + } + // sqsub_advsimd.html#SQSUB_asisdsame_only public static void Sqsub_S(Bits size, Bits Rm, Bits Rn, Bits Rd) { diff --git a/Ryujinx.Tests/Ryujinx.Tests.csproj b/Ryujinx.Tests/Ryujinx.Tests.csproj index b4ba379a1..a68b34e94 100644 --- a/Ryujinx.Tests/Ryujinx.Tests.csproj +++ b/Ryujinx.Tests/Ryujinx.Tests.csproj @@ -1,20 +1,25 @@ - + + netcoreapp2.1 win10-x64;osx-x64;linux-x64 Exe false + false + - + + + diff --git a/Ryujinx/Ryujinx.csproj b/Ryujinx/Ryujinx.csproj index 443e7bbad..ad132ada4 100644 --- a/Ryujinx/Ryujinx.csproj +++ b/Ryujinx/Ryujinx.csproj @@ -1,23 +1,28 @@ - + + - Exe netcoreapp2.1 - true win10-x64;osx-x64;linux-x64 + Exe + true + + - + + PreserveNewest - \ No newline at end of file + +