diff --git a/ChocolArm64/Memory/AMemory.cs b/ChocolArm64/Memory/AMemory.cs
index 7af288a60..2adf54032 100644
--- a/ChocolArm64/Memory/AMemory.cs
+++ b/ChocolArm64/Memory/AMemory.cs
@@ -355,11 +355,18 @@ namespace ChocolArm64.Memory
 
         public byte[] ReadBytes(long Position, long Size)
         {
+            if ((uint)Size > int.MaxValue)
+            {
+                throw new ArgumentOutOfRangeException(nameof(Size));
+            }
+
             EnsureRangeIsValid(Position, Size, AMemoryPerm.Read);
 
-            byte[] Result = new byte[Size];
-            Marshal.Copy((IntPtr)(RamPtr + (uint)Position), Result, 0, (int)Size);
-            return Result;
+            byte[] Data = new byte[Size];
+
+            Marshal.Copy((IntPtr)(RamPtr + (uint)Position), Data, 0, (int)Size);
+
+            return Data;
         }
 
         public Vector128<float> ReadVector8Unchecked(long Position)
@@ -392,9 +399,7 @@ namespace ChocolArm64.Memory
         {
             if (Sse.IsSupported)
             {
-                byte* Address = RamPtr + (uint)Position;
-
-                return Sse.LoadScalarVector128((float*)Address);
+                return Sse.LoadScalarVector128((float*)(RamPtr + (uint)Position));
             }
             else
             {
@@ -420,9 +425,7 @@ namespace ChocolArm64.Memory
         {
             if (Sse.IsSupported)
             {
-                byte* Address = RamPtr + (uint)Position;
-
-                return Sse.LoadVector128((float*)Address);
+                return Sse.LoadVector128((float*)(RamPtr + (uint)Position));
             }
             else
             {
@@ -678,11 +681,12 @@ namespace ChocolArm64.Memory
 
         private void EnsureRangeIsValid(long Position, long Size, AMemoryPerm Perm)
         {
-            long EndPos = (Position + Size);
-            Position = Position & ~AMemoryMgr.PageMask; //check base of each page
-            while (Position < EndPos)
+            long EndPos = Position + Size;
+
+            while ((ulong)Position < (ulong)EndPos)
             {
                 EnsureAccessIsValid(Position, Perm);
+
                 Position += AMemoryMgr.PageSize;
             }
         }
diff --git a/Ryujinx.Core/OsHle/Kernel/SvcThread.cs b/Ryujinx.Core/OsHle/Kernel/SvcThread.cs
index b6346f4e8..8aa26dd3f 100644
--- a/Ryujinx.Core/OsHle/Kernel/SvcThread.cs
+++ b/Ryujinx.Core/OsHle/Kernel/SvcThread.cs
@@ -1,7 +1,6 @@
 using ChocolArm64.State;
 using Ryujinx.Core.Logging;
 using Ryujinx.Core.OsHle.Handles;
-using System;
 using System.Threading;
 
 using static Ryujinx.Core.OsHle.ErrorCode;
diff --git a/Ryujinx.Core/OsHle/Services/Am/IStorageAccessor.cs b/Ryujinx.Core/OsHle/Services/Am/IStorageAccessor.cs
index 4cd1f99b8..ff00f3306 100644
--- a/Ryujinx.Core/OsHle/Services/Am/IStorageAccessor.cs
+++ b/Ryujinx.Core/OsHle/Services/Am/IStorageAccessor.cs
@@ -1,5 +1,4 @@
 using ChocolArm64.Memory;
-using Ryujinx.Core.Logging;
 using Ryujinx.Core.OsHle.Ipc;
 using System;
 using System.Collections.Generic;
diff --git a/Ryujinx.Core/OsHle/Services/Lm/ILogger.cs b/Ryujinx.Core/OsHle/Services/Lm/ILogger.cs
index 510901058..41f3710ba 100644
--- a/Ryujinx.Core/OsHle/Services/Lm/ILogger.cs
+++ b/Ryujinx.Core/OsHle/Services/Lm/ILogger.cs
@@ -1,4 +1,3 @@
-using ChocolArm64.Memory;
 using Ryujinx.Core.Logging;
 using Ryujinx.Core.OsHle.Ipc;
 using System.Collections.Generic;
diff --git a/Ryujinx.Core/OsHle/Services/Vi/IHOSBinderDriver.cs b/Ryujinx.Core/OsHle/Services/Vi/IHOSBinderDriver.cs
index 41c3970e7..23746613b 100644
--- a/Ryujinx.Core/OsHle/Services/Vi/IHOSBinderDriver.cs
+++ b/Ryujinx.Core/OsHle/Services/Vi/IHOSBinderDriver.cs
@@ -1,4 +1,3 @@
-using ChocolArm64.Memory;
 using Ryujinx.Core.OsHle.Handles;
 using Ryujinx.Core.OsHle.Ipc;
 using Ryujinx.Core.OsHle.Services.Android;