From e9a96e3522ee7620b525d210915a0e45510ea528 Mon Sep 17 00:00:00 2001 From: LDj3SNuD <35856442+LDj3SNuD@users.noreply.github.com> Date: Wed, 18 Apr 2018 22:22:45 +0200 Subject: [PATCH] Add 151 complete tests for 71 base instructions of types: Alu; AluImm; AluRs; AluRx; Bfm; CcmpImm; CcmpReg; Csel; Mov; Mul. (#80) * Add files via upload * Update Ryujinx.Tests.csproj --- Ryujinx.Tests/Cpu/CpuTest.cs | 9 +- Ryujinx.Tests/Cpu/CpuTestAlu.cs | 447 +++-- Ryujinx.Tests/Cpu/CpuTestAluImm.cs | 811 +++++++++ Ryujinx.Tests/Cpu/CpuTestAluRs.cs | 1911 +++++++++++++++++++++ Ryujinx.Tests/Cpu/CpuTestAluRx.cs | 1349 +++++++++++++++ Ryujinx.Tests/Cpu/CpuTestBfm.cs | 213 +++ Ryujinx.Tests/Cpu/CpuTestCcmpImm.cs | 151 ++ Ryujinx.Tests/Cpu/CpuTestCcmpReg.cs | 163 ++ Ryujinx.Tests/Cpu/CpuTestCsel.cs | 319 ++++ Ryujinx.Tests/Cpu/CpuTestMisc.cs | 221 ++- Ryujinx.Tests/Cpu/CpuTestMov.cs | 189 ++ Ryujinx.Tests/Cpu/CpuTestMul.cs | 375 ++++ Ryujinx.Tests/Cpu/Tester/Instructions.cs | 1682 ++++++++++++++++++ Ryujinx.Tests/Cpu/Tester/Pseudocode.cs | 958 +++++++++++ Ryujinx.Tests/Cpu/Tester/Types/Bits.cs | 248 +++ Ryujinx.Tests/Cpu/Tester/Types/Integer.cs | 42 + Ryujinx.Tests/Ryujinx.Tests.csproj | 8 +- 17 files changed, 8833 insertions(+), 263 deletions(-) create mode 100644 Ryujinx.Tests/Cpu/CpuTestAluImm.cs create mode 100644 Ryujinx.Tests/Cpu/CpuTestAluRs.cs create mode 100644 Ryujinx.Tests/Cpu/CpuTestAluRx.cs create mode 100644 Ryujinx.Tests/Cpu/CpuTestBfm.cs create mode 100644 Ryujinx.Tests/Cpu/CpuTestCcmpImm.cs create mode 100644 Ryujinx.Tests/Cpu/CpuTestCcmpReg.cs create mode 100644 Ryujinx.Tests/Cpu/CpuTestCsel.cs create mode 100644 Ryujinx.Tests/Cpu/CpuTestMov.cs create mode 100644 Ryujinx.Tests/Cpu/CpuTestMul.cs create mode 100644 Ryujinx.Tests/Cpu/Tester/Instructions.cs create mode 100644 Ryujinx.Tests/Cpu/Tester/Pseudocode.cs create mode 100644 Ryujinx.Tests/Cpu/Tester/Types/Bits.cs create mode 100644 Ryujinx.Tests/Cpu/Tester/Types/Integer.cs diff --git a/Ryujinx.Tests/Cpu/CpuTest.cs b/Ryujinx.Tests/Cpu/CpuTest.cs index b5bbdbc17..14ef0a15d 100644 --- a/Ryujinx.Tests/Cpu/CpuTest.cs +++ b/Ryujinx.Tests/Cpu/CpuTest.cs @@ -1,7 +1,9 @@ using ChocolArm64; using ChocolArm64.Memory; using ChocolArm64.State; + using NUnit.Framework; + using System.Threading; namespace Ryujinx.Tests.Cpu @@ -51,13 +53,14 @@ namespace Ryujinx.Tests.Cpu Position += 4; } - protected void SetThreadState(ulong X0 = 0, ulong X1 = 0, ulong X2 = 0, ulong X31 = 0, + protected void SetThreadState(ulong X0 = 0, ulong X1 = 0, ulong X2 = 0, ulong X3 = 0, ulong X31 = 0, AVec V0 = default(AVec), AVec V1 = default(AVec), AVec V2 = default(AVec), bool Overflow = false, bool Carry = false, bool Zero = false, bool Negative = false, int Fpcr = 0x0) { Thread.ThreadState.X0 = X0; Thread.ThreadState.X1 = X1; Thread.ThreadState.X2 = X2; + Thread.ThreadState.X3 = X3; Thread.ThreadState.X31 = X31; Thread.ThreadState.V0 = V0; Thread.ThreadState.V1 = V1; @@ -87,14 +90,14 @@ namespace Ryujinx.Tests.Cpu } protected AThreadState SingleOpcode(uint Opcode, - ulong X0 = 0, ulong X1 = 0, ulong X2 = 0, ulong X31 = 0, + ulong X0 = 0, ulong X1 = 0, ulong X2 = 0, ulong X3 = 0, ulong X31 = 0, AVec V0 = default(AVec), AVec V1 = default(AVec), AVec V2 = default(AVec), bool Overflow = false, bool Carry = false, bool Zero = false, bool Negative = false, int Fpcr = 0x0) { this.Opcode(Opcode); this.Opcode(0xD4200000); // BRK #0 this.Opcode(0xD65F03C0); // RET - SetThreadState(X0, X1, X2, X31, V0, V1, V2, Overflow, Carry, Zero, Negative, Fpcr); + SetThreadState(X0, X1, X2, X3, X31, V0, V1, V2, Overflow, Carry, Zero, Negative, Fpcr); ExecuteOpcodes(); return GetThreadState(); diff --git a/Ryujinx.Tests/Cpu/CpuTestAlu.cs b/Ryujinx.Tests/Cpu/CpuTestAlu.cs index 8116fc7c7..564fadec2 100644 --- a/Ryujinx.Tests/Cpu/CpuTestAlu.cs +++ b/Ryujinx.Tests/Cpu/CpuTestAlu.cs @@ -1,162 +1,331 @@ +//#define Alu + using ChocolArm64.State; + using NUnit.Framework; namespace Ryujinx.Tests.Cpu { - public class CpuTestAlu : CpuTest + using Tester; + using Tester.Types; + + [Category("Alu"), Ignore("Tested: first half of 2018.")] + public sealed class CpuTestAlu : CpuTest { - [TestCase(0x9A020020u, 2u, 3u, true, 6u)] - [TestCase(0x9A020020u, 2u, 3u, false, 5u)] - [TestCase(0x1A020020u, 2u, 3u, true, 6u)] - [TestCase(0x1A020020u, 2u, 3u, false, 5u)] - [TestCase(0x1A020020u, 0xFFFFFFFFu, 0x2u, false, 0x1u)] - public void Adc(uint Opcode, uint A, uint B, bool CarryState, uint Result) +#if Alu + [SetUp] + public void SetupTester() { - // ADC (X0/W0), (X1/W1), (X2/W2) - AThreadState ThreadState = SingleOpcode(Opcode, X1: A, X2: B, Carry: CarryState); - Assert.AreEqual(Result, ThreadState.X0); + AArch64.TakeReset(false); } - [TestCase(0x3A020020u, 2u, 3u, false, false, false, false, 5u)] - [TestCase(0x3A020020u, 2u, 3u, true, false, false, false, 6u)] - [TestCase(0xBA020020u, 2u, 3u, false, false, false, false, 5u)] - [TestCase(0xBA020020u, 2u, 3u, true, false, false, false, 6u)] - [TestCase(0x3A020020u, 0xFFFFFFFEu, 0x1u, true, false, true, true, 0x0u)] - [TestCase(0x3A020020u, 0xFFFFFFFFu, 0xFFFFFFFFu, true, true, false, true, 0xFFFFFFFFu)] - public void Adcs(uint Opcode, uint A, uint B, bool CarryState, bool Negative, bool Zero, bool Carry, uint Result) + [Test, Description("CLS , ")] + public void Cls_64bit([Values(0u, 31u)] uint Rd, + [Values(1u, 31u)] uint Rn, + [Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul, + 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(256)] ulong Xn) { - //ADCS (X0/W0), (X1, W1), (X2/W2) - AThreadState ThreadState = SingleOpcode(Opcode, X1: A, X2: B, Carry: CarryState); - Assert.Multiple(() => + uint Opcode = 0xDAC01400; // CLS X0, X0 + Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0); + + ulong _X31 = TestContext.CurrentContext.Random.NextULong(); + AThreadState ThreadState = SingleOpcode(Opcode, X1: Xn, X31: _X31); + + if (Rd != 31) { - Assert.IsFalse(ThreadState.Overflow); - Assert.AreEqual(Negative, ThreadState.Negative); - Assert.AreEqual(Zero, ThreadState.Zero); - Assert.AreEqual(Carry, ThreadState.Carry); - Assert.AreEqual(Result, ThreadState.X0); - }); - } - - [Test] - public void Add() - { - // ADD X0, X1, X2 - AThreadState ThreadState = SingleOpcode(0x8B020020, X1: 1, X2: 2); - Assert.AreEqual(3, ThreadState.X0); - } + Bits Op = new Bits(Opcode); - [TestCase(2u, false, false)] - [TestCase(5u, false, false)] - [TestCase(7u, false, false)] - [TestCase(0xFFFFFFFFu, false, true )] - [TestCase(0xFFFFFFFBu, true, true )] - public void Adds(uint A, bool Zero, bool Carry) - { - //ADDS WZR, WSP, #5 - AThreadState ThreadState = SingleOpcode(0x310017FF, X31: A); - Assert.Multiple(() => + AArch64.X((int)Rn, new Bits(Xn)); + Base.Cls(Op[31], Op[9, 5], Op[4, 0]); + ulong Xd = AArch64.X(64, (int)Rd).ToUInt64(); + + Assert.That((ulong)ThreadState.X0, Is.EqualTo(Xd)); + } + else { - Assert.IsFalse(ThreadState.Negative); - Assert.IsFalse(ThreadState.Overflow); - Assert.AreEqual(Zero, ThreadState.Zero); - Assert.AreEqual(Carry, ThreadState.Carry); - Assert.AreEqual(A, ThreadState.X31); - }); + Assert.That((ulong)ThreadState.X31, Is.EqualTo(_X31)); + } } - [TestCase(0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFul, true, false)] - [TestCase(0xFFFFFFFFu, 0x00000000u, 0x00000000ul, false, true)] - [TestCase(0x12345678u, 0x7324A993u, 0x12240010ul, false, false)] - public void Ands(uint A, uint B, ulong Result, bool Negative, bool Zero) + [Test, Description("CLS , ")] + public void Cls_32bit([Values(0u, 31u)] uint Rd, + [Values(1u, 31u)] uint Rn, + [Values(0x00000000u, 0x7FFFFFFFu, + 0x80000000u, 0xFFFFFFFFu)] [Random(256)] uint Wn) { - // ANDS W0, W1, W2 - uint Opcode = 0x6A020020; - AThreadState ThreadState = SingleOpcode(Opcode, X1: A, X2: B); - Assert.Multiple(() => + uint Opcode = 0x5AC01400; // CLS W0, W0 + Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0); + + uint _W31 = TestContext.CurrentContext.Random.NextUInt(); + AThreadState ThreadState = SingleOpcode(Opcode, X1: Wn, X31: _W31); + + if (Rd != 31) { - Assert.AreEqual(Result, ThreadState.X0); - Assert.AreEqual(Negative, ThreadState.Negative); - Assert.AreEqual(Zero, ThreadState.Zero); - }); - } + Bits Op = new Bits(Opcode); - [TestCase(0x0000FF44u, 0x00000004u, 0x00000FF4u)] - [TestCase(0x00000000u, 0x00000004u, 0x00000000u)] - [TestCase(0x0000FF44u, 0x00000008u, 0x000000FFu)] - [TestCase(0xFFFFFFFFu, 0x00000004u, 0xFFFFFFFFu)] - [TestCase(0xFFFFFFFFu, 0x00000008u, 0xFFFFFFFFu)] - [TestCase(0xFFFFFFFFu, 0x00000020u, 0xFFFFFFFFu)] - [TestCase(0x0FFFFFFFu, 0x0000001Cu, 0x00000000u)] - [TestCase(0x80000000u, 0x0000001Fu, 0xFFFFFFFFu)] - [TestCase(0xCAFE0000u, 0x00000020u, 0xCAFE0000u)] - public void Asrv32(uint A, uint ShiftValue, uint Result) - { - // ASRV W0, W1, W2 - AThreadState ThreadState = SingleOpcode(0x1AC22820, X1: A, X2: ShiftValue); - Assert.AreEqual(Result, ThreadState.X0); - } + AArch64.X((int)Rn, new Bits(Wn)); + Base.Cls(Op[31], Op[9, 5], Op[4, 0]); + uint Wd = AArch64.X(32, (int)Rd).ToUInt32(); - [TestCase(0x000000000000FF44ul, 0x00000004u, 0x0000000000000FF4ul)] - [TestCase(0x0000000000000000ul, 0x00000004u, 0x0000000000000000ul)] - [TestCase(0x000000000000FF44ul, 0x00000008u, 0x00000000000000FFul)] - [TestCase(0x00000000FFFFFFFFul, 0x00000004u, 0x000000000FFFFFFFul)] - [TestCase(0x00000000FFFFFFFFul, 0x00000008u, 0x0000000000FFFFFFul)] - [TestCase(0x00000000FFFFFFFFul, 0x00000020u, 0x0000000000000000ul)] - [TestCase(0x000000000FFFFFFFul, 0x0000001Cu, 0x0000000000000000ul)] - [TestCase(0x000CC4488FFFFFFFul, 0x0000001Cu, 0x0000000000CC4488ul)] - [TestCase(0xFFFFFFFFFFFFFFFFul, 0x0000001Cu, 0xFFFFFFFFFFFFFFFFul)] - [TestCase(0x8000000000000000ul, 0x0000003Fu, 0xFFFFFFFFFFFFFFFFul)] - [TestCase(0xCAFE000000000000ul, 0x00000040u, 0xCAFE000000000000ul)] - public void Asrv64(ulong A, uint ShiftValue, ulong Result) - { - // ASRV X0, X1, X2 - AThreadState ThreadState = SingleOpcode(0x9AC22820, X1: A, X2: ShiftValue); - Assert.AreEqual(Result, ThreadState.X0); - } - - [TestCase(0x01010101u, 0x3200C3E2u)] - [TestCase(0x00F000F0u, 0x320C8FE2u)] - [TestCase(0x00000001u, 0x320003E2u)] - public void OrrBitmasks(uint Bitmask, uint Opcode) - { - // ORR W2, WZR, #Bitmask - Assert.AreEqual(Bitmask, SingleOpcode(Opcode).X2); - } - - [Test] - public void RevX0X0() - { - // REV X0, X0 - AThreadState ThreadState = SingleOpcode(0xDAC00C00, X0: 0xAABBCCDDEEFF1100); - Assert.AreEqual(0x0011FFEEDDCCBBAA, ThreadState.X0); - } - - [Test] - public void RevW1W1() - { - // REV W1, W1 - AThreadState ThreadState = SingleOpcode(0x5AC00821, X1: 0x12345678); - Assert.AreEqual(0x78563412, ThreadState.X1); - } - - [TestCase(0x7A020020u, 4u, 2u, false, false, false, true, 1u)] - [TestCase(0x7A020020u, 4u, 2u, true, false, false, true, 2u)] - [TestCase(0xFA020020u, 4u, 2u, false, false, false, true, 1u)] - [TestCase(0xFA020020u, 4u, 2u, true, false, false, true, 2u)] - [TestCase(0x7A020020u, 4u, 4u, false, true, false, false, 0xFFFFFFFFu)] - [TestCase(0x7A020020u, 4u, 4u, true, false, true, true, 0x0u)] - public void Sbcs(uint Opcode, uint A, uint B, bool CarryState, bool Negative, bool Zero, bool Carry, uint Result) - { - //SBCS (X0/W0), (X1, W1), (X2/W2) - AThreadState ThreadState = SingleOpcode(Opcode, X1: A, X2: B, Carry: CarryState); - Assert.Multiple(() => + Assert.That((uint)ThreadState.X0, Is.EqualTo(Wd)); + } + else { - Assert.IsFalse(ThreadState.Overflow); - Assert.AreEqual(Negative, ThreadState.Negative); - Assert.AreEqual(Zero, ThreadState.Zero); - Assert.AreEqual(Carry, ThreadState.Carry); - Assert.AreEqual(Result, ThreadState.X0); - }); + Assert.That((uint)ThreadState.X31, Is.EqualTo(_W31)); + } } + + [Test, Description("CLZ , ")] + public void Clz_64bit([Values(0u, 31u)] uint Rd, + [Values(1u, 31u)] uint Rn, + [Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul, + 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(256)] ulong Xn) + { + uint Opcode = 0xDAC01000; // CLZ X0, X0 + Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0); + + ulong _X31 = TestContext.CurrentContext.Random.NextULong(); + AThreadState ThreadState = SingleOpcode(Opcode, X1: Xn, X31: _X31); + + if (Rd != 31) + { + Bits Op = new Bits(Opcode); + + AArch64.X((int)Rn, new Bits(Xn)); + Base.Clz(Op[31], Op[9, 5], Op[4, 0]); + ulong Xd = AArch64.X(64, (int)Rd).ToUInt64(); + + Assert.That((ulong)ThreadState.X0, Is.EqualTo(Xd)); + } + else + { + Assert.That((ulong)ThreadState.X31, Is.EqualTo(_X31)); + } + } + + [Test, Description("CLZ , ")] + public void Clz_32bit([Values(0u, 31u)] uint Rd, + [Values(1u, 31u)] uint Rn, + [Values(0x00000000u, 0x7FFFFFFFu, + 0x80000000u, 0xFFFFFFFFu)] [Random(256)] uint Wn) + { + uint Opcode = 0x5AC01000; // CLZ W0, W0 + Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0); + + uint _W31 = TestContext.CurrentContext.Random.NextUInt(); + AThreadState ThreadState = SingleOpcode(Opcode, X1: Wn, X31: _W31); + + if (Rd != 31) + { + Bits Op = new Bits(Opcode); + + AArch64.X((int)Rn, new Bits(Wn)); + Base.Clz(Op[31], Op[9, 5], Op[4, 0]); + uint Wd = AArch64.X(32, (int)Rd).ToUInt32(); + + Assert.That((uint)ThreadState.X0, Is.EqualTo(Wd)); + } + else + { + Assert.That((uint)ThreadState.X31, Is.EqualTo(_W31)); + } + } + + [Test, Description("RBIT , ")] + public void Rbit_64bit([Values(0u, 31u)] uint Rd, + [Values(1u, 31u)] uint Rn, + [Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul, + 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(256)] ulong Xn) + { + uint Opcode = 0xDAC00000; // RBIT X0, X0 + Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0); + + ulong _X31 = TestContext.CurrentContext.Random.NextULong(); + AThreadState ThreadState = SingleOpcode(Opcode, X1: Xn, X31: _X31); + + if (Rd != 31) + { + Bits Op = new Bits(Opcode); + + AArch64.X((int)Rn, new Bits(Xn)); + Base.Rbit(Op[31], Op[9, 5], Op[4, 0]); + ulong Xd = AArch64.X(64, (int)Rd).ToUInt64(); + + Assert.That((ulong)ThreadState.X0, Is.EqualTo(Xd)); + } + else + { + Assert.That((ulong)ThreadState.X31, Is.EqualTo(_X31)); + } + } + + [Test, Description("RBIT , ")] + public void Rbit_32bit([Values(0u, 31u)] uint Rd, + [Values(1u, 31u)] uint Rn, + [Values(0x00000000u, 0x7FFFFFFFu, + 0x80000000u, 0xFFFFFFFFu)] [Random(256)] uint Wn) + { + uint Opcode = 0x5AC00000; // RBIT W0, W0 + Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0); + + uint _W31 = TestContext.CurrentContext.Random.NextUInt(); + AThreadState ThreadState = SingleOpcode(Opcode, X1: Wn, X31: _W31); + + if (Rd != 31) + { + Bits Op = new Bits(Opcode); + + AArch64.X((int)Rn, new Bits(Wn)); + Base.Rbit(Op[31], Op[9, 5], Op[4, 0]); + uint Wd = AArch64.X(32, (int)Rd).ToUInt32(); + + Assert.That((uint)ThreadState.X0, Is.EqualTo(Wd)); + } + else + { + Assert.That((uint)ThreadState.X31, Is.EqualTo(_W31)); + } + } + + [Test, Description("REV16 , ")] + public void Rev16_64bit([Values(0u, 31u)] uint Rd, + [Values(1u, 31u)] uint Rn, + [Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul, + 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(256)] ulong Xn) + { + uint Opcode = 0xDAC00400; // REV16 X0, X0 + Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0); + + ulong _X31 = TestContext.CurrentContext.Random.NextULong(); + AThreadState ThreadState = SingleOpcode(Opcode, X1: Xn, X31: _X31); + + if (Rd != 31) + { + Bits Op = new Bits(Opcode); + + AArch64.X((int)Rn, new Bits(Xn)); + Base.Rev16(Op[31], Op[9, 5], Op[4, 0]); + ulong Xd = AArch64.X(64, (int)Rd).ToUInt64(); + + Assert.That((ulong)ThreadState.X0, Is.EqualTo(Xd)); + } + else + { + Assert.That((ulong)ThreadState.X31, Is.EqualTo(_X31)); + } + } + + [Test, Description("REV16 , ")] + public void Rev16_32bit([Values(0u, 31u)] uint Rd, + [Values(1u, 31u)] uint Rn, + [Values(0x00000000u, 0x7FFFFFFFu, + 0x80000000u, 0xFFFFFFFFu)] [Random(256)] uint Wn) + { + uint Opcode = 0x5AC00400; // REV16 W0, W0 + Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0); + + uint _W31 = TestContext.CurrentContext.Random.NextUInt(); + AThreadState ThreadState = SingleOpcode(Opcode, X1: Wn, X31: _W31); + + if (Rd != 31) + { + Bits Op = new Bits(Opcode); + + AArch64.X((int)Rn, new Bits(Wn)); + Base.Rev16(Op[31], Op[9, 5], Op[4, 0]); + uint Wd = AArch64.X(32, (int)Rd).ToUInt32(); + + Assert.That((uint)ThreadState.X0, Is.EqualTo(Wd)); + } + else + { + Assert.That((uint)ThreadState.X31, Is.EqualTo(_W31)); + } + } + + [Test, Description("REV32 , ")] + public void Rev32_64bit([Values(0u, 31u)] uint Rd, + [Values(1u, 31u)] uint Rn, + [Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul, + 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(256)] ulong Xn) + { + uint Opcode = 0xDAC00800; // REV32 X0, X0 + Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0); + + ulong _X31 = TestContext.CurrentContext.Random.NextULong(); + AThreadState ThreadState = SingleOpcode(Opcode, X1: Xn, X31: _X31); + + if (Rd != 31) + { + Bits Op = new Bits(Opcode); + + AArch64.X((int)Rn, new Bits(Xn)); + Base.Rev32(Op[31], Op[9, 5], Op[4, 0]); + ulong Xd = AArch64.X(64, (int)Rd).ToUInt64(); + + Assert.That((ulong)ThreadState.X0, Is.EqualTo(Xd)); + } + else + { + Assert.That((ulong)ThreadState.X31, Is.EqualTo(_X31)); + } + } + + [Test, Description("REV , ")] + public void Rev32_32bit([Values(0u, 31u)] uint Rd, + [Values(1u, 31u)] uint Rn, + [Values(0x00000000u, 0x7FFFFFFFu, + 0x80000000u, 0xFFFFFFFFu)] [Random(256)] uint Wn) + { + uint Opcode = 0x5AC00800; // REV W0, W0 + Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0); + + uint _W31 = TestContext.CurrentContext.Random.NextUInt(); + AThreadState ThreadState = SingleOpcode(Opcode, X1: Wn, X31: _W31); + + if (Rd != 31) + { + Bits Op = new Bits(Opcode); + + AArch64.X((int)Rn, new Bits(Wn)); + Base.Rev32(Op[31], Op[9, 5], Op[4, 0]); + uint Wd = AArch64.X(32, (int)Rd).ToUInt32(); + + Assert.That((uint)ThreadState.X0, Is.EqualTo(Wd)); + } + else + { + Assert.That((uint)ThreadState.X31, Is.EqualTo(_W31)); + } + } + + [Test, Description("REV64 , ")] + public void Rev64_64bit([Values(0u, 31u)] uint Rd, + [Values(1u, 31u)] uint Rn, + [Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul, + 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(256)] ulong Xn) + { + uint Opcode = 0xDAC00C00; // REV64 X0, X0 + Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0); + + ulong _X31 = TestContext.CurrentContext.Random.NextULong(); + AThreadState ThreadState = SingleOpcode(Opcode, X1: Xn, X31: _X31); + + if (Rd != 31) + { + Bits Op = new Bits(Opcode); + + AArch64.X((int)Rn, new Bits(Xn)); + Base.Rev64(Op[9, 5], Op[4, 0]); + ulong Xd = AArch64.X(64, (int)Rd).ToUInt64(); + + Assert.That((ulong)ThreadState.X0, Is.EqualTo(Xd)); + } + else + { + Assert.That((ulong)ThreadState.X31, Is.EqualTo(_X31)); + } + } +#endif } } diff --git a/Ryujinx.Tests/Cpu/CpuTestAluImm.cs b/Ryujinx.Tests/Cpu/CpuTestAluImm.cs new file mode 100644 index 000000000..5d1f0b6ba --- /dev/null +++ b/Ryujinx.Tests/Cpu/CpuTestAluImm.cs @@ -0,0 +1,811 @@ +//#define AluImm + +using ChocolArm64.State; + +using NUnit.Framework; + +namespace Ryujinx.Tests.Cpu +{ + using Tester; + using Tester.Types; + + [Category("AluImm"), Ignore("Tested: first half of 2018.")] + public sealed class CpuTestAluImm : CpuTest + { +#if AluImm + [SetUp] + public void SetupTester() + { + AArch64.TakeReset(false); + } + + [Test, Description("ADD , , #{, }")] + public void Add_64bit([Values(0u, 31u)] uint Rd, + [Values(1u, 31u)] uint Rn, + [Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul, + 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(8)] ulong Xn_SP, + [Values(0u, 4095u)] [Random(0u, 4095u, 10)] uint imm, + [Values(0b00u, 0b01u)] uint shift) // + { + uint Opcode = 0x91000000; // ADD X0, X0, #0, LSL #0 + Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0); + Opcode |= ((shift & 3) << 22) | ((imm & 4095) << 10); + Bits Op = new Bits(Opcode); + + AThreadState ThreadState; + + if (Rn != 31) + { + ThreadState = SingleOpcode(Opcode, X1: Xn_SP); + + AArch64.X((int)Rn, new Bits(Xn_SP)); + } + else + { + ThreadState = SingleOpcode(Opcode, X31: Xn_SP); + + AArch64.SP(new Bits(Xn_SP)); + } + + Base.Add_Imm(Op[31], Op[23, 22], Op[21, 10], Op[9, 5], Op[4, 0]); + + if (Rd != 31) + { + ulong Xd = AArch64.X(64, (int)Rd).ToUInt64(); + + Assert.That((ulong)ThreadState.X0, Is.EqualTo(Xd)); + } + else + { + ulong SP = AArch64.SP(64).ToUInt64(); + + Assert.That((ulong)ThreadState.X31, Is.EqualTo(SP)); + } + } + + [Test, Description("ADD , , #{, }")] + public void Add_32bit([Values(0u, 31u)] uint Rd, + [Values(1u, 31u)] uint Rn, + [Values(0x00000000u, 0x7FFFFFFFu, + 0x80000000u, 0xFFFFFFFFu)] [Random(8)] uint Wn_WSP, + [Values(0u, 4095u)] [Random(0u, 4095u, 10)] uint imm, + [Values(0b00u, 0b01u)] uint shift) // + { + uint Opcode = 0x11000000; // ADD W0, W0, #0, LSL #0 + Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0); + Opcode |= ((shift & 3) << 22) | ((imm & 4095) << 10); + Bits Op = new Bits(Opcode); + + AThreadState ThreadState; + + if (Rn != 31) + { + ThreadState = SingleOpcode(Opcode, X1: Wn_WSP); + + AArch64.X((int)Rn, new Bits(Wn_WSP)); + } + else + { + ThreadState = SingleOpcode(Opcode, X31: Wn_WSP); + + AArch64.SP(new Bits(Wn_WSP)); + } + + Base.Add_Imm(Op[31], Op[23, 22], Op[21, 10], Op[9, 5], Op[4, 0]); + + if (Rd != 31) + { + uint Wd = AArch64.X(32, (int)Rd).ToUInt32(); + + Assert.That((uint)ThreadState.X0, Is.EqualTo(Wd)); + } + else + { + uint WSP = AArch64.SP(32).ToUInt32(); + + Assert.That((uint)ThreadState.X31, Is.EqualTo(WSP)); + } + } + + [Test, Description("ADDS , , #{, }")] + public void Adds_64bit([Values(0u, 31u)] uint Rd, + [Values(1u, 31u)] uint Rn, + [Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul, + 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(8)] ulong Xn_SP, + [Values(0u, 4095u)] [Random(0u, 4095u, 10)] uint imm, + [Values(0b00u, 0b01u)] uint shift) // + { + uint Opcode = 0xB1000000; // ADDS X0, X0, #0, LSL #0 + Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0); + Opcode |= ((shift & 3) << 22) | ((imm & 4095) << 10); + Bits Op = new Bits(Opcode); + + AThreadState ThreadState; + + if (Rn != 31) + { + ThreadState = SingleOpcode(Opcode, X1: Xn_SP); + + AArch64.X((int)Rn, new Bits(Xn_SP)); + } + else + { + ThreadState = SingleOpcode(Opcode, X31: Xn_SP); + + AArch64.SP(new Bits(Xn_SP)); + } + + Base.Adds_Imm(Op[31], Op[23, 22], Op[21, 10], Op[9, 5], Op[4, 0]); + + if (Rd != 31) + { + ulong Xd = AArch64.X(64, (int)Rd).ToUInt64(); + + Assert.That((ulong)ThreadState.X0, Is.EqualTo(Xd)); + } + else + { + ulong _X31 = AArch64.SP(64).ToUInt64(); + + Assert.That((ulong)ThreadState.X31, Is.EqualTo(_X31)); + } + Assert.Multiple(() => + { + Assert.That(ThreadState.Negative, Is.EqualTo(Shared.PSTATE.N)); + Assert.That(ThreadState.Zero, Is.EqualTo(Shared.PSTATE.Z)); + Assert.That(ThreadState.Carry, Is.EqualTo(Shared.PSTATE.C)); + Assert.That(ThreadState.Overflow, Is.EqualTo(Shared.PSTATE.V)); + }); + } + + [Test, Description("ADDS , , #{, }")] + public void Adds_32bit([Values(0u, 31u)] uint Rd, + [Values(1u, 31u)] uint Rn, + [Values(0x00000000u, 0x7FFFFFFFu, + 0x80000000u, 0xFFFFFFFFu)] [Random(8)] uint Wn_WSP, + [Values(0u, 4095u)] [Random(0u, 4095u, 10)] uint imm, + [Values(0b00u, 0b01u)] uint shift) // + { + uint Opcode = 0x31000000; // ADDS W0, W0, #0, LSL #0 + Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0); + Opcode |= ((shift & 3) << 22) | ((imm & 4095) << 10); + Bits Op = new Bits(Opcode); + + AThreadState ThreadState; + + if (Rn != 31) + { + ThreadState = SingleOpcode(Opcode, X1: Wn_WSP); + + AArch64.X((int)Rn, new Bits(Wn_WSP)); + } + else + { + ThreadState = SingleOpcode(Opcode, X31: Wn_WSP); + + AArch64.SP(new Bits(Wn_WSP)); + } + + Base.Adds_Imm(Op[31], Op[23, 22], Op[21, 10], Op[9, 5], Op[4, 0]); + + if (Rd != 31) + { + uint Wd = AArch64.X(32, (int)Rd).ToUInt32(); + + Assert.That((uint)ThreadState.X0, Is.EqualTo(Wd)); + } + else + { + uint _W31 = AArch64.SP(32).ToUInt32(); + + Assert.That((uint)ThreadState.X31, Is.EqualTo(_W31)); + } + Assert.Multiple(() => + { + Assert.That(ThreadState.Negative, Is.EqualTo(Shared.PSTATE.N)); + Assert.That(ThreadState.Zero, Is.EqualTo(Shared.PSTATE.Z)); + Assert.That(ThreadState.Carry, Is.EqualTo(Shared.PSTATE.C)); + Assert.That(ThreadState.Overflow, Is.EqualTo(Shared.PSTATE.V)); + }); + } + + [Test, Description("AND , , #")] + public void And_N1_64bit([Values(0u, 31u)] uint Rd, + [Values(1u, 31u)] uint Rn, + [Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul, + 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(2)] ulong Xn, + [Values(0u, 31u, 32u, 62u)] [Random(0u, 62u, 2)] uint imms, // + [Values(0u, 31u, 32u, 63u)] [Random(0u, 63u, 2)] uint immr) // + { + uint Opcode = 0x92400000; // AND X0, X0, #0x1 + Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0); + Opcode |= ((immr & 63) << 16) | ((imms & 63) << 10); + Bits Op = new Bits(Opcode); + + ulong _X31 = TestContext.CurrentContext.Random.NextULong(); + AThreadState ThreadState = SingleOpcode(Opcode, X1: Xn, X31: _X31); + + AArch64.X((int)Rn, new Bits(Xn)); + Base.And_Imm(Op[31], Op[22], Op[21, 16], Op[15, 10], Op[9, 5], Op[4, 0]); + + if (Rd != 31) + { + ulong Xd = AArch64.X(64, (int)Rd).ToUInt64(); + + Assert.That((ulong)ThreadState.X0, Is.EqualTo(Xd)); + } + else + { + ulong SP = AArch64.SP(64).ToUInt64(); + + Assert.That((ulong)ThreadState.X31, Is.EqualTo(SP)); + } + } + + [Test, Description("AND , , #")] + public void And_N0_64bit([Values(0u, 31u)] uint Rd, + [Values(1u, 31u)] uint Rn, + [Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul, + 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(2)] ulong Xn, + [Values(0u, 15u, 16u, 30u)] [Random(0u, 30u, 2)] uint imms, // + [Values(0u, 15u, 16u, 31u)] [Random(0u, 31u, 2)] uint immr) // + { + uint Opcode = 0x92000000; // AND X0, X0, #0x100000001 + Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0); + Opcode |= ((immr & 63) << 16) | ((imms & 63) << 10); + Bits Op = new Bits(Opcode); + + ulong _X31 = TestContext.CurrentContext.Random.NextULong(); + AThreadState ThreadState = SingleOpcode(Opcode, X1: Xn, X31: _X31); + + AArch64.X((int)Rn, new Bits(Xn)); + Base.And_Imm(Op[31], Op[22], Op[21, 16], Op[15, 10], Op[9, 5], Op[4, 0]); + + if (Rd != 31) + { + ulong Xd = AArch64.X(64, (int)Rd).ToUInt64(); + + Assert.That((ulong)ThreadState.X0, Is.EqualTo(Xd)); + } + else + { + ulong SP = AArch64.SP(64).ToUInt64(); + + Assert.That((ulong)ThreadState.X31, Is.EqualTo(SP)); + } + } + + [Test, Description("AND , , #")] + public void And_32bit([Values(0u, 31u)] uint Rd, + [Values(1u, 31u)] uint Rn, + [Values(0x00000000u, 0x7FFFFFFFu, + 0x80000000u, 0xFFFFFFFFu)] [Random(2)] uint Wn, + [Values(0u, 15u, 16u, 30u)] [Random(0u, 30u, 2)] uint imms, // + [Values(0u, 15u, 16u, 31u)] [Random(0u, 31u, 2)] uint immr) // + { + uint Opcode = 0x12000000; // AND W0, W0, #0x1 + Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0); + Opcode |= ((immr & 63) << 16) | ((imms & 63) << 10); + Bits Op = new Bits(Opcode); + + uint _W31 = TestContext.CurrentContext.Random.NextUInt(); + AThreadState ThreadState = SingleOpcode(Opcode, X1: Wn, X31: _W31); + + AArch64.X((int)Rn, new Bits(Wn)); + Base.And_Imm(Op[31], Op[22], Op[21, 16], Op[15, 10], Op[9, 5], Op[4, 0]); + + if (Rd != 31) + { + uint Wd = AArch64.X(32, (int)Rd).ToUInt32(); + + Assert.That((uint)ThreadState.X0, Is.EqualTo(Wd)); + } + else + { + uint WSP = AArch64.SP(32).ToUInt32(); + + Assert.That((uint)ThreadState.X31, Is.EqualTo(WSP)); + } + } + + [Test, Description("ANDS , , #")] + public void Ands_N1_64bit([Values(0u, 31u)] uint Rd, + [Values(1u, 31u)] uint Rn, + [Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul, + 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(2)] ulong Xn, + [Values(0u, 31u, 32u, 62u)] [Random(0u, 62u, 2)] uint imms, // + [Values(0u, 31u, 32u, 63u)] [Random(0u, 63u, 2)] uint immr) // + { + uint Opcode = 0xF2400000; // ANDS X0, X0, #0x1 + Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0); + Opcode |= ((immr & 63) << 16) | ((imms & 63) << 10); + Bits Op = new Bits(Opcode); + + ulong _X31 = TestContext.CurrentContext.Random.NextULong(); + AThreadState ThreadState = SingleOpcode(Opcode, X1: Xn, X31: _X31); + + AArch64.X((int)Rn, new Bits(Xn)); + Base.Ands_Imm(Op[31], Op[22], Op[21, 16], Op[15, 10], Op[9, 5], Op[4, 0]); + ulong Xd = AArch64.X(64, (int)Rd).ToUInt64(); + + if (Rd != 31) + { + Assert.That((ulong)ThreadState.X0, Is.EqualTo(Xd)); + } + else + { + Assert.That((ulong)ThreadState.X31, Is.EqualTo(_X31)); + } + Assert.Multiple(() => + { + Assert.That(ThreadState.Negative, Is.EqualTo(Shared.PSTATE.N)); + Assert.That(ThreadState.Zero, Is.EqualTo(Shared.PSTATE.Z)); + Assert.That(ThreadState.Carry, Is.EqualTo(Shared.PSTATE.C)); + Assert.That(ThreadState.Overflow, Is.EqualTo(Shared.PSTATE.V)); + }); + } + + [Test, Description("ANDS , , #")] + public void Ands_N0_64bit([Values(0u, 31u)] uint Rd, + [Values(1u, 31u)] uint Rn, + [Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul, + 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(2)] ulong Xn, + [Values(0u, 15u, 16u, 30u)] [Random(0u, 30u, 2)] uint imms, // + [Values(0u, 15u, 16u, 31u)] [Random(0u, 31u, 2)] uint immr) // + { + uint Opcode = 0xF2000000; // ANDS X0, X0, #0x100000001 + Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0); + Opcode |= ((immr & 63) << 16) | ((imms & 63) << 10); + Bits Op = new Bits(Opcode); + + ulong _X31 = TestContext.CurrentContext.Random.NextULong(); + AThreadState ThreadState = SingleOpcode(Opcode, X1: Xn, X31: _X31); + + AArch64.X((int)Rn, new Bits(Xn)); + Base.Ands_Imm(Op[31], Op[22], Op[21, 16], Op[15, 10], Op[9, 5], Op[4, 0]); + ulong Xd = AArch64.X(64, (int)Rd).ToUInt64(); + + if (Rd != 31) + { + Assert.That((ulong)ThreadState.X0, Is.EqualTo(Xd)); + } + else + { + Assert.That((ulong)ThreadState.X31, Is.EqualTo(_X31)); + } + Assert.Multiple(() => + { + Assert.That(ThreadState.Negative, Is.EqualTo(Shared.PSTATE.N)); + Assert.That(ThreadState.Zero, Is.EqualTo(Shared.PSTATE.Z)); + Assert.That(ThreadState.Carry, Is.EqualTo(Shared.PSTATE.C)); + Assert.That(ThreadState.Overflow, Is.EqualTo(Shared.PSTATE.V)); + }); + } + + [Test, Description("ANDS , , #")] + public void Ands_32bit([Values(0u, 31u)] uint Rd, + [Values(1u, 31u)] uint Rn, + [Values(0x00000000u, 0x7FFFFFFFu, + 0x80000000u, 0xFFFFFFFFu)] [Random(2)] uint Wn, + [Values(0u, 15u, 16u, 30u)] [Random(0u, 30u, 2)] uint imms, // + [Values(0u, 15u, 16u, 31u)] [Random(0u, 31u, 2)] uint immr) // + { + uint Opcode = 0x72000000; // ANDS W0, W0, #0x1 + Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0); + Opcode |= ((immr & 63) << 16) | ((imms & 63) << 10); + Bits Op = new Bits(Opcode); + + uint _W31 = TestContext.CurrentContext.Random.NextUInt(); + AThreadState ThreadState = SingleOpcode(Opcode, X1: Wn, X31: _W31); + + AArch64.X((int)Rn, new Bits(Wn)); + Base.Ands_Imm(Op[31], Op[22], Op[21, 16], Op[15, 10], Op[9, 5], Op[4, 0]); + uint Wd = AArch64.X(32, (int)Rd).ToUInt32(); + + if (Rd != 31) + { + Assert.That((uint)ThreadState.X0, Is.EqualTo(Wd)); + } + else + { + Assert.That((uint)ThreadState.X31, Is.EqualTo(_W31)); + } + Assert.Multiple(() => + { + Assert.That(ThreadState.Negative, Is.EqualTo(Shared.PSTATE.N)); + Assert.That(ThreadState.Zero, Is.EqualTo(Shared.PSTATE.Z)); + Assert.That(ThreadState.Carry, Is.EqualTo(Shared.PSTATE.C)); + Assert.That(ThreadState.Overflow, Is.EqualTo(Shared.PSTATE.V)); + }); + } + + [Test, Description("EOR , , #")] + public void Eor_N1_64bit([Values(0u, 31u)] uint Rd, + [Values(1u, 31u)] uint Rn, + [Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul, + 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(2)] ulong Xn, + [Values(0u, 31u, 32u, 62u)] [Random(0u, 62u, 2)] uint imms, // + [Values(0u, 31u, 32u, 63u)] [Random(0u, 63u, 2)] uint immr) // + { + uint Opcode = 0xD2400000; // EOR X0, X0, #0x1 + Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0); + Opcode |= ((immr & 63) << 16) | ((imms & 63) << 10); + Bits Op = new Bits(Opcode); + + ulong _X31 = TestContext.CurrentContext.Random.NextULong(); + AThreadState ThreadState = SingleOpcode(Opcode, X1: Xn, X31: _X31); + + AArch64.X((int)Rn, new Bits(Xn)); + Base.Eor_Imm(Op[31], Op[22], Op[21, 16], Op[15, 10], Op[9, 5], Op[4, 0]); + + if (Rd != 31) + { + ulong Xd = AArch64.X(64, (int)Rd).ToUInt64(); + + Assert.That((ulong)ThreadState.X0, Is.EqualTo(Xd)); + } + else + { + ulong SP = AArch64.SP(64).ToUInt64(); + + Assert.That((ulong)ThreadState.X31, Is.EqualTo(SP)); + } + } + + [Test, Description("EOR , , #")] + public void Eor_N0_64bit([Values(0u, 31u)] uint Rd, + [Values(1u, 31u)] uint Rn, + [Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul, + 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(2)] ulong Xn, + [Values(0u, 15u, 16u, 30u)] [Random(0u, 30u, 2)] uint imms, // + [Values(0u, 15u, 16u, 31u)] [Random(0u, 31u, 2)] uint immr) // + { + uint Opcode = 0xD2000000; // EOR X0, X0, #0x100000001 + Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0); + Opcode |= ((immr & 63) << 16) | ((imms & 63) << 10); + Bits Op = new Bits(Opcode); + + ulong _X31 = TestContext.CurrentContext.Random.NextULong(); + AThreadState ThreadState = SingleOpcode(Opcode, X1: Xn, X31: _X31); + + AArch64.X((int)Rn, new Bits(Xn)); + Base.Eor_Imm(Op[31], Op[22], Op[21, 16], Op[15, 10], Op[9, 5], Op[4, 0]); + + if (Rd != 31) + { + ulong Xd = AArch64.X(64, (int)Rd).ToUInt64(); + + Assert.That((ulong)ThreadState.X0, Is.EqualTo(Xd)); + } + else + { + ulong SP = AArch64.SP(64).ToUInt64(); + + Assert.That((ulong)ThreadState.X31, Is.EqualTo(SP)); + } + } + + [Test, Description("EOR , , #")] + public void Eor_32bit([Values(0u, 31u)] uint Rd, + [Values(1u, 31u)] uint Rn, + [Values(0x00000000u, 0x7FFFFFFFu, + 0x80000000u, 0xFFFFFFFFu)] [Random(2)] uint Wn, + [Values(0u, 15u, 16u, 30u)] [Random(0u, 30u, 2)] uint imms, // + [Values(0u, 15u, 16u, 31u)] [Random(0u, 31u, 2)] uint immr) // + { + uint Opcode = 0x52000000; // EOR W0, W0, #0x1 + Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0); + Opcode |= ((immr & 63) << 16) | ((imms & 63) << 10); + Bits Op = new Bits(Opcode); + + uint _W31 = TestContext.CurrentContext.Random.NextUInt(); + AThreadState ThreadState = SingleOpcode(Opcode, X1: Wn, X31: _W31); + + AArch64.X((int)Rn, new Bits(Wn)); + Base.Eor_Imm(Op[31], Op[22], Op[21, 16], Op[15, 10], Op[9, 5], Op[4, 0]); + + if (Rd != 31) + { + uint Wd = AArch64.X(32, (int)Rd).ToUInt32(); + + Assert.That((uint)ThreadState.X0, Is.EqualTo(Wd)); + } + else + { + uint WSP = AArch64.SP(32).ToUInt32(); + + Assert.That((uint)ThreadState.X31, Is.EqualTo(WSP)); + } + } + + [Test, Description("ORR , , #")] + public void Orr_N1_64bit([Values(0u, 31u)] uint Rd, + [Values(1u, 31u)] uint Rn, + [Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul, + 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(2)] ulong Xn, + [Values(0u, 31u, 32u, 62u)] [Random(0u, 62u, 2)] uint imms, // + [Values(0u, 31u, 32u, 63u)] [Random(0u, 63u, 2)] uint immr) // + { + uint Opcode = 0xB2400000; // ORR X0, X0, #0x1 + Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0); + Opcode |= ((immr & 63) << 16) | ((imms & 63) << 10); + Bits Op = new Bits(Opcode); + + ulong _X31 = TestContext.CurrentContext.Random.NextULong(); + AThreadState ThreadState = SingleOpcode(Opcode, X1: Xn, X31: _X31); + + AArch64.X((int)Rn, new Bits(Xn)); + Base.Orr_Imm(Op[31], Op[22], Op[21, 16], Op[15, 10], Op[9, 5], Op[4, 0]); + + if (Rd != 31) + { + ulong Xd = AArch64.X(64, (int)Rd).ToUInt64(); + + Assert.That((ulong)ThreadState.X0, Is.EqualTo(Xd)); + } + else + { + ulong SP = AArch64.SP(64).ToUInt64(); + + Assert.That((ulong)ThreadState.X31, Is.EqualTo(SP)); + } + } + + [Test, Description("ORR , , #")] + public void Orr_N0_64bit([Values(0u, 31u)] uint Rd, + [Values(1u, 31u)] uint Rn, + [Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul, + 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(2)] ulong Xn, + [Values(0u, 15u, 16u, 30u)] [Random(0u, 30u, 2)] uint imms, // + [Values(0u, 15u, 16u, 31u)] [Random(0u, 31u, 2)] uint immr) // + { + uint Opcode = 0xB2000000; // ORR X0, X0, #0x100000001 + Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0); + Opcode |= ((immr & 63) << 16) | ((imms & 63) << 10); + Bits Op = new Bits(Opcode); + + ulong _X31 = TestContext.CurrentContext.Random.NextULong(); + AThreadState ThreadState = SingleOpcode(Opcode, X1: Xn, X31: _X31); + + AArch64.X((int)Rn, new Bits(Xn)); + Base.Orr_Imm(Op[31], Op[22], Op[21, 16], Op[15, 10], Op[9, 5], Op[4, 0]); + + if (Rd != 31) + { + ulong Xd = AArch64.X(64, (int)Rd).ToUInt64(); + + Assert.That((ulong)ThreadState.X0, Is.EqualTo(Xd)); + } + else + { + ulong SP = AArch64.SP(64).ToUInt64(); + + Assert.That((ulong)ThreadState.X31, Is.EqualTo(SP)); + } + } + + [Test, Description("ORR , , #")] + public void Orr_32bit([Values(0u, 31u)] uint Rd, + [Values(1u, 31u)] uint Rn, + [Values(0x00000000u, 0x7FFFFFFFu, + 0x80000000u, 0xFFFFFFFFu)] [Random(2)] uint Wn, + [Values(0u, 15u, 16u, 30u)] [Random(0u, 30u, 2)] uint imms, // + [Values(0u, 15u, 16u, 31u)] [Random(0u, 31u, 2)] uint immr) // + { + uint Opcode = 0x32000000; // ORR W0, W0, #0x1 + Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0); + Opcode |= ((immr & 63) << 16) | ((imms & 63) << 10); + Bits Op = new Bits(Opcode); + + uint _W31 = TestContext.CurrentContext.Random.NextUInt(); + AThreadState ThreadState = SingleOpcode(Opcode, X1: Wn, X31: _W31); + + AArch64.X((int)Rn, new Bits(Wn)); + Base.Orr_Imm(Op[31], Op[22], Op[21, 16], Op[15, 10], Op[9, 5], Op[4, 0]); + + if (Rd != 31) + { + uint Wd = AArch64.X(32, (int)Rd).ToUInt32(); + + Assert.That((uint)ThreadState.X0, Is.EqualTo(Wd)); + } + else + { + uint WSP = AArch64.SP(32).ToUInt32(); + + Assert.That((uint)ThreadState.X31, Is.EqualTo(WSP)); + } + } + + [Test, Description("SUB , , #{, }")] + public void Sub_64bit([Values(0u, 31u)] uint Rd, + [Values(1u, 31u)] uint Rn, + [Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul, + 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(8)] ulong Xn_SP, + [Values(0u, 4095u)] [Random(0u, 4095u, 10)] uint imm, + [Values(0b00u, 0b01u)] uint shift) // + { + uint Opcode = 0xD1000000; // SUB X0, X0, #0, LSL #0 + Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0); + Opcode |= ((shift & 3) << 22) | ((imm & 4095) << 10); + Bits Op = new Bits(Opcode); + + AThreadState ThreadState; + + if (Rn != 31) + { + ThreadState = SingleOpcode(Opcode, X1: Xn_SP); + + AArch64.X((int)Rn, new Bits(Xn_SP)); + } + else + { + ThreadState = SingleOpcode(Opcode, X31: Xn_SP); + + AArch64.SP(new Bits(Xn_SP)); + } + + Base.Sub_Imm(Op[31], Op[23, 22], Op[21, 10], Op[9, 5], Op[4, 0]); + + if (Rd != 31) + { + ulong Xd = AArch64.X(64, (int)Rd).ToUInt64(); + + Assert.That((ulong)ThreadState.X0, Is.EqualTo(Xd)); + } + else + { + ulong SP = AArch64.SP(64).ToUInt64(); + + Assert.That((ulong)ThreadState.X31, Is.EqualTo(SP)); + } + } + + [Test, Description("SUB , , #{, }")] + public void Sub_32bit([Values(0u, 31u)] uint Rd, + [Values(1u, 31u)] uint Rn, + [Values(0x00000000u, 0x7FFFFFFFu, + 0x80000000u, 0xFFFFFFFFu)] [Random(8)] uint Wn_WSP, + [Values(0u, 4095u)] [Random(0u, 4095u, 10)] uint imm, + [Values(0b00u, 0b01u)] uint shift) // + { + uint Opcode = 0x51000000; // SUB W0, W0, #0, LSL #0 + Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0); + Opcode |= ((shift & 3) << 22) | ((imm & 4095) << 10); + Bits Op = new Bits(Opcode); + + AThreadState ThreadState; + + if (Rn != 31) + { + ThreadState = SingleOpcode(Opcode, X1: Wn_WSP); + + AArch64.X((int)Rn, new Bits(Wn_WSP)); + } + else + { + ThreadState = SingleOpcode(Opcode, X31: Wn_WSP); + + AArch64.SP(new Bits(Wn_WSP)); + } + + Base.Sub_Imm(Op[31], Op[23, 22], Op[21, 10], Op[9, 5], Op[4, 0]); + + if (Rd != 31) + { + uint Wd = AArch64.X(32, (int)Rd).ToUInt32(); + + Assert.That((uint)ThreadState.X0, Is.EqualTo(Wd)); + } + else + { + uint WSP = AArch64.SP(32).ToUInt32(); + + Assert.That((uint)ThreadState.X31, Is.EqualTo(WSP)); + } + } + + [Test, Description("SUBS , , #{, }")] + public void Subs_64bit([Values(0u, 31u)] uint Rd, + [Values(1u, 31u)] uint Rn, + [Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul, + 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(8)] ulong Xn_SP, + [Values(0u, 4095u)] [Random(0u, 4095u, 10)] uint imm, + [Values(0b00u, 0b01u)] uint shift) // + { + uint Opcode = 0xF1000000; // SUBS X0, X0, #0, LSL #0 + Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0); + Opcode |= ((shift & 3) << 22) | ((imm & 4095) << 10); + Bits Op = new Bits(Opcode); + + AThreadState ThreadState; + + if (Rn != 31) + { + ThreadState = SingleOpcode(Opcode, X1: Xn_SP); + + AArch64.X((int)Rn, new Bits(Xn_SP)); + } + else + { + ThreadState = SingleOpcode(Opcode, X31: Xn_SP); + + AArch64.SP(new Bits(Xn_SP)); + } + + Base.Subs_Imm(Op[31], Op[23, 22], Op[21, 10], Op[9, 5], Op[4, 0]); + + if (Rd != 31) + { + ulong Xd = AArch64.X(64, (int)Rd).ToUInt64(); + + Assert.That((ulong)ThreadState.X0, Is.EqualTo(Xd)); + } + else + { + ulong _X31 = AArch64.SP(64).ToUInt64(); + + Assert.That((ulong)ThreadState.X31, Is.EqualTo(_X31)); + } + Assert.Multiple(() => + { + Assert.That(ThreadState.Negative, Is.EqualTo(Shared.PSTATE.N)); + Assert.That(ThreadState.Zero, Is.EqualTo(Shared.PSTATE.Z)); + Assert.That(ThreadState.Carry, Is.EqualTo(Shared.PSTATE.C)); + Assert.That(ThreadState.Overflow, Is.EqualTo(Shared.PSTATE.V)); + }); + } + + [Test, Description("SUBS , , #{, }")] + public void Subs_32bit([Values(0u, 31u)] uint Rd, + [Values(1u, 31u)] uint Rn, + [Values(0x00000000u, 0x7FFFFFFFu, + 0x80000000u, 0xFFFFFFFFu)] [Random(8)] uint Wn_WSP, + [Values(0u, 4095u)] [Random(0u, 4095u, 10)] uint imm, + [Values(0b00u, 0b01u)] uint shift) // + { + uint Opcode = 0x71000000; // SUBS W0, W0, #0, LSL #0 + Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0); + Opcode |= ((shift & 3) << 22) | ((imm & 4095) << 10); + Bits Op = new Bits(Opcode); + + AThreadState ThreadState; + + if (Rn != 31) + { + ThreadState = SingleOpcode(Opcode, X1: Wn_WSP); + + AArch64.X((int)Rn, new Bits(Wn_WSP)); + } + else + { + ThreadState = SingleOpcode(Opcode, X31: Wn_WSP); + + AArch64.SP(new Bits(Wn_WSP)); + } + + Base.Subs_Imm(Op[31], Op[23, 22], Op[21, 10], Op[9, 5], Op[4, 0]); + + if (Rd != 31) + { + uint Wd = AArch64.X(32, (int)Rd).ToUInt32(); + + Assert.That((uint)ThreadState.X0, Is.EqualTo(Wd)); + } + else + { + uint _W31 = AArch64.SP(32).ToUInt32(); + + Assert.That((uint)ThreadState.X31, Is.EqualTo(_W31)); + } + Assert.Multiple(() => + { + Assert.That(ThreadState.Negative, Is.EqualTo(Shared.PSTATE.N)); + Assert.That(ThreadState.Zero, Is.EqualTo(Shared.PSTATE.Z)); + Assert.That(ThreadState.Carry, Is.EqualTo(Shared.PSTATE.C)); + Assert.That(ThreadState.Overflow, Is.EqualTo(Shared.PSTATE.V)); + }); + } +#endif + } +} diff --git a/Ryujinx.Tests/Cpu/CpuTestAluRs.cs b/Ryujinx.Tests/Cpu/CpuTestAluRs.cs new file mode 100644 index 000000000..b81f7100c --- /dev/null +++ b/Ryujinx.Tests/Cpu/CpuTestAluRs.cs @@ -0,0 +1,1911 @@ +//#define AluRs + +using ChocolArm64.State; + +using NUnit.Framework; + +namespace Ryujinx.Tests.Cpu +{ + using Tester; + using Tester.Types; + + [Category("AluRs"), Ignore("Tested: first half of 2018.")] + public sealed class CpuTestAluRs : CpuTest + { +#if AluRs + [SetUp] + public void SetupTester() + { + AArch64.TakeReset(false); + } + + [Test, Description("ADC , , ")] + public void Adc_64bit([Values(0u, 31u)] uint Rd, + [Values(1u, 31u)] uint Rn, + [Values(2u, 31u)] uint Rm, + [Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul, + 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(4)] ulong Xn, + [Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul, + 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(4)] ulong Xm, + [Values] bool CarryIn) + { + uint Opcode = 0x9A000000; // ADC X0, X0, X0 + Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); + + ulong _X31 = TestContext.CurrentContext.Random.NextULong(); + AThreadState ThreadState = SingleOpcode(Opcode, X1: Xn, X2: Xm, X31: _X31, Carry: CarryIn); + + if (Rd != 31) + { + Bits Op = new Bits(Opcode); + + AArch64.X((int)Rn, new Bits(Xn)); + AArch64.X((int)Rm, new Bits(Xm)); + Shared.PSTATE.C = CarryIn; + Base.Adc(Op[31], Op[20, 16], Op[9, 5], Op[4, 0]); + ulong Xd = AArch64.X(64, (int)Rd).ToUInt64(); + + Assert.That((ulong)ThreadState.X0, Is.EqualTo(Xd)); + } + else + { + Assert.That((ulong)ThreadState.X31, Is.EqualTo(_X31)); + } + } + + [Test, Description("ADC , , ")] + public void Adc_32bit([Values(0u, 31u)] uint Rd, + [Values(1u, 31u)] uint Rn, + [Values(2u, 31u)] uint Rm, + [Values(0x00000000u, 0x7FFFFFFFu, + 0x80000000u, 0xFFFFFFFFu)] [Random(4)] uint Wn, + [Values(0x00000000u, 0x7FFFFFFFu, + 0x80000000u, 0xFFFFFFFFu)] [Random(4)] uint Wm, + [Values] bool CarryIn) + { + uint Opcode = 0x1A000000; // ADC W0, W0, W0 + Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); + + uint _W31 = TestContext.CurrentContext.Random.NextUInt(); + AThreadState ThreadState = SingleOpcode(Opcode, X1: Wn, X2: Wm, X31: _W31, Carry: CarryIn); + + if (Rd != 31) + { + Bits Op = new Bits(Opcode); + + AArch64.X((int)Rn, new Bits(Wn)); + AArch64.X((int)Rm, new Bits(Wm)); + Shared.PSTATE.C = CarryIn; + Base.Adc(Op[31], Op[20, 16], Op[9, 5], Op[4, 0]); + uint Wd = AArch64.X(32, (int)Rd).ToUInt32(); + + Assert.That((uint)ThreadState.X0, Is.EqualTo(Wd)); + } + else + { + Assert.That((uint)ThreadState.X31, Is.EqualTo(_W31)); + } + } + + [Test, Description("ADCS , , ")] + public void Adcs_64bit([Values(0u, 31u)] uint Rd, + [Values(1u, 31u)] uint Rn, + [Values(2u, 31u)] uint Rm, + [Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul, + 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(4)] ulong Xn, + [Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul, + 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(4)] ulong Xm, + [Values] bool CarryIn) + { + uint Opcode = 0xBA000000; // ADCS X0, X0, X0 + Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); + Bits Op = new Bits(Opcode); + + ulong _X31 = TestContext.CurrentContext.Random.NextULong(); + AThreadState ThreadState = SingleOpcode(Opcode, X1: Xn, X2: Xm, X31: _X31, Carry: CarryIn); + + AArch64.X((int)Rn, new Bits(Xn)); + AArch64.X((int)Rm, new Bits(Xm)); + Shared.PSTATE.C = CarryIn; + Base.Adcs(Op[31], Op[20, 16], Op[9, 5], Op[4, 0]); + ulong Xd = AArch64.X(64, (int)Rd).ToUInt64(); + + if (Rd != 31) + { + Assert.That((ulong)ThreadState.X0, Is.EqualTo(Xd)); + } + else + { + Assert.That((ulong)ThreadState.X31, Is.EqualTo(_X31)); + } + Assert.Multiple(() => + { + Assert.That(ThreadState.Negative, Is.EqualTo(Shared.PSTATE.N)); + Assert.That(ThreadState.Zero, Is.EqualTo(Shared.PSTATE.Z)); + Assert.That(ThreadState.Carry, Is.EqualTo(Shared.PSTATE.C)); + Assert.That(ThreadState.Overflow, Is.EqualTo(Shared.PSTATE.V)); + }); + } + + [Test, Description("ADCS , , ")] + public void Adcs_32bit([Values(0u, 31u)] uint Rd, + [Values(1u, 31u)] uint Rn, + [Values(2u, 31u)] uint Rm, + [Values(0x00000000u, 0x7FFFFFFFu, + 0x80000000u, 0xFFFFFFFFu)] [Random(4)] uint Wn, + [Values(0x00000000u, 0x7FFFFFFFu, + 0x80000000u, 0xFFFFFFFFu)] [Random(4)] uint Wm, + [Values] bool CarryIn) + { + uint Opcode = 0x3A000000; // ADCS W0, W0, W0 + Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); + Bits Op = new Bits(Opcode); + + uint _W31 = TestContext.CurrentContext.Random.NextUInt(); + AThreadState ThreadState = SingleOpcode(Opcode, X1: Wn, X2: Wm, X31: _W31, Carry: CarryIn); + + AArch64.X((int)Rn, new Bits(Wn)); + AArch64.X((int)Rm, new Bits(Wm)); + Shared.PSTATE.C = CarryIn; + Base.Adcs(Op[31], Op[20, 16], Op[9, 5], Op[4, 0]); + uint Wd = AArch64.X(32, (int)Rd).ToUInt32(); + + if (Rd != 31) + { + Assert.That((uint)ThreadState.X0, Is.EqualTo(Wd)); + } + else + { + Assert.That((uint)ThreadState.X31, Is.EqualTo(_W31)); + } + Assert.Multiple(() => + { + Assert.That(ThreadState.Negative, Is.EqualTo(Shared.PSTATE.N)); + Assert.That(ThreadState.Zero, Is.EqualTo(Shared.PSTATE.Z)); + Assert.That(ThreadState.Carry, Is.EqualTo(Shared.PSTATE.C)); + Assert.That(ThreadState.Overflow, Is.EqualTo(Shared.PSTATE.V)); + }); + } + + [Test, Description("ADD , , {, #}")] + public void Add_64bit([Values(0u, 31u)] uint Rd, + [Values(1u, 31u)] uint Rn, + [Values(2u, 31u)] uint Rm, + [Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul, + 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(1)] ulong Xn, + [Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul, + 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(1)] ulong Xm, + [Values(0b00u, 0b01u, 0b10u)] uint shift, // + [Values(0u, 31u, 32u, 63u)] [Random(0u, 63u, 1)] uint amount) + { + uint Opcode = 0x8B000000; // ADD X0, X0, X0, LSL #0 + Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); + Opcode |= ((shift & 3) << 22) | ((amount & 63) << 10); + + ulong _X31 = TestContext.CurrentContext.Random.NextULong(); + AThreadState ThreadState = SingleOpcode(Opcode, X1: Xn, X2: Xm, X31: _X31); + + if (Rd != 31) + { + Bits Op = new Bits(Opcode); + + AArch64.X((int)Rn, new Bits(Xn)); + AArch64.X((int)Rm, new Bits(Xm)); + Base.Add_Rs(Op[31], Op[23, 22], Op[20, 16], Op[15, 10], Op[9, 5], Op[4, 0]); + ulong Xd = AArch64.X(64, (int)Rd).ToUInt64(); + + Assert.That((ulong)ThreadState.X0, Is.EqualTo(Xd)); + } + else + { + Assert.That((ulong)ThreadState.X31, Is.EqualTo(_X31)); + } + } + + [Test, Description("ADD , , {, #}")] + public void Add_32bit([Values(0u, 31u)] uint Rd, + [Values(1u, 31u)] uint Rn, + [Values(2u, 31u)] uint Rm, + [Values(0x00000000u, 0x7FFFFFFFu, + 0x80000000u, 0xFFFFFFFFu)] [Random(1)] uint Wn, + [Values(0x00000000u, 0x7FFFFFFFu, + 0x80000000u, 0xFFFFFFFFu)] [Random(1)] uint Wm, + [Values(0b00u, 0b01u, 0b10u)] uint shift, // + [Values(0u, 15u, 16u, 31u)] [Random(0u, 31u, 1)] uint amount) + { + uint Opcode = 0x0B000000; // ADD W0, W0, W0, LSL #0 + Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); + Opcode |= ((shift & 3) << 22) | ((amount & 63) << 10); + + uint _W31 = TestContext.CurrentContext.Random.NextUInt(); + AThreadState ThreadState = SingleOpcode(Opcode, X1: Wn, X2: Wm, X31: _W31); + + if (Rd != 31) + { + Bits Op = new Bits(Opcode); + + AArch64.X((int)Rn, new Bits(Wn)); + AArch64.X((int)Rm, new Bits(Wm)); + Base.Add_Rs(Op[31], Op[23, 22], Op[20, 16], Op[15, 10], Op[9, 5], Op[4, 0]); + uint Wd = AArch64.X(32, (int)Rd).ToUInt32(); + + Assert.That((uint)ThreadState.X0, Is.EqualTo(Wd)); + } + else + { + Assert.That((uint)ThreadState.X31, Is.EqualTo(_W31)); + } + } + + [Test, Description("ADDS , , {, #}")] + public void Adds_64bit([Values(0u, 31u)] uint Rd, + [Values(1u, 31u)] uint Rn, + [Values(2u, 31u)] uint Rm, + [Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul, + 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(1)] ulong Xn, + [Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul, + 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(1)] ulong Xm, + [Values(0b00u, 0b01u, 0b10u)] uint shift, // + [Values(0u, 31u, 32u, 63u)] [Random(0u, 63u, 1)] uint amount) + { + uint Opcode = 0xAB000000; // ADDS X0, X0, X0, LSL #0 + Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); + Opcode |= ((shift & 3) << 22) | ((amount & 63) << 10); + Bits Op = new Bits(Opcode); + + ulong _X31 = TestContext.CurrentContext.Random.NextULong(); + AThreadState ThreadState = SingleOpcode(Opcode, X1: Xn, X2: Xm, X31: _X31); + + AArch64.X((int)Rn, new Bits(Xn)); + AArch64.X((int)Rm, new Bits(Xm)); + Base.Adds_Rs(Op[31], Op[23, 22], Op[20, 16], Op[15, 10], Op[9, 5], Op[4, 0]); + ulong Xd = AArch64.X(64, (int)Rd).ToUInt64(); + + if (Rd != 31) + { + Assert.That((ulong)ThreadState.X0, Is.EqualTo(Xd)); + } + else + { + Assert.That((ulong)ThreadState.X31, Is.EqualTo(_X31)); + } + Assert.Multiple(() => + { + Assert.That(ThreadState.Negative, Is.EqualTo(Shared.PSTATE.N)); + Assert.That(ThreadState.Zero, Is.EqualTo(Shared.PSTATE.Z)); + Assert.That(ThreadState.Carry, Is.EqualTo(Shared.PSTATE.C)); + Assert.That(ThreadState.Overflow, Is.EqualTo(Shared.PSTATE.V)); + }); + } + + [Test, Description("ADDS , , {, #}")] + public void Adds_32bit([Values(0u, 31u)] uint Rd, + [Values(1u, 31u)] uint Rn, + [Values(2u, 31u)] uint Rm, + [Values(0x00000000u, 0x7FFFFFFFu, + 0x80000000u, 0xFFFFFFFFu)] [Random(1)] uint Wn, + [Values(0x00000000u, 0x7FFFFFFFu, + 0x80000000u, 0xFFFFFFFFu)] [Random(1)] uint Wm, + [Values(0b00u, 0b01u, 0b10u)] uint shift, // + [Values(0u, 15u, 16u, 31u)] [Random(0u, 31u, 1)] uint amount) + { + uint Opcode = 0x2B000000; // ADDS W0, W0, W0, LSL #0 + Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); + Opcode |= ((shift & 3) << 22) | ((amount & 63) << 10); + Bits Op = new Bits(Opcode); + + uint _W31 = TestContext.CurrentContext.Random.NextUInt(); + AThreadState ThreadState = SingleOpcode(Opcode, X1: Wn, X2: Wm, X31: _W31); + + AArch64.X((int)Rn, new Bits(Wn)); + AArch64.X((int)Rm, new Bits(Wm)); + Base.Adds_Rs(Op[31], Op[23, 22], Op[20, 16], Op[15, 10], Op[9, 5], Op[4, 0]); + uint Wd = AArch64.X(32, (int)Rd).ToUInt32(); + + if (Rd != 31) + { + Assert.That((uint)ThreadState.X0, Is.EqualTo(Wd)); + } + else + { + Assert.That((uint)ThreadState.X31, Is.EqualTo(_W31)); + } + Assert.Multiple(() => + { + Assert.That(ThreadState.Negative, Is.EqualTo(Shared.PSTATE.N)); + Assert.That(ThreadState.Zero, Is.EqualTo(Shared.PSTATE.Z)); + Assert.That(ThreadState.Carry, Is.EqualTo(Shared.PSTATE.C)); + Assert.That(ThreadState.Overflow, Is.EqualTo(Shared.PSTATE.V)); + }); + } + + [Test, Description("AND , , {, #}")] + public void And_64bit([Values(0u, 31u)] uint Rd, + [Values(1u, 31u)] uint Rn, + [Values(2u, 31u)] uint Rm, + [Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul, + 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(1)] ulong Xn, + [Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul, + 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(1)] ulong Xm, + [Values(0b00u, 0b01u, 0b10u, 0b11u)] uint shift, // + [Values(0u, 31u, 32u, 63u)] [Random(0u, 63u, 1)] uint amount) + { + uint Opcode = 0x8A000000; // AND X0, X0, X0, LSL #0 + Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); + Opcode |= ((shift & 3) << 22) | ((amount & 63) << 10); + + ulong _X31 = TestContext.CurrentContext.Random.NextULong(); + AThreadState ThreadState = SingleOpcode(Opcode, X1: Xn, X2: Xm, X31: _X31); + + if (Rd != 31) + { + Bits Op = new Bits(Opcode); + + AArch64.X((int)Rn, new Bits(Xn)); + AArch64.X((int)Rm, new Bits(Xm)); + Base.And_Rs(Op[31], Op[23, 22], Op[20, 16], Op[15, 10], Op[9, 5], Op[4, 0]); + ulong Xd = AArch64.X(64, (int)Rd).ToUInt64(); + + Assert.That((ulong)ThreadState.X0, Is.EqualTo(Xd)); + } + else + { + Assert.That((ulong)ThreadState.X31, Is.EqualTo(_X31)); + } + } + + [Test, Description("AND , , {, #}")] + public void And_32bit([Values(0u, 31u)] uint Rd, + [Values(1u, 31u)] uint Rn, + [Values(2u, 31u)] uint Rm, + [Values(0x00000000u, 0x7FFFFFFFu, + 0x80000000u, 0xFFFFFFFFu)] [Random(1)] uint Wn, + [Values(0x00000000u, 0x7FFFFFFFu, + 0x80000000u, 0xFFFFFFFFu)] [Random(1)] uint Wm, + [Values(0b00u, 0b01u, 0b10u, 0b11u)] uint shift, // + [Values(0u, 15u, 16u, 31u)] [Random(0u, 31u, 1)] uint amount) + { + uint Opcode = 0x0A000000; // AND W0, W0, W0, LSL #0 + Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); + Opcode |= ((shift & 3) << 22) | ((amount & 63) << 10); + + uint _W31 = TestContext.CurrentContext.Random.NextUInt(); + AThreadState ThreadState = SingleOpcode(Opcode, X1: Wn, X2: Wm, X31: _W31); + + if (Rd != 31) + { + Bits Op = new Bits(Opcode); + + AArch64.X((int)Rn, new Bits(Wn)); + AArch64.X((int)Rm, new Bits(Wm)); + Base.And_Rs(Op[31], Op[23, 22], Op[20, 16], Op[15, 10], Op[9, 5], Op[4, 0]); + uint Wd = AArch64.X(32, (int)Rd).ToUInt32(); + + Assert.That((uint)ThreadState.X0, Is.EqualTo(Wd)); + } + else + { + Assert.That((uint)ThreadState.X31, Is.EqualTo(_W31)); + } + } + + [Test, Description("ANDS , , {, #}")] + public void Ands_64bit([Values(0u, 31u)] uint Rd, + [Values(1u, 31u)] uint Rn, + [Values(2u, 31u)] uint Rm, + [Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul, + 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(1)] ulong Xn, + [Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul, + 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(1)] ulong Xm, + [Values(0b00u, 0b01u, 0b10u, 0b11u)] uint shift, // + [Values(0u, 31u, 32u, 63u)] [Random(0u, 63u, 1)] uint amount) + { + uint Opcode = 0xEA000000; // ANDS X0, X0, X0, LSL #0 + Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); + Opcode |= ((shift & 3) << 22) | ((amount & 63) << 10); + Bits Op = new Bits(Opcode); + + ulong _X31 = TestContext.CurrentContext.Random.NextULong(); + AThreadState ThreadState = SingleOpcode(Opcode, X1: Xn, X2: Xm, X31: _X31); + + AArch64.X((int)Rn, new Bits(Xn)); + AArch64.X((int)Rm, new Bits(Xm)); + Base.Ands_Rs(Op[31], Op[23, 22], Op[20, 16], Op[15, 10], Op[9, 5], Op[4, 0]); + ulong Xd = AArch64.X(64, (int)Rd).ToUInt64(); + + if (Rd != 31) + { + Assert.That((ulong)ThreadState.X0, Is.EqualTo(Xd)); + } + else + { + Assert.That((ulong)ThreadState.X31, Is.EqualTo(_X31)); + } + Assert.Multiple(() => + { + Assert.That(ThreadState.Negative, Is.EqualTo(Shared.PSTATE.N)); + Assert.That(ThreadState.Zero, Is.EqualTo(Shared.PSTATE.Z)); + Assert.That(ThreadState.Carry, Is.EqualTo(Shared.PSTATE.C)); + Assert.That(ThreadState.Overflow, Is.EqualTo(Shared.PSTATE.V)); + }); + } + + [Test, Description("ANDS , , {, #}")] + public void Ands_32bit([Values(0u, 31u)] uint Rd, + [Values(1u, 31u)] uint Rn, + [Values(2u, 31u)] uint Rm, + [Values(0x00000000u, 0x7FFFFFFFu, + 0x80000000u, 0xFFFFFFFFu)] [Random(1)] uint Wn, + [Values(0x00000000u, 0x7FFFFFFFu, + 0x80000000u, 0xFFFFFFFFu)] [Random(1)] uint Wm, + [Values(0b00u, 0b01u, 0b10u, 0b11u)] uint shift, // + [Values(0u, 15u, 16u, 31u)] [Random(0u, 31u, 1)] uint amount) + { + uint Opcode = 0x6A000000; // ANDS W0, W0, W0, LSL #0 + Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); + Opcode |= ((shift & 3) << 22) | ((amount & 63) << 10); + Bits Op = new Bits(Opcode); + + uint _W31 = TestContext.CurrentContext.Random.NextUInt(); + AThreadState ThreadState = SingleOpcode(Opcode, X1: Wn, X2: Wm, X31: _W31); + + AArch64.X((int)Rn, new Bits(Wn)); + AArch64.X((int)Rm, new Bits(Wm)); + Base.Ands_Rs(Op[31], Op[23, 22], Op[20, 16], Op[15, 10], Op[9, 5], Op[4, 0]); + uint Wd = AArch64.X(32, (int)Rd).ToUInt32(); + + if (Rd != 31) + { + Assert.That((uint)ThreadState.X0, Is.EqualTo(Wd)); + } + else + { + Assert.That((uint)ThreadState.X31, Is.EqualTo(_W31)); + } + Assert.Multiple(() => + { + Assert.That(ThreadState.Negative, Is.EqualTo(Shared.PSTATE.N)); + Assert.That(ThreadState.Zero, Is.EqualTo(Shared.PSTATE.Z)); + Assert.That(ThreadState.Carry, Is.EqualTo(Shared.PSTATE.C)); + Assert.That(ThreadState.Overflow, Is.EqualTo(Shared.PSTATE.V)); + }); + } + + [Test, Description("ASRV , , ")] + public void Asrv_64bit([Values(0u, 31u)] uint Rd, + [Values(1u, 31u)] uint Rn, + [Values(2u, 31u)] uint Rm, + [Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul, + 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(8)] ulong Xn, + [Values(0ul, 31ul, 32ul, 63ul, 0x7FFFFFFFFFFFFFFFul, + 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(5)] ulong Xm) + { + uint Opcode = 0x9AC02800; // ASRV X0, X0, X0 + Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); + + ulong _X31 = TestContext.CurrentContext.Random.NextULong(); + AThreadState ThreadState = SingleOpcode(Opcode, X1: Xn, X2: Xm, X31: _X31); + + if (Rd != 31) + { + Bits Op = new Bits(Opcode); + + AArch64.X((int)Rn, new Bits(Xn)); + AArch64.X((int)Rm, new Bits(Xm)); + Base.Asrv(Op[31], Op[20, 16], Op[9, 5], Op[4, 0]); + ulong Xd = AArch64.X(64, (int)Rd).ToUInt64(); + + Assert.That((ulong)ThreadState.X0, Is.EqualTo(Xd)); + } + else + { + Assert.That((ulong)ThreadState.X31, Is.EqualTo(_X31)); + } + } + + [Test, Description("ASRV , , ")] + public void Asrv_32bit([Values(0u, 31u)] uint Rd, + [Values(1u, 31u)] uint Rn, + [Values(2u, 31u)] uint Rm, + [Values(0x00000000u, 0x7FFFFFFFu, + 0x80000000u, 0xFFFFFFFFu)] [Random(8)] uint Wn, + [Values(0u, 15u, 16u, 31u, 0x7FFFFFFFu, + 0x80000000u, 0xFFFFFFFFu)] [Random(5)] uint Wm) + { + uint Opcode = 0x1AC02800; // ASRV W0, W0, W0 + Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); + + uint _W31 = TestContext.CurrentContext.Random.NextUInt(); + AThreadState ThreadState = SingleOpcode(Opcode, X1: Wn, X2: Wm, X31: _W31); + + if (Rd != 31) + { + Bits Op = new Bits(Opcode); + + AArch64.X((int)Rn, new Bits(Wn)); + AArch64.X((int)Rm, new Bits(Wm)); + Base.Asrv(Op[31], Op[20, 16], Op[9, 5], Op[4, 0]); + uint Wd = AArch64.X(32, (int)Rd).ToUInt32(); + + Assert.That((uint)ThreadState.X0, Is.EqualTo(Wd)); + } + else + { + Assert.That((uint)ThreadState.X31, Is.EqualTo(_W31)); + } + } + + [Test, Description("BIC , , {, #}")] + public void Bic_64bit([Values(0u, 31u)] uint Rd, + [Values(1u, 31u)] uint Rn, + [Values(2u, 31u)] uint Rm, + [Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul, + 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(1)] ulong Xn, + [Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul, + 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(1)] ulong Xm, + [Values(0b00u, 0b01u, 0b10u, 0b11u)] uint shift, // + [Values(0u, 31u, 32u, 63u)] [Random(0u, 63u, 1)] uint amount) + { + uint Opcode = 0x8A200000; // BIC X0, X0, X0, LSL #0 + Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); + Opcode |= ((shift & 3) << 22) | ((amount & 63) << 10); + + ulong _X31 = TestContext.CurrentContext.Random.NextULong(); + AThreadState ThreadState = SingleOpcode(Opcode, X1: Xn, X2: Xm, X31: _X31); + + if (Rd != 31) + { + Bits Op = new Bits(Opcode); + + AArch64.X((int)Rn, new Bits(Xn)); + AArch64.X((int)Rm, new Bits(Xm)); + Base.Bic(Op[31], Op[23, 22], Op[20, 16], Op[15, 10], Op[9, 5], Op[4, 0]); + ulong Xd = AArch64.X(64, (int)Rd).ToUInt64(); + + Assert.That((ulong)ThreadState.X0, Is.EqualTo(Xd)); + } + else + { + Assert.That((ulong)ThreadState.X31, Is.EqualTo(_X31)); + } + } + + [Test, Description("BIC , , {, #}")] + public void Bic_32bit([Values(0u, 31u)] uint Rd, + [Values(1u, 31u)] uint Rn, + [Values(2u, 31u)] uint Rm, + [Values(0x00000000u, 0x7FFFFFFFu, + 0x80000000u, 0xFFFFFFFFu)] [Random(1)] uint Wn, + [Values(0x00000000u, 0x7FFFFFFFu, + 0x80000000u, 0xFFFFFFFFu)] [Random(1)] uint Wm, + [Values(0b00u, 0b01u, 0b10u, 0b11u)] uint shift, // + [Values(0u, 15u, 16u, 31u)] [Random(0u, 31u, 1)] uint amount) + { + uint Opcode = 0x0A200000; // BIC W0, W0, W0, LSL #0 + Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); + Opcode |= ((shift & 3) << 22) | ((amount & 63) << 10); + + uint _W31 = TestContext.CurrentContext.Random.NextUInt(); + AThreadState ThreadState = SingleOpcode(Opcode, X1: Wn, X2: Wm, X31: _W31); + + if (Rd != 31) + { + Bits Op = new Bits(Opcode); + + AArch64.X((int)Rn, new Bits(Wn)); + AArch64.X((int)Rm, new Bits(Wm)); + Base.Bic(Op[31], Op[23, 22], Op[20, 16], Op[15, 10], Op[9, 5], Op[4, 0]); + uint Wd = AArch64.X(32, (int)Rd).ToUInt32(); + + Assert.That((uint)ThreadState.X0, Is.EqualTo(Wd)); + } + else + { + Assert.That((uint)ThreadState.X31, Is.EqualTo(_W31)); + } + } + + [Test, Description("BICS , , {, #}")] + public void Bics_64bit([Values(0u, 31u)] uint Rd, + [Values(1u, 31u)] uint Rn, + [Values(2u, 31u)] uint Rm, + [Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul, + 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(1)] ulong Xn, + [Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul, + 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(1)] ulong Xm, + [Values(0b00u, 0b01u, 0b10u, 0b11u)] uint shift, // + [Values(0u, 31u, 32u, 63u)] [Random(0u, 63u, 1)] uint amount) + { + uint Opcode = 0xEA200000; // BICS X0, X0, X0, LSL #0 + Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); + Opcode |= ((shift & 3) << 22) | ((amount & 63) << 10); + Bits Op = new Bits(Opcode); + + ulong _X31 = TestContext.CurrentContext.Random.NextULong(); + AThreadState ThreadState = SingleOpcode(Opcode, X1: Xn, X2: Xm, X31: _X31); + + AArch64.X((int)Rn, new Bits(Xn)); + AArch64.X((int)Rm, new Bits(Xm)); + Base.Bics(Op[31], Op[23, 22], Op[20, 16], Op[15, 10], Op[9, 5], Op[4, 0]); + ulong Xd = AArch64.X(64, (int)Rd).ToUInt64(); + + if (Rd != 31) + { + Assert.That((ulong)ThreadState.X0, Is.EqualTo(Xd)); + } + else + { + Assert.That((ulong)ThreadState.X31, Is.EqualTo(_X31)); + } + Assert.Multiple(() => + { + Assert.That(ThreadState.Negative, Is.EqualTo(Shared.PSTATE.N)); + Assert.That(ThreadState.Zero, Is.EqualTo(Shared.PSTATE.Z)); + Assert.That(ThreadState.Carry, Is.EqualTo(Shared.PSTATE.C)); + Assert.That(ThreadState.Overflow, Is.EqualTo(Shared.PSTATE.V)); + }); + } + + [Test, Description("BICS , , {, #}")] + public void Bics_32bit([Values(0u, 31u)] uint Rd, + [Values(1u, 31u)] uint Rn, + [Values(2u, 31u)] uint Rm, + [Values(0x00000000u, 0x7FFFFFFFu, + 0x80000000u, 0xFFFFFFFFu)] [Random(1)] uint Wn, + [Values(0x00000000u, 0x7FFFFFFFu, + 0x80000000u, 0xFFFFFFFFu)] [Random(1)] uint Wm, + [Values(0b00u, 0b01u, 0b10u, 0b11u)] uint shift, // + [Values(0u, 15u, 16u, 31u)] [Random(0u, 31u, 1)] uint amount) + { + uint Opcode = 0x6A200000; // BICS W0, W0, W0, LSL #0 + Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); + Opcode |= ((shift & 3) << 22) | ((amount & 63) << 10); + Bits Op = new Bits(Opcode); + + uint _W31 = TestContext.CurrentContext.Random.NextUInt(); + AThreadState ThreadState = SingleOpcode(Opcode, X1: Wn, X2: Wm, X31: _W31); + + AArch64.X((int)Rn, new Bits(Wn)); + AArch64.X((int)Rm, new Bits(Wm)); + Base.Bics(Op[31], Op[23, 22], Op[20, 16], Op[15, 10], Op[9, 5], Op[4, 0]); + uint Wd = AArch64.X(32, (int)Rd).ToUInt32(); + + if (Rd != 31) + { + Assert.That((uint)ThreadState.X0, Is.EqualTo(Wd)); + } + else + { + Assert.That((uint)ThreadState.X31, Is.EqualTo(_W31)); + } + Assert.Multiple(() => + { + Assert.That(ThreadState.Negative, Is.EqualTo(Shared.PSTATE.N)); + Assert.That(ThreadState.Zero, Is.EqualTo(Shared.PSTATE.Z)); + Assert.That(ThreadState.Carry, Is.EqualTo(Shared.PSTATE.C)); + Assert.That(ThreadState.Overflow, Is.EqualTo(Shared.PSTATE.V)); + }); + } + + [Test, Description("CRC32X , , ")] + public void Crc32x([Values(0u, 31u)] uint Rd, + [Values(1u, 31u)] uint Rn, + [Values(2u, 31u)] uint Rm, + [Values(0x00000000u, 0xFFFFFFFFu)] [Random(2)] uint Wn, + [Values((ulong)0x00_00_00_00_00_00_00_00, + (ulong)0x7F_FF_FF_FF_FF_FF_FF_FF, + (ulong)0x80_00_00_00_00_00_00_00, + (ulong)0xFF_FF_FF_FF_FF_FF_FF_FF)] [Random(64)] ulong Xm) + { + uint Opcode = 0x9AC04C00; // CRC32X W0, W0, X0 + Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); + + uint _W31 = TestContext.CurrentContext.Random.NextUInt(); + AThreadState ThreadState = SingleOpcode(Opcode, X1: Wn, X2: Xm, X31: _W31); + + if (Rd != 31) + { + Bits Op = new Bits(Opcode); + + AArch64.X((int)Rn, new Bits(Wn)); + AArch64.X((int)Rm, new Bits(Xm)); + Base.Crc32(Op[31], Op[20, 16], Op[11, 10], Op[9, 5], Op[4, 0]); + uint Wd = AArch64.X(32, (int)Rd).ToUInt32(); + + Assert.That((uint)ThreadState.X0, Is.EqualTo(Wd)); + } + else + { + Assert.That((uint)ThreadState.X31, Is.EqualTo(_W31)); + } + } + + [Test, Description("CRC32W , , ")] + public void Crc32w([Values(0u, 31u)] uint Rd, + [Values(1u, 31u)] uint Rn, + [Values(2u, 31u)] uint Rm, + [Values(0x00000000u, 0xFFFFFFFFu)] [Random(2)] uint Wn, + [Values((uint)0x00_00_00_00, (uint)0x7F_FF_FF_FF, + (uint)0x80_00_00_00, (uint)0xFF_FF_FF_FF)] [Random(64)] uint Wm) + { + uint Opcode = 0x1AC04800; // CRC32W W0, W0, W0 + Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); + + uint _W31 = TestContext.CurrentContext.Random.NextUInt(); + AThreadState ThreadState = SingleOpcode(Opcode, X1: Wn, X2: Wm, X31: _W31); + + if (Rd != 31) + { + Bits Op = new Bits(Opcode); + + AArch64.X((int)Rn, new Bits(Wn)); + AArch64.X((int)Rm, new Bits(Wm)); + Base.Crc32(Op[31], Op[20, 16], Op[11, 10], Op[9, 5], Op[4, 0]); + uint Wd = AArch64.X(32, (int)Rd).ToUInt32(); + + Assert.That((uint)ThreadState.X0, Is.EqualTo(Wd)); + } + else + { + Assert.That((uint)ThreadState.X31, Is.EqualTo(_W31)); + } + } + + [Test, Description("CRC32H , , ")] + public void Crc32h([Values(0u, 31u)] uint Rd, + [Values(1u, 31u)] uint Rn, + [Values(2u, 31u)] uint Rm, + [Values(0x00000000u, 0xFFFFFFFFu)] [Random(2)] uint Wn, + [Values((ushort)0x00_00, (ushort)0x7F_FF, + (ushort)0x80_00, (ushort)0xFF_FF)] [Random(64)] ushort Wm) + { + uint Opcode = 0x1AC04400; // CRC32H W0, W0, W0 + Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); + + uint _W31 = TestContext.CurrentContext.Random.NextUInt(); + AThreadState ThreadState = SingleOpcode(Opcode, X1: Wn, X2: Wm, X31: _W31); + + if (Rd != 31) + { + Bits Op = new Bits(Opcode); + + AArch64.X((int)Rn, new Bits(Wn)); + AArch64.X((int)Rm, new Bits(Wm)); + Base.Crc32(Op[31], Op[20, 16], Op[11, 10], Op[9, 5], Op[4, 0]); + uint Wd = AArch64.X(32, (int)Rd).ToUInt32(); + + Assert.That((uint)ThreadState.X0, Is.EqualTo(Wd)); + } + else + { + Assert.That((uint)ThreadState.X31, Is.EqualTo(_W31)); + } + } + + [Test, Description("CRC32B , , ")] + public void Crc32b([Values(0u, 31u)] uint Rd, + [Values(1u, 31u)] uint Rn, + [Values(2u, 31u)] uint Rm, + [Values(0x00000000u, 0xFFFFFFFFu)] [Random(2)] uint Wn, + [Values((byte)0x00, (byte)0x7F, + (byte)0x80, (byte)0xFF)] [Random(64)] byte Wm) + { + uint Opcode = 0x1AC04000; // CRC32B W0, W0, W0 + Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); + + uint _W31 = TestContext.CurrentContext.Random.NextUInt(); + AThreadState ThreadState = SingleOpcode(Opcode, X1: Wn, X2: Wm, X31: _W31); + + if (Rd != 31) + { + Bits Op = new Bits(Opcode); + + AArch64.X((int)Rn, new Bits(Wn)); + AArch64.X((int)Rm, new Bits(Wm)); + Base.Crc32(Op[31], Op[20, 16], Op[11, 10], Op[9, 5], Op[4, 0]); + uint Wd = AArch64.X(32, (int)Rd).ToUInt32(); + + Assert.That((uint)ThreadState.X0, Is.EqualTo(Wd)); + } + else + { + Assert.That((uint)ThreadState.X31, Is.EqualTo(_W31)); + } + } + + [Test, Description("CRC32CX , , ")] + public void Crc32cx([Values(0u, 31u)] uint Rd, + [Values(1u, 31u)] uint Rn, + [Values(2u, 31u)] uint Rm, + [Values(0x00000000u, 0xFFFFFFFFu)] [Random(2)] uint Wn, + [Values((ulong)0x00_00_00_00_00_00_00_00, + (ulong)0x7F_FF_FF_FF_FF_FF_FF_FF, + (ulong)0x80_00_00_00_00_00_00_00, + (ulong)0xFF_FF_FF_FF_FF_FF_FF_FF)] [Random(64)] ulong Xm) + { + uint Opcode = 0x9AC05C00; // CRC32CX W0, W0, X0 + Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); + + uint _W31 = TestContext.CurrentContext.Random.NextUInt(); + AThreadState ThreadState = SingleOpcode(Opcode, X1: Wn, X2: Xm, X31: _W31); + + if (Rd != 31) + { + Bits Op = new Bits(Opcode); + + AArch64.X((int)Rn, new Bits(Wn)); + AArch64.X((int)Rm, new Bits(Xm)); + Base.Crc32c(Op[31], Op[20, 16], Op[11, 10], Op[9, 5], Op[4, 0]); + uint Wd = AArch64.X(32, (int)Rd).ToUInt32(); + + Assert.That((uint)ThreadState.X0, Is.EqualTo(Wd)); + } + else + { + Assert.That((uint)ThreadState.X31, Is.EqualTo(_W31)); + } + } + + [Test, Description("CRC32CW , , ")] + public void Crc32cw([Values(0u, 31u)] uint Rd, + [Values(1u, 31u)] uint Rn, + [Values(2u, 31u)] uint Rm, + [Values(0x00000000u, 0xFFFFFFFFu)] [Random(2)] uint Wn, + [Values((uint)0x00_00_00_00, (uint)0x7F_FF_FF_FF, + (uint)0x80_00_00_00, (uint)0xFF_FF_FF_FF)] [Random(64)] uint Wm) + { + uint Opcode = 0x1AC05800; // CRC32CW W0, W0, W0 + Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); + + uint _W31 = TestContext.CurrentContext.Random.NextUInt(); + AThreadState ThreadState = SingleOpcode(Opcode, X1: Wn, X2: Wm, X31: _W31); + + if (Rd != 31) + { + Bits Op = new Bits(Opcode); + + AArch64.X((int)Rn, new Bits(Wn)); + AArch64.X((int)Rm, new Bits(Wm)); + Base.Crc32c(Op[31], Op[20, 16], Op[11, 10], Op[9, 5], Op[4, 0]); + uint Wd = AArch64.X(32, (int)Rd).ToUInt32(); + + Assert.That((uint)ThreadState.X0, Is.EqualTo(Wd)); + } + else + { + Assert.That((uint)ThreadState.X31, Is.EqualTo(_W31)); + } + } + + [Test, Description("CRC32CH , , ")] + public void Crc32ch([Values(0u, 31u)] uint Rd, + [Values(1u, 31u)] uint Rn, + [Values(2u, 31u)] uint Rm, + [Values(0x00000000u, 0xFFFFFFFFu)] [Random(2)] uint Wn, + [Values((ushort)0x00_00, (ushort)0x7F_FF, + (ushort)0x80_00, (ushort)0xFF_FF)] [Random(64)] ushort Wm) + { + uint Opcode = 0x1AC05400; // CRC32CH W0, W0, W0 + Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); + + uint _W31 = TestContext.CurrentContext.Random.NextUInt(); + AThreadState ThreadState = SingleOpcode(Opcode, X1: Wn, X2: Wm, X31: _W31); + + if (Rd != 31) + { + Bits Op = new Bits(Opcode); + + AArch64.X((int)Rn, new Bits(Wn)); + AArch64.X((int)Rm, new Bits(Wm)); + Base.Crc32c(Op[31], Op[20, 16], Op[11, 10], Op[9, 5], Op[4, 0]); + uint Wd = AArch64.X(32, (int)Rd).ToUInt32(); + + Assert.That((uint)ThreadState.X0, Is.EqualTo(Wd)); + } + else + { + Assert.That((uint)ThreadState.X31, Is.EqualTo(_W31)); + } + } + + [Test, Description("CRC32CB , , ")] + public void Crc32cb([Values(0u, 31u)] uint Rd, + [Values(1u, 31u)] uint Rn, + [Values(2u, 31u)] uint Rm, + [Values(0x00000000u, 0xFFFFFFFFu)] [Random(2)] uint Wn, + [Values((byte)0x00, (byte)0x7F, + (byte)0x80, (byte)0xFF)] [Random(64)] byte Wm) + { + uint Opcode = 0x1AC05000; // CRC32CB W0, W0, W0 + Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); + + uint _W31 = TestContext.CurrentContext.Random.NextUInt(); + AThreadState ThreadState = SingleOpcode(Opcode, X1: Wn, X2: Wm, X31: _W31); + + if (Rd != 31) + { + Bits Op = new Bits(Opcode); + + AArch64.X((int)Rn, new Bits(Wn)); + AArch64.X((int)Rm, new Bits(Wm)); + Base.Crc32c(Op[31], Op[20, 16], Op[11, 10], Op[9, 5], Op[4, 0]); + uint Wd = AArch64.X(32, (int)Rd).ToUInt32(); + + Assert.That((uint)ThreadState.X0, Is.EqualTo(Wd)); + } + else + { + Assert.That((uint)ThreadState.X31, Is.EqualTo(_W31)); + } + } + + [Test, Description("EON , , {, #}")] + public void Eon_64bit([Values(0u, 31u)] uint Rd, + [Values(1u, 31u)] uint Rn, + [Values(2u, 31u)] uint Rm, + [Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul, + 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(1)] ulong Xn, + [Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul, + 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(1)] ulong Xm, + [Values(0b00u, 0b01u, 0b10u, 0b11u)] uint shift, // + [Values(0u, 31u, 32u, 63u)] [Random(0u, 63u, 1)] uint amount) + { + uint Opcode = 0xCA200000; // EON X0, X0, X0, LSL #0 + Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); + Opcode |= ((shift & 3) << 22) | ((amount & 63) << 10); + + ulong _X31 = TestContext.CurrentContext.Random.NextULong(); + AThreadState ThreadState = SingleOpcode(Opcode, X1: Xn, X2: Xm, X31: _X31); + + if (Rd != 31) + { + Bits Op = new Bits(Opcode); + + AArch64.X((int)Rn, new Bits(Xn)); + AArch64.X((int)Rm, new Bits(Xm)); + Base.Eon(Op[31], Op[23, 22], Op[20, 16], Op[15, 10], Op[9, 5], Op[4, 0]); + ulong Xd = AArch64.X(64, (int)Rd).ToUInt64(); + + Assert.That((ulong)ThreadState.X0, Is.EqualTo(Xd)); + } + else + { + Assert.That((ulong)ThreadState.X31, Is.EqualTo(_X31)); + } + } + + [Test, Description("EON , , {, #}")] + public void Eon_32bit([Values(0u, 31u)] uint Rd, + [Values(1u, 31u)] uint Rn, + [Values(2u, 31u)] uint Rm, + [Values(0x00000000u, 0x7FFFFFFFu, + 0x80000000u, 0xFFFFFFFFu)] [Random(1)] uint Wn, + [Values(0x00000000u, 0x7FFFFFFFu, + 0x80000000u, 0xFFFFFFFFu)] [Random(1)] uint Wm, + [Values(0b00u, 0b01u, 0b10u, 0b11u)] uint shift, // + [Values(0u, 15u, 16u, 31u)] [Random(0u, 31u, 1)] uint amount) + { + uint Opcode = 0x4A200000; // EON W0, W0, W0, LSL #0 + Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); + Opcode |= ((shift & 3) << 22) | ((amount & 63) << 10); + + uint _W31 = TestContext.CurrentContext.Random.NextUInt(); + AThreadState ThreadState = SingleOpcode(Opcode, X1: Wn, X2: Wm, X31: _W31); + + if (Rd != 31) + { + Bits Op = new Bits(Opcode); + + AArch64.X((int)Rn, new Bits(Wn)); + AArch64.X((int)Rm, new Bits(Wm)); + Base.Eon(Op[31], Op[23, 22], Op[20, 16], Op[15, 10], Op[9, 5], Op[4, 0]); + uint Wd = AArch64.X(32, (int)Rd).ToUInt32(); + + Assert.That((uint)ThreadState.X0, Is.EqualTo(Wd)); + } + else + { + Assert.That((uint)ThreadState.X31, Is.EqualTo(_W31)); + } + } + + [Test, Description("EOR , , {, #}")] + public void Eor_64bit([Values(0u, 31u)] uint Rd, + [Values(1u, 31u)] uint Rn, + [Values(2u, 31u)] uint Rm, + [Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul, + 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(1)] ulong Xn, + [Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul, + 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(1)] ulong Xm, + [Values(0b00u, 0b01u, 0b10u, 0b11u)] uint shift, // + [Values(0u, 31u, 32u, 63u)] [Random(0u, 63u, 1)] uint amount) + { + uint Opcode = 0xCA000000; // EOR X0, X0, X0, LSL #0 + Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); + Opcode |= ((shift & 3) << 22) | ((amount & 63) << 10); + + ulong _X31 = TestContext.CurrentContext.Random.NextULong(); + AThreadState ThreadState = SingleOpcode(Opcode, X1: Xn, X2: Xm, X31: _X31); + + if (Rd != 31) + { + Bits Op = new Bits(Opcode); + + AArch64.X((int)Rn, new Bits(Xn)); + AArch64.X((int)Rm, new Bits(Xm)); + Base.Eor_Rs(Op[31], Op[23, 22], Op[20, 16], Op[15, 10], Op[9, 5], Op[4, 0]); + ulong Xd = AArch64.X(64, (int)Rd).ToUInt64(); + + Assert.That((ulong)ThreadState.X0, Is.EqualTo(Xd)); + } + else + { + Assert.That((ulong)ThreadState.X31, Is.EqualTo(_X31)); + } + } + + [Test, Description("EOR , , {, #}")] + public void Eor_32bit([Values(0u, 31u)] uint Rd, + [Values(1u, 31u)] uint Rn, + [Values(2u, 31u)] uint Rm, + [Values(0x00000000u, 0x7FFFFFFFu, + 0x80000000u, 0xFFFFFFFFu)] [Random(1)] uint Wn, + [Values(0x00000000u, 0x7FFFFFFFu, + 0x80000000u, 0xFFFFFFFFu)] [Random(1)] uint Wm, + [Values(0b00u, 0b01u, 0b10u, 0b11u)] uint shift, // + [Values(0u, 15u, 16u, 31u)] [Random(0u, 31u, 1)] uint amount) + { + uint Opcode = 0x4A000000; // EOR W0, W0, W0, LSL #0 + Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); + Opcode |= ((shift & 3) << 22) | ((amount & 63) << 10); + + uint _W31 = TestContext.CurrentContext.Random.NextUInt(); + AThreadState ThreadState = SingleOpcode(Opcode, X1: Wn, X2: Wm, X31: _W31); + + if (Rd != 31) + { + Bits Op = new Bits(Opcode); + + AArch64.X((int)Rn, new Bits(Wn)); + AArch64.X((int)Rm, new Bits(Wm)); + Base.Eor_Rs(Op[31], Op[23, 22], Op[20, 16], Op[15, 10], Op[9, 5], Op[4, 0]); + uint Wd = AArch64.X(32, (int)Rd).ToUInt32(); + + Assert.That((uint)ThreadState.X0, Is.EqualTo(Wd)); + } + else + { + Assert.That((uint)ThreadState.X31, Is.EqualTo(_W31)); + } + } + + [Test, Description("EXTR , , , #")] + public void Extr_64bit([Values(0u, 31u)] uint Rd, + [Values(1u, 31u)] uint Rn, + [Values(2u, 31u)] uint Rm, + [Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul, + 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(2)] ulong Xn, + [Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul, + 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(2)] ulong Xm, + [Values(0u, 31u, 32u, 63u)] [Random(0u, 63u, 2)] uint lsb) + { + uint Opcode = 0x93C00000; // EXTR X0, X0, X0, #0 + Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); + Opcode |= ((lsb & 63) << 10); + + ulong _X31 = TestContext.CurrentContext.Random.NextULong(); + AThreadState ThreadState = SingleOpcode(Opcode, X1: Xn, X2: Xm, X31: _X31); + + if (Rd != 31) + { + Bits Op = new Bits(Opcode); + + AArch64.X((int)Rn, new Bits(Xn)); + AArch64.X((int)Rm, new Bits(Xm)); + Base.Extr(Op[31], Op[22], Op[20, 16], Op[15, 10], Op[9, 5], Op[4, 0]); + ulong Xd = AArch64.X(64, (int)Rd).ToUInt64(); + + Assert.That((ulong)ThreadState.X0, Is.EqualTo(Xd)); + } + else + { + Assert.That((ulong)ThreadState.X31, Is.EqualTo(_X31)); + } + } + + [Test, Description("EXTR , , , #")] + public void Extr_32bit([Values(0u, 31u)] uint Rd, + [Values(1u, 31u)] uint Rn, + [Values(2u, 31u)] uint Rm, + [Values(0x00000000u, 0x7FFFFFFFu, + 0x80000000u, 0xFFFFFFFFu)] [Random(2)] uint Wn, + [Values(0x00000000u, 0x7FFFFFFFu, + 0x80000000u, 0xFFFFFFFFu)] [Random(2)] uint Wm, + [Values(0u, 15u, 16u, 31u)] [Random(0u, 31u, 2)] uint lsb) + { + uint Opcode = 0x13800000; // EXTR W0, W0, W0, #0 + Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); + Opcode |= ((lsb & 63) << 10); + + uint _W31 = TestContext.CurrentContext.Random.NextUInt(); + AThreadState ThreadState = SingleOpcode(Opcode, X1: Wn, X2: Wm, X31: _W31); + + if (Rd != 31) + { + Bits Op = new Bits(Opcode); + + AArch64.X((int)Rn, new Bits(Wn)); + AArch64.X((int)Rm, new Bits(Wm)); + Base.Extr(Op[31], Op[22], Op[20, 16], Op[15, 10], Op[9, 5], Op[4, 0]); + uint Wd = AArch64.X(32, (int)Rd).ToUInt32(); + + Assert.That((uint)ThreadState.X0, Is.EqualTo(Wd)); + } + else + { + Assert.That((uint)ThreadState.X31, Is.EqualTo(_W31)); + } + } + + [Test, Description("LSLV , , ")] + public void Lslv_64bit([Values(0u, 31u)] uint Rd, + [Values(1u, 31u)] uint Rn, + [Values(2u, 31u)] uint Rm, + [Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul, + 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(8)] ulong Xn, + [Values(0ul, 31ul, 32ul, 63ul, 0x7FFFFFFFFFFFFFFFul, + 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(5)] ulong Xm) + { + uint Opcode = 0x9AC02000; // LSLV X0, X0, X0 + Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); + + ulong _X31 = TestContext.CurrentContext.Random.NextULong(); + AThreadState ThreadState = SingleOpcode(Opcode, X1: Xn, X2: Xm, X31: _X31); + + if (Rd != 31) + { + Bits Op = new Bits(Opcode); + + AArch64.X((int)Rn, new Bits(Xn)); + AArch64.X((int)Rm, new Bits(Xm)); + Base.Lslv(Op[31], Op[20, 16], Op[9, 5], Op[4, 0]); + ulong Xd = AArch64.X(64, (int)Rd).ToUInt64(); + + Assert.That((ulong)ThreadState.X0, Is.EqualTo(Xd)); + } + else + { + Assert.That((ulong)ThreadState.X31, Is.EqualTo(_X31)); + } + } + + [Test, Description("LSLV , , ")] + public void Lslv_32bit([Values(0u, 31u)] uint Rd, + [Values(1u, 31u)] uint Rn, + [Values(2u, 31u)] uint Rm, + [Values(0x00000000u, 0x7FFFFFFFu, + 0x80000000u, 0xFFFFFFFFu)] [Random(8)] uint Wn, + [Values(0u, 15u, 16u, 31u, 0x7FFFFFFFu, + 0x80000000u, 0xFFFFFFFFu)] [Random(5)] uint Wm) + { + uint Opcode = 0x1AC02000; // LSLV W0, W0, W0 + Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); + + uint _W31 = TestContext.CurrentContext.Random.NextUInt(); + AThreadState ThreadState = SingleOpcode(Opcode, X1: Wn, X2: Wm, X31: _W31); + + if (Rd != 31) + { + Bits Op = new Bits(Opcode); + + AArch64.X((int)Rn, new Bits(Wn)); + AArch64.X((int)Rm, new Bits(Wm)); + Base.Lslv(Op[31], Op[20, 16], Op[9, 5], Op[4, 0]); + uint Wd = AArch64.X(32, (int)Rd).ToUInt32(); + + Assert.That((uint)ThreadState.X0, Is.EqualTo(Wd)); + } + else + { + Assert.That((uint)ThreadState.X31, Is.EqualTo(_W31)); + } + } + + [Test, Description("LSRV , , ")] + public void Lsrv_64bit([Values(0u, 31u)] uint Rd, + [Values(1u, 31u)] uint Rn, + [Values(2u, 31u)] uint Rm, + [Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul, + 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(8)] ulong Xn, + [Values(0ul, 31ul, 32ul, 63ul, 0x7FFFFFFFFFFFFFFFul, + 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(5)] ulong Xm) + { + uint Opcode = 0x9AC02400; // LSRV X0, X0, X0 + Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); + + ulong _X31 = TestContext.CurrentContext.Random.NextULong(); + AThreadState ThreadState = SingleOpcode(Opcode, X1: Xn, X2: Xm, X31: _X31); + + if (Rd != 31) + { + Bits Op = new Bits(Opcode); + + AArch64.X((int)Rn, new Bits(Xn)); + AArch64.X((int)Rm, new Bits(Xm)); + Base.Lsrv(Op[31], Op[20, 16], Op[9, 5], Op[4, 0]); + ulong Xd = AArch64.X(64, (int)Rd).ToUInt64(); + + Assert.That((ulong)ThreadState.X0, Is.EqualTo(Xd)); + } + else + { + Assert.That((ulong)ThreadState.X31, Is.EqualTo(_X31)); + } + } + + [Test, Description("LSRV , , ")] + public void Lsrv_32bit([Values(0u, 31u)] uint Rd, + [Values(1u, 31u)] uint Rn, + [Values(2u, 31u)] uint Rm, + [Values(0x00000000u, 0x7FFFFFFFu, + 0x80000000u, 0xFFFFFFFFu)] [Random(8)] uint Wn, + [Values(0u, 15u, 16u, 31u, 0x7FFFFFFFu, + 0x80000000u, 0xFFFFFFFFu)] [Random(5)] uint Wm) + { + uint Opcode = 0x1AC02400; // LSRV W0, W0, W0 + Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); + + uint _W31 = TestContext.CurrentContext.Random.NextUInt(); + AThreadState ThreadState = SingleOpcode(Opcode, X1: Wn, X2: Wm, X31: _W31); + + if (Rd != 31) + { + Bits Op = new Bits(Opcode); + + AArch64.X((int)Rn, new Bits(Wn)); + AArch64.X((int)Rm, new Bits(Wm)); + Base.Lsrv(Op[31], Op[20, 16], Op[9, 5], Op[4, 0]); + uint Wd = AArch64.X(32, (int)Rd).ToUInt32(); + + Assert.That((uint)ThreadState.X0, Is.EqualTo(Wd)); + } + else + { + Assert.That((uint)ThreadState.X31, Is.EqualTo(_W31)); + } + } + + [Test, Description("ORN , , {, #}")] + public void Orn_64bit([Values(0u, 31u)] uint Rd, + [Values(1u, 31u)] uint Rn, + [Values(2u, 31u)] uint Rm, + [Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul, + 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(1)] ulong Xn, + [Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul, + 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(1)] ulong Xm, + [Values(0b00u, 0b01u, 0b10u, 0b11u)] uint shift, // + [Values(0u, 31u, 32u, 63u)] [Random(0u, 63u, 1)] uint amount) + { + uint Opcode = 0xAA200000; // ORN X0, X0, X0, LSL #0 + Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); + Opcode |= ((shift & 3) << 22) | ((amount & 63) << 10); + + ulong _X31 = TestContext.CurrentContext.Random.NextULong(); + AThreadState ThreadState = SingleOpcode(Opcode, X1: Xn, X2: Xm, X31: _X31); + + if (Rd != 31) + { + Bits Op = new Bits(Opcode); + + AArch64.X((int)Rn, new Bits(Xn)); + AArch64.X((int)Rm, new Bits(Xm)); + Base.Orn(Op[31], Op[23, 22], Op[20, 16], Op[15, 10], Op[9, 5], Op[4, 0]); + ulong Xd = AArch64.X(64, (int)Rd).ToUInt64(); + + Assert.That((ulong)ThreadState.X0, Is.EqualTo(Xd)); + } + else + { + Assert.That((ulong)ThreadState.X31, Is.EqualTo(_X31)); + } + } + + [Test, Description("ORN , , {, #}")] + public void Orn_32bit([Values(0u, 31u)] uint Rd, + [Values(1u, 31u)] uint Rn, + [Values(2u, 31u)] uint Rm, + [Values(0x00000000u, 0x7FFFFFFFu, + 0x80000000u, 0xFFFFFFFFu)] [Random(1)] uint Wn, + [Values(0x00000000u, 0x7FFFFFFFu, + 0x80000000u, 0xFFFFFFFFu)] [Random(1)] uint Wm, + [Values(0b00u, 0b01u, 0b10u, 0b11u)] uint shift, // + [Values(0u, 15u, 16u, 31u)] [Random(0u, 31u, 1)] uint amount) + { + uint Opcode = 0x2A200000; // ORN W0, W0, W0, LSL #0 + Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); + Opcode |= ((shift & 3) << 22) | ((amount & 63) << 10); + + uint _W31 = TestContext.CurrentContext.Random.NextUInt(); + AThreadState ThreadState = SingleOpcode(Opcode, X1: Wn, X2: Wm, X31: _W31); + + if (Rd != 31) + { + Bits Op = new Bits(Opcode); + + AArch64.X((int)Rn, new Bits(Wn)); + AArch64.X((int)Rm, new Bits(Wm)); + Base.Orn(Op[31], Op[23, 22], Op[20, 16], Op[15, 10], Op[9, 5], Op[4, 0]); + uint Wd = AArch64.X(32, (int)Rd).ToUInt32(); + + Assert.That((uint)ThreadState.X0, Is.EqualTo(Wd)); + } + else + { + Assert.That((uint)ThreadState.X31, Is.EqualTo(_W31)); + } + } + + [Test, Description("ORR , , {, #}")] + public void Orr_64bit([Values(0u, 31u)] uint Rd, + [Values(1u, 31u)] uint Rn, + [Values(2u, 31u)] uint Rm, + [Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul, + 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(1)] ulong Xn, + [Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul, + 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(1)] ulong Xm, + [Values(0b00u, 0b01u, 0b10u, 0b11u)] uint shift, // + [Values(0u, 31u, 32u, 63u)] [Random(0u, 63u, 1)] uint amount) + { + uint Opcode = 0xAA000000; // ORR X0, X0, X0, LSL #0 + Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); + Opcode |= ((shift & 3) << 22) | ((amount & 63) << 10); + + ulong _X31 = TestContext.CurrentContext.Random.NextULong(); + AThreadState ThreadState = SingleOpcode(Opcode, X1: Xn, X2: Xm, X31: _X31); + + if (Rd != 31) + { + Bits Op = new Bits(Opcode); + + AArch64.X((int)Rn, new Bits(Xn)); + AArch64.X((int)Rm, new Bits(Xm)); + Base.Orr_Rs(Op[31], Op[23, 22], Op[20, 16], Op[15, 10], Op[9, 5], Op[4, 0]); + ulong Xd = AArch64.X(64, (int)Rd).ToUInt64(); + + Assert.That((ulong)ThreadState.X0, Is.EqualTo(Xd)); + } + else + { + Assert.That((ulong)ThreadState.X31, Is.EqualTo(_X31)); + } + } + + [Test, Description("ORR , , {, #}")] + public void Orr_32bit([Values(0u, 31u)] uint Rd, + [Values(1u, 31u)] uint Rn, + [Values(2u, 31u)] uint Rm, + [Values(0x00000000u, 0x7FFFFFFFu, + 0x80000000u, 0xFFFFFFFFu)] [Random(1)] uint Wn, + [Values(0x00000000u, 0x7FFFFFFFu, + 0x80000000u, 0xFFFFFFFFu)] [Random(1)] uint Wm, + [Values(0b00u, 0b01u, 0b10u, 0b11u)] uint shift, // + [Values(0u, 15u, 16u, 31u)] [Random(0u, 31u, 1)] uint amount) + { + uint Opcode = 0x2A000000; // ORR W0, W0, W0, LSL #0 + Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); + Opcode |= ((shift & 3) << 22) | ((amount & 63) << 10); + + uint _W31 = TestContext.CurrentContext.Random.NextUInt(); + AThreadState ThreadState = SingleOpcode(Opcode, X1: Wn, X2: Wm, X31: _W31); + + if (Rd != 31) + { + Bits Op = new Bits(Opcode); + + AArch64.X((int)Rn, new Bits(Wn)); + AArch64.X((int)Rm, new Bits(Wm)); + Base.Orr_Rs(Op[31], Op[23, 22], Op[20, 16], Op[15, 10], Op[9, 5], Op[4, 0]); + uint Wd = AArch64.X(32, (int)Rd).ToUInt32(); + + Assert.That((uint)ThreadState.X0, Is.EqualTo(Wd)); + } + else + { + Assert.That((uint)ThreadState.X31, Is.EqualTo(_W31)); + } + } + + [Test, Description("RORV , , ")] + public void Rorv_64bit([Values(0u, 31u)] uint Rd, + [Values(1u, 31u)] uint Rn, + [Values(2u, 31u)] uint Rm, + [Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul, + 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(8)] ulong Xn, + [Values(0ul, 31ul, 32ul, 63ul, 0x7FFFFFFFFFFFFFFFul, + 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(5)] ulong Xm) + { + uint Opcode = 0x9AC02C00; // RORV X0, X0, X0 + Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); + + ulong _X31 = TestContext.CurrentContext.Random.NextULong(); + AThreadState ThreadState = SingleOpcode(Opcode, X1: Xn, X2: Xm, X31: _X31); + + if (Rd != 31) + { + Bits Op = new Bits(Opcode); + + AArch64.X((int)Rn, new Bits(Xn)); + AArch64.X((int)Rm, new Bits(Xm)); + Base.Rorv(Op[31], Op[20, 16], Op[9, 5], Op[4, 0]); + ulong Xd = AArch64.X(64, (int)Rd).ToUInt64(); + + Assert.That((ulong)ThreadState.X0, Is.EqualTo(Xd)); + } + else + { + Assert.That((ulong)ThreadState.X31, Is.EqualTo(_X31)); + } + } + + [Test, Description("RORV , , ")] + public void Rorv_32bit([Values(0u, 31u)] uint Rd, + [Values(1u, 31u)] uint Rn, + [Values(2u, 31u)] uint Rm, + [Values(0x00000000u, 0x7FFFFFFFu, + 0x80000000u, 0xFFFFFFFFu)] [Random(8)] uint Wn, + [Values(0u, 15u, 16u, 31u, 0x7FFFFFFFu, + 0x80000000u, 0xFFFFFFFFu)] [Random(5)] uint Wm) + { + uint Opcode = 0x1AC02C00; // RORV W0, W0, W0 + Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); + + uint _W31 = TestContext.CurrentContext.Random.NextUInt(); + AThreadState ThreadState = SingleOpcode(Opcode, X1: Wn, X2: Wm, X31: _W31); + + if (Rd != 31) + { + Bits Op = new Bits(Opcode); + + AArch64.X((int)Rn, new Bits(Wn)); + AArch64.X((int)Rm, new Bits(Wm)); + Base.Rorv(Op[31], Op[20, 16], Op[9, 5], Op[4, 0]); + uint Wd = AArch64.X(32, (int)Rd).ToUInt32(); + + Assert.That((uint)ThreadState.X0, Is.EqualTo(Wd)); + } + else + { + Assert.That((uint)ThreadState.X31, Is.EqualTo(_W31)); + } + } + + [Test, Description("SBC , , ")] + public void Sbc_64bit([Values(0u, 31u)] uint Rd, + [Values(1u, 31u)] uint Rn, + [Values(2u, 31u)] uint Rm, + [Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul, + 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(4)] ulong Xn, + [Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul, + 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(4)] ulong Xm, + [Values] bool CarryIn) + { + uint Opcode = 0xDA000000; // SBC X0, X0, X0 + Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); + + ulong _X31 = TestContext.CurrentContext.Random.NextULong(); + AThreadState ThreadState = SingleOpcode(Opcode, X1: Xn, X2: Xm, X31: _X31, Carry: CarryIn); + + if (Rd != 31) + { + Bits Op = new Bits(Opcode); + + AArch64.X((int)Rn, new Bits(Xn)); + AArch64.X((int)Rm, new Bits(Xm)); + Shared.PSTATE.C = CarryIn; + Base.Sbc(Op[31], Op[20, 16], Op[9, 5], Op[4, 0]); + ulong Xd = AArch64.X(64, (int)Rd).ToUInt64(); + + Assert.That((ulong)ThreadState.X0, Is.EqualTo(Xd)); + } + else + { + Assert.That((ulong)ThreadState.X31, Is.EqualTo(_X31)); + } + } + + [Test, Description("SBC , , ")] + public void Sbc_32bit([Values(0u, 31u)] uint Rd, + [Values(1u, 31u)] uint Rn, + [Values(2u, 31u)] uint Rm, + [Values(0x00000000u, 0x7FFFFFFFu, + 0x80000000u, 0xFFFFFFFFu)] [Random(4)] uint Wn, + [Values(0x00000000u, 0x7FFFFFFFu, + 0x80000000u, 0xFFFFFFFFu)] [Random(4)] uint Wm, + [Values] bool CarryIn) + { + uint Opcode = 0x5A000000; // SBC W0, W0, W0 + Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); + + uint _W31 = TestContext.CurrentContext.Random.NextUInt(); + AThreadState ThreadState = SingleOpcode(Opcode, X1: Wn, X2: Wm, X31: _W31, Carry: CarryIn); + + if (Rd != 31) + { + Bits Op = new Bits(Opcode); + + AArch64.X((int)Rn, new Bits(Wn)); + AArch64.X((int)Rm, new Bits(Wm)); + Shared.PSTATE.C = CarryIn; + Base.Sbc(Op[31], Op[20, 16], Op[9, 5], Op[4, 0]); + uint Wd = AArch64.X(32, (int)Rd).ToUInt32(); + + Assert.That((uint)ThreadState.X0, Is.EqualTo(Wd)); + } + else + { + Assert.That((uint)ThreadState.X31, Is.EqualTo(_W31)); + } + } + + [Test, Description("SBCS , , ")] + public void Sbcs_64bit([Values(0u, 31u)] uint Rd, + [Values(1u, 31u)] uint Rn, + [Values(2u, 31u)] uint Rm, + [Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul, + 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(4)] ulong Xn, + [Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul, + 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(4)] ulong Xm, + [Values] bool CarryIn) + { + uint Opcode = 0xFA000000; // SBCS X0, X0, X0 + Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); + Bits Op = new Bits(Opcode); + + ulong _X31 = TestContext.CurrentContext.Random.NextULong(); + AThreadState ThreadState = SingleOpcode(Opcode, X1: Xn, X2: Xm, X31: _X31, Carry: CarryIn); + + AArch64.X((int)Rn, new Bits(Xn)); + AArch64.X((int)Rm, new Bits(Xm)); + Shared.PSTATE.C = CarryIn; + Base.Sbcs(Op[31], Op[20, 16], Op[9, 5], Op[4, 0]); + ulong Xd = AArch64.X(64, (int)Rd).ToUInt64(); + + if (Rd != 31) + { + Assert.That((ulong)ThreadState.X0, Is.EqualTo(Xd)); + } + else + { + Assert.That((ulong)ThreadState.X31, Is.EqualTo(_X31)); + } + Assert.Multiple(() => + { + Assert.That(ThreadState.Negative, Is.EqualTo(Shared.PSTATE.N)); + Assert.That(ThreadState.Zero, Is.EqualTo(Shared.PSTATE.Z)); + Assert.That(ThreadState.Carry, Is.EqualTo(Shared.PSTATE.C)); + Assert.That(ThreadState.Overflow, Is.EqualTo(Shared.PSTATE.V)); + }); + } + + [Test, Description("SBCS , , ")] + public void Sbcs_32bit([Values(0u, 31u)] uint Rd, + [Values(1u, 31u)] uint Rn, + [Values(2u, 31u)] uint Rm, + [Values(0x00000000u, 0x7FFFFFFFu, + 0x80000000u, 0xFFFFFFFFu)] [Random(4)] uint Wn, + [Values(0x00000000u, 0x7FFFFFFFu, + 0x80000000u, 0xFFFFFFFFu)] [Random(4)] uint Wm, + [Values] bool CarryIn) + { + uint Opcode = 0x7A000000; // SBCS W0, W0, W0 + Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); + Bits Op = new Bits(Opcode); + + uint _W31 = TestContext.CurrentContext.Random.NextUInt(); + AThreadState ThreadState = SingleOpcode(Opcode, X1: Wn, X2: Wm, X31: _W31, Carry: CarryIn); + + AArch64.X((int)Rn, new Bits(Wn)); + AArch64.X((int)Rm, new Bits(Wm)); + Shared.PSTATE.C = CarryIn; + Base.Sbcs(Op[31], Op[20, 16], Op[9, 5], Op[4, 0]); + uint Wd = AArch64.X(32, (int)Rd).ToUInt32(); + + if (Rd != 31) + { + Assert.That((uint)ThreadState.X0, Is.EqualTo(Wd)); + } + else + { + Assert.That((uint)ThreadState.X31, Is.EqualTo(_W31)); + } + Assert.Multiple(() => + { + Assert.That(ThreadState.Negative, Is.EqualTo(Shared.PSTATE.N)); + Assert.That(ThreadState.Zero, Is.EqualTo(Shared.PSTATE.Z)); + Assert.That(ThreadState.Carry, Is.EqualTo(Shared.PSTATE.C)); + Assert.That(ThreadState.Overflow, Is.EqualTo(Shared.PSTATE.V)); + }); + } + + [Test, Description("SDIV , , ")] + public void Sdiv_64bit([Values(0u, 31u)] uint Rd, + [Values(1u, 31u)] uint Rn, + [Values(2u, 31u)] uint Rm, + [Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul, + 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(8)] ulong Xn, + [Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul, + 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(8)] ulong Xm) + { + uint Opcode = 0x9AC00C00; // SDIV X0, X0, X0 + Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); + + ulong _X31 = TestContext.CurrentContext.Random.NextULong(); + AThreadState ThreadState = SingleOpcode(Opcode, X1: Xn, X2: Xm, X31: _X31); + + if (Rd != 31) + { + Bits Op = new Bits(Opcode); + + AArch64.X((int)Rn, new Bits(Xn)); + AArch64.X((int)Rm, new Bits(Xm)); + Base.Sdiv(Op[31], Op[20, 16], Op[9, 5], Op[4, 0]); + ulong Xd = AArch64.X(64, (int)Rd).ToUInt64(); + + Assert.That((ulong)ThreadState.X0, Is.EqualTo(Xd)); + } + else + { + Assert.That((ulong)ThreadState.X31, Is.EqualTo(_X31)); + } + } + + [Test, Description("SDIV , , ")] + public void Sdiv_32bit([Values(0u, 31u)] uint Rd, + [Values(1u, 31u)] uint Rn, + [Values(2u, 31u)] uint Rm, + [Values(0x00000000u, 0x7FFFFFFFu, + 0x80000000u, 0xFFFFFFFFu)] [Random(8)] uint Wn, + [Values(0x00000000u, 0x7FFFFFFFu, + 0x80000000u, 0xFFFFFFFFu)] [Random(8)] uint Wm) + { + uint Opcode = 0x1AC00C00; // SDIV W0, W0, W0 + Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); + + uint _W31 = TestContext.CurrentContext.Random.NextUInt(); + AThreadState ThreadState = SingleOpcode(Opcode, X1: Wn, X2: Wm, X31: _W31); + + if (Rd != 31) + { + Bits Op = new Bits(Opcode); + + AArch64.X((int)Rn, new Bits(Wn)); + AArch64.X((int)Rm, new Bits(Wm)); + Base.Sdiv(Op[31], Op[20, 16], Op[9, 5], Op[4, 0]); + uint Wd = AArch64.X(32, (int)Rd).ToUInt32(); + + Assert.That((uint)ThreadState.X0, Is.EqualTo(Wd)); + } + else + { + Assert.That((uint)ThreadState.X31, Is.EqualTo(_W31)); + } + } + + [Test, Description("SUB , , {, #}")] + public void Sub_64bit([Values(0u, 31u)] uint Rd, + [Values(1u, 31u)] uint Rn, + [Values(2u, 31u)] uint Rm, + [Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul, + 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(1)] ulong Xn, + [Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul, + 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(1)] ulong Xm, + [Values(0b00u, 0b01u, 0b10u)] uint shift, // + [Values(0u, 31u, 32u, 63u)] [Random(0u, 63u, 1)] uint amount) + { + uint Opcode = 0xCB000000; // SUB X0, X0, X0, LSL #0 + Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); + Opcode |= ((shift & 3) << 22) | ((amount & 63) << 10); + + ulong _X31 = TestContext.CurrentContext.Random.NextULong(); + AThreadState ThreadState = SingleOpcode(Opcode, X1: Xn, X2: Xm, X31: _X31); + + if (Rd != 31) + { + Bits Op = new Bits(Opcode); + + AArch64.X((int)Rn, new Bits(Xn)); + AArch64.X((int)Rm, new Bits(Xm)); + Base.Sub_Rs(Op[31], Op[23, 22], Op[20, 16], Op[15, 10], Op[9, 5], Op[4, 0]); + ulong Xd = AArch64.X(64, (int)Rd).ToUInt64(); + + Assert.That((ulong)ThreadState.X0, Is.EqualTo(Xd)); + } + else + { + Assert.That((ulong)ThreadState.X31, Is.EqualTo(_X31)); + } + } + + [Test, Description("SUB , , {, #}")] + public void Sub_32bit([Values(0u, 31u)] uint Rd, + [Values(1u, 31u)] uint Rn, + [Values(2u, 31u)] uint Rm, + [Values(0x00000000u, 0x7FFFFFFFu, + 0x80000000u, 0xFFFFFFFFu)] [Random(1)] uint Wn, + [Values(0x00000000u, 0x7FFFFFFFu, + 0x80000000u, 0xFFFFFFFFu)] [Random(1)] uint Wm, + [Values(0b00u, 0b01u, 0b10u)] uint shift, // + [Values(0u, 15u, 16u, 31u)] [Random(0u, 31u, 1)] uint amount) + { + uint Opcode = 0x4B000000; // SUB W0, W0, W0, LSL #0 + Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); + Opcode |= ((shift & 3) << 22) | ((amount & 63) << 10); + + uint _W31 = TestContext.CurrentContext.Random.NextUInt(); + AThreadState ThreadState = SingleOpcode(Opcode, X1: Wn, X2: Wm, X31: _W31); + + if (Rd != 31) + { + Bits Op = new Bits(Opcode); + + AArch64.X((int)Rn, new Bits(Wn)); + AArch64.X((int)Rm, new Bits(Wm)); + Base.Sub_Rs(Op[31], Op[23, 22], Op[20, 16], Op[15, 10], Op[9, 5], Op[4, 0]); + uint Wd = AArch64.X(32, (int)Rd).ToUInt32(); + + Assert.That((uint)ThreadState.X0, Is.EqualTo(Wd)); + } + else + { + Assert.That((uint)ThreadState.X31, Is.EqualTo(_W31)); + } + } + + [Test, Description("SUBS , , {, #}")] + public void Subs_64bit([Values(0u, 31u)] uint Rd, + [Values(1u, 31u)] uint Rn, + [Values(2u, 31u)] uint Rm, + [Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul, + 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(1)] ulong Xn, + [Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul, + 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(1)] ulong Xm, + [Values(0b00u, 0b01u, 0b10u)] uint shift, // + [Values(0u, 31u, 32u, 63u)] [Random(0u, 63u, 1)] uint amount) + { + uint Opcode = 0xEB000000; // SUBS X0, X0, X0, LSL #0 + Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); + Opcode |= ((shift & 3) << 22) | ((amount & 63) << 10); + Bits Op = new Bits(Opcode); + + ulong _X31 = TestContext.CurrentContext.Random.NextULong(); + AThreadState ThreadState = SingleOpcode(Opcode, X1: Xn, X2: Xm, X31: _X31); + + AArch64.X((int)Rn, new Bits(Xn)); + AArch64.X((int)Rm, new Bits(Xm)); + Base.Subs_Rs(Op[31], Op[23, 22], Op[20, 16], Op[15, 10], Op[9, 5], Op[4, 0]); + ulong Xd = AArch64.X(64, (int)Rd).ToUInt64(); + + if (Rd != 31) + { + Assert.That((ulong)ThreadState.X0, Is.EqualTo(Xd)); + } + else + { + Assert.That((ulong)ThreadState.X31, Is.EqualTo(_X31)); + } + Assert.Multiple(() => + { + Assert.That(ThreadState.Negative, Is.EqualTo(Shared.PSTATE.N)); + Assert.That(ThreadState.Zero, Is.EqualTo(Shared.PSTATE.Z)); + Assert.That(ThreadState.Carry, Is.EqualTo(Shared.PSTATE.C)); + Assert.That(ThreadState.Overflow, Is.EqualTo(Shared.PSTATE.V)); + }); + } + + [Test, Description("SUBS , , {, #}")] + public void Subs_32bit([Values(0u, 31u)] uint Rd, + [Values(1u, 31u)] uint Rn, + [Values(2u, 31u)] uint Rm, + [Values(0x00000000u, 0x7FFFFFFFu, + 0x80000000u, 0xFFFFFFFFu)] [Random(1)] uint Wn, + [Values(0x00000000u, 0x7FFFFFFFu, + 0x80000000u, 0xFFFFFFFFu)] [Random(1)] uint Wm, + [Values(0b00u, 0b01u, 0b10u)] uint shift, // + [Values(0u, 15u, 16u, 31u)] [Random(0u, 31u, 1)] uint amount) + { + uint Opcode = 0x6B000000; // SUBS W0, W0, W0, LSL #0 + Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); + Opcode |= ((shift & 3) << 22) | ((amount & 63) << 10); + Bits Op = new Bits(Opcode); + + uint _W31 = TestContext.CurrentContext.Random.NextUInt(); + AThreadState ThreadState = SingleOpcode(Opcode, X1: Wn, X2: Wm, X31: _W31); + + AArch64.X((int)Rn, new Bits(Wn)); + AArch64.X((int)Rm, new Bits(Wm)); + Base.Subs_Rs(Op[31], Op[23, 22], Op[20, 16], Op[15, 10], Op[9, 5], Op[4, 0]); + uint Wd = AArch64.X(32, (int)Rd).ToUInt32(); + + if (Rd != 31) + { + Assert.That((uint)ThreadState.X0, Is.EqualTo(Wd)); + } + else + { + Assert.That((uint)ThreadState.X31, Is.EqualTo(_W31)); + } + Assert.Multiple(() => + { + Assert.That(ThreadState.Negative, Is.EqualTo(Shared.PSTATE.N)); + Assert.That(ThreadState.Zero, Is.EqualTo(Shared.PSTATE.Z)); + Assert.That(ThreadState.Carry, Is.EqualTo(Shared.PSTATE.C)); + Assert.That(ThreadState.Overflow, Is.EqualTo(Shared.PSTATE.V)); + }); + } + + [Test, Description("UDIV , , ")] + public void Udiv_64bit([Values(0u, 31u)] uint Rd, + [Values(1u, 31u)] uint Rn, + [Values(2u, 31u)] uint Rm, + [Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul, + 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(8)] ulong Xn, + [Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul, + 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(8)] ulong Xm) + { + uint Opcode = 0x9AC00800; // UDIV X0, X0, X0 + Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); + + ulong _X31 = TestContext.CurrentContext.Random.NextULong(); + AThreadState ThreadState = SingleOpcode(Opcode, X1: Xn, X2: Xm, X31: _X31); + + if (Rd != 31) + { + Bits Op = new Bits(Opcode); + + AArch64.X((int)Rn, new Bits(Xn)); + AArch64.X((int)Rm, new Bits(Xm)); + Base.Udiv(Op[31], Op[20, 16], Op[9, 5], Op[4, 0]); + ulong Xd = AArch64.X(64, (int)Rd).ToUInt64(); + + Assert.That((ulong)ThreadState.X0, Is.EqualTo(Xd)); + } + else + { + Assert.That((ulong)ThreadState.X31, Is.EqualTo(_X31)); + } + } + + [Test, Description("UDIV , , ")] + public void Udiv_32bit([Values(0u, 31u)] uint Rd, + [Values(1u, 31u)] uint Rn, + [Values(2u, 31u)] uint Rm, + [Values(0x00000000u, 0x7FFFFFFFu, + 0x80000000u, 0xFFFFFFFFu)] [Random(8)] uint Wn, + [Values(0x00000000u, 0x7FFFFFFFu, + 0x80000000u, 0xFFFFFFFFu)] [Random(8)] uint Wm) + { + uint Opcode = 0x1AC00800; // UDIV W0, W0, W0 + Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); + + uint _W31 = TestContext.CurrentContext.Random.NextUInt(); + AThreadState ThreadState = SingleOpcode(Opcode, X1: Wn, X2: Wm, X31: _W31); + + if (Rd != 31) + { + Bits Op = new Bits(Opcode); + + AArch64.X((int)Rn, new Bits(Wn)); + AArch64.X((int)Rm, new Bits(Wm)); + Base.Udiv(Op[31], Op[20, 16], Op[9, 5], Op[4, 0]); + uint Wd = AArch64.X(32, (int)Rd).ToUInt32(); + + Assert.That((uint)ThreadState.X0, Is.EqualTo(Wd)); + } + else + { + Assert.That((uint)ThreadState.X31, Is.EqualTo(_W31)); + } + } +#endif + } +} diff --git a/Ryujinx.Tests/Cpu/CpuTestAluRx.cs b/Ryujinx.Tests/Cpu/CpuTestAluRx.cs new file mode 100644 index 000000000..26169bca6 --- /dev/null +++ b/Ryujinx.Tests/Cpu/CpuTestAluRx.cs @@ -0,0 +1,1349 @@ +//#define AluRx + +using ChocolArm64.State; + +using NUnit.Framework; + +namespace Ryujinx.Tests.Cpu +{ + using Tester; + using Tester.Types; + + [Category("AluRx"), Ignore("Tested: first half of 2018.")] + public sealed class CpuTestAluRx : CpuTest + { +#if AluRx + [SetUp] + public void SetupTester() + { + AArch64.TakeReset(false); + } + + [Test, Description("ADD , , {, {#}}")] + public void Add_X_64bit([Values(0u, 31u)] uint Rd, + [Values(1u, 31u)] uint Rn, + [Values(2u, 31u)] uint Rm, + [Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul, + 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(1)] ulong Xn_SP, + [Values((ulong)0x0000000000000000, (ulong)0x7FFFFFFFFFFFFFFF, + (ulong)0x8000000000000000, (ulong)0xFFFFFFFFFFFFFFFF)] [Random(2)] ulong Xm, + [Values(0b011u, 0b111u)] uint extend, // + [Values(0u, 1u, 2u, 3u, 4u)] uint amount) + { + uint Opcode = 0x8B206000; // ADD X0, X0, X0, UXTX #0 + Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); + Opcode |= ((extend & 7) << 13) | ((amount & 7) << 10); + Bits Op = new Bits(Opcode); + + AThreadState ThreadState; + + if (Rn != 31) + { + ulong _X31 = TestContext.CurrentContext.Random.NextULong(); + ThreadState = SingleOpcode(Opcode, X1: Xn_SP, X2: Xm, X31: _X31); + + AArch64.X((int)Rn, new Bits(Xn_SP)); + } + else + { + ThreadState = SingleOpcode(Opcode, X31: Xn_SP, X2: Xm); + + AArch64.SP(new Bits(Xn_SP)); + } + + AArch64.X((int)Rm, new Bits(Xm)); + Base.Add_Rx(Op[31], Op[20, 16], Op[15, 13], Op[12, 10], Op[9, 5], Op[4, 0]); + + if (Rd != 31) + { + ulong Xd = AArch64.X(64, (int)Rd).ToUInt64(); + + Assert.That((ulong)ThreadState.X0, Is.EqualTo(Xd)); + } + else + { + ulong SP = AArch64.SP(64).ToUInt64(); + + Assert.That((ulong)ThreadState.X31, Is.EqualTo(SP)); + } + } + + [Test, Description("ADD , , {, {#}}")] + public void Add_W_64bit([Values(0u, 31u)] uint Rd, + [Values(1u, 31u)] uint Rn, + [Values(2u, 31u)] uint Rm, + [Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul, + 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(1)] ulong Xn_SP, + [Values((uint)0x00000000, (uint)0x7FFFFFFF, + (uint)0x80000000, (uint)0xFFFFFFFF)] [Random(2)] uint Wm, + [Values(0b000u, 0b001u, 0b010u, // + [Values(0u, 1u, 2u, 3u, 4u)] uint amount) + { + uint Opcode = 0x8B200000; // ADD X0, X0, W0, UXTB #0 + Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); + Opcode |= ((extend & 7) << 13) | ((amount & 7) << 10); + Bits Op = new Bits(Opcode); + + AThreadState ThreadState; + + if (Rn != 31) + { + ulong _X31 = TestContext.CurrentContext.Random.NextULong(); + ThreadState = SingleOpcode(Opcode, X1: Xn_SP, X2: Wm, X31: _X31); + + AArch64.X((int)Rn, new Bits(Xn_SP)); + } + else + { + ThreadState = SingleOpcode(Opcode, X31: Xn_SP, X2: Wm); + + AArch64.SP(new Bits(Xn_SP)); + } + + AArch64.X((int)Rm, new Bits(Wm)); + Base.Add_Rx(Op[31], Op[20, 16], Op[15, 13], Op[12, 10], Op[9, 5], Op[4, 0]); + + if (Rd != 31) + { + ulong Xd = AArch64.X(64, (int)Rd).ToUInt64(); + + Assert.That((ulong)ThreadState.X0, Is.EqualTo(Xd)); + } + else + { + ulong SP = AArch64.SP(64).ToUInt64(); + + Assert.That((ulong)ThreadState.X31, Is.EqualTo(SP)); + } + } + + [Test, Description("ADD , , {, {#}}")] + public void Add_H_64bit([Values(0u, 31u)] uint Rd, + [Values(1u, 31u)] uint Rn, + [Values(2u, 31u)] uint Rm, + [Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul, + 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(1)] ulong Xn_SP, + [Values((ushort)0x0000, (ushort)0x7FFF, + (ushort)0x8000, (ushort)0xFFFF)] [Random(2)] ushort Wm, + [Values(0b000u, 0b001u, 0b010u, // + [Values(0u, 1u, 2u, 3u, 4u)] uint amount) + { + uint Opcode = 0x8B200000; // ADD X0, X0, W0, UXTB #0 + Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); + Opcode |= ((extend & 7) << 13) | ((amount & 7) << 10); + Bits Op = new Bits(Opcode); + + AThreadState ThreadState; + + if (Rn != 31) + { + ulong _X31 = TestContext.CurrentContext.Random.NextULong(); + ThreadState = SingleOpcode(Opcode, X1: Xn_SP, X2: Wm, X31: _X31); + + AArch64.X((int)Rn, new Bits(Xn_SP)); + } + else + { + ThreadState = SingleOpcode(Opcode, X31: Xn_SP, X2: Wm); + + AArch64.SP(new Bits(Xn_SP)); + } + + AArch64.X((int)Rm, new Bits(Wm)); + Base.Add_Rx(Op[31], Op[20, 16], Op[15, 13], Op[12, 10], Op[9, 5], Op[4, 0]); + + if (Rd != 31) + { + ulong Xd = AArch64.X(64, (int)Rd).ToUInt64(); + + Assert.That((ulong)ThreadState.X0, Is.EqualTo(Xd)); + } + else + { + ulong SP = AArch64.SP(64).ToUInt64(); + + Assert.That((ulong)ThreadState.X31, Is.EqualTo(SP)); + } + } + + [Test, Description("ADD , , {, {#}}")] + public void Add_B_64bit([Values(0u, 31u)] uint Rd, + [Values(1u, 31u)] uint Rn, + [Values(2u, 31u)] uint Rm, + [Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul, + 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(1)] ulong Xn_SP, + [Values((byte)0x00, (byte)0x7F, + (byte)0x80, (byte)0xFF)] [Random(2)] byte Wm, + [Values(0b000u, 0b001u, 0b010u, // + [Values(0u, 1u, 2u, 3u, 4u)] uint amount) + { + uint Opcode = 0x8B200000; // ADD X0, X0, W0, UXTB #0 + Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); + Opcode |= ((extend & 7) << 13) | ((amount & 7) << 10); + Bits Op = new Bits(Opcode); + + AThreadState ThreadState; + + if (Rn != 31) + { + ulong _X31 = TestContext.CurrentContext.Random.NextULong(); + ThreadState = SingleOpcode(Opcode, X1: Xn_SP, X2: Wm, X31: _X31); + + AArch64.X((int)Rn, new Bits(Xn_SP)); + } + else + { + ThreadState = SingleOpcode(Opcode, X31: Xn_SP, X2: Wm); + + AArch64.SP(new Bits(Xn_SP)); + } + + AArch64.X((int)Rm, new Bits(Wm)); + Base.Add_Rx(Op[31], Op[20, 16], Op[15, 13], Op[12, 10], Op[9, 5], Op[4, 0]); + + if (Rd != 31) + { + ulong Xd = AArch64.X(64, (int)Rd).ToUInt64(); + + Assert.That((ulong)ThreadState.X0, Is.EqualTo(Xd)); + } + else + { + ulong SP = AArch64.SP(64).ToUInt64(); + + Assert.That((ulong)ThreadState.X31, Is.EqualTo(SP)); + } + } + + [Test, Description("ADD , , {, {#}}")] + public void Add_W_32bit([Values(0u, 31u)] uint Rd, + [Values(1u, 31u)] uint Rn, + [Values(2u, 31u)] uint Rm, + [Values(0x00000000u, 0x7FFFFFFFu, + 0x80000000u, 0xFFFFFFFFu)] [Random(1)] uint Wn_WSP, + [Values((uint)0x00000000, (uint)0x7FFFFFFF, + (uint)0x80000000, (uint)0xFFFFFFFF)] [Random(2)] uint Wm, + [Values(0b000u, 0b001u, 0b010u, 0b011u, // + [Values(0u, 1u, 2u, 3u, 4u)] uint amount) + { + uint Opcode = 0x0B200000; // ADD W0, W0, W0, UXTB #0 + Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); + Opcode |= ((extend & 7) << 13) | ((amount & 7) << 10); + Bits Op = new Bits(Opcode); + + AThreadState ThreadState; + + if (Rn != 31) + { + uint _W31 = TestContext.CurrentContext.Random.NextUInt(); + ThreadState = SingleOpcode(Opcode, X1: Wn_WSP, X2: Wm, X31: _W31); + + AArch64.X((int)Rn, new Bits(Wn_WSP)); + } + else + { + ThreadState = SingleOpcode(Opcode, X31: Wn_WSP, X2: Wm); + + AArch64.SP(new Bits(Wn_WSP)); + } + + AArch64.X((int)Rm, new Bits(Wm)); + Base.Add_Rx(Op[31], Op[20, 16], Op[15, 13], Op[12, 10], Op[9, 5], Op[4, 0]); + + if (Rd != 31) + { + uint Wd = AArch64.X(32, (int)Rd).ToUInt32(); + + Assert.That((uint)ThreadState.X0, Is.EqualTo(Wd)); + } + else + { + uint WSP = AArch64.SP(32).ToUInt32(); + + Assert.That((uint)ThreadState.X31, Is.EqualTo(WSP)); + } + } + + [Test, Description("ADD , , {, {#}}")] + public void Add_H_32bit([Values(0u, 31u)] uint Rd, + [Values(1u, 31u)] uint Rn, + [Values(2u, 31u)] uint Rm, + [Values(0x00000000u, 0x7FFFFFFFu, + 0x80000000u, 0xFFFFFFFFu)] [Random(1)] uint Wn_WSP, + [Values((ushort)0x0000, (ushort)0x7FFF, + (ushort)0x8000, (ushort)0xFFFF)] [Random(2)] ushort Wm, + [Values(0b000u, 0b001u, 0b010u, 0b011u, // + [Values(0u, 1u, 2u, 3u, 4u)] uint amount) + { + uint Opcode = 0x0B200000; // ADD W0, W0, W0, UXTB #0 + Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); + Opcode |= ((extend & 7) << 13) | ((amount & 7) << 10); + Bits Op = new Bits(Opcode); + + AThreadState ThreadState; + + if (Rn != 31) + { + uint _W31 = TestContext.CurrentContext.Random.NextUInt(); + ThreadState = SingleOpcode(Opcode, X1: Wn_WSP, X2: Wm, X31: _W31); + + AArch64.X((int)Rn, new Bits(Wn_WSP)); + } + else + { + ThreadState = SingleOpcode(Opcode, X31: Wn_WSP, X2: Wm); + + AArch64.SP(new Bits(Wn_WSP)); + } + + AArch64.X((int)Rm, new Bits(Wm)); + Base.Add_Rx(Op[31], Op[20, 16], Op[15, 13], Op[12, 10], Op[9, 5], Op[4, 0]); + + if (Rd != 31) + { + uint Wd = AArch64.X(32, (int)Rd).ToUInt32(); + + Assert.That((uint)ThreadState.X0, Is.EqualTo(Wd)); + } + else + { + uint WSP = AArch64.SP(32).ToUInt32(); + + Assert.That((uint)ThreadState.X31, Is.EqualTo(WSP)); + } + } + + [Test, Description("ADD , , {, {#}}")] + public void Add_B_32bit([Values(0u, 31u)] uint Rd, + [Values(1u, 31u)] uint Rn, + [Values(2u, 31u)] uint Rm, + [Values(0x00000000u, 0x7FFFFFFFu, + 0x80000000u, 0xFFFFFFFFu)] [Random(1)] uint Wn_WSP, + [Values((byte)0x00, (byte)0x7F, + (byte)0x80, (byte)0xFF)] [Random(2)] byte Wm, + [Values(0b000u, 0b001u, 0b010u, 0b011u, // + [Values(0u, 1u, 2u, 3u, 4u)] uint amount) + { + uint Opcode = 0x0B200000; // ADD W0, W0, W0, UXTB #0 + Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); + Opcode |= ((extend & 7) << 13) | ((amount & 7) << 10); + Bits Op = new Bits(Opcode); + + AThreadState ThreadState; + + if (Rn != 31) + { + uint _W31 = TestContext.CurrentContext.Random.NextUInt(); + ThreadState = SingleOpcode(Opcode, X1: Wn_WSP, X2: Wm, X31: _W31); + + AArch64.X((int)Rn, new Bits(Wn_WSP)); + } + else + { + ThreadState = SingleOpcode(Opcode, X31: Wn_WSP, X2: Wm); + + AArch64.SP(new Bits(Wn_WSP)); + } + + AArch64.X((int)Rm, new Bits(Wm)); + Base.Add_Rx(Op[31], Op[20, 16], Op[15, 13], Op[12, 10], Op[9, 5], Op[4, 0]); + + if (Rd != 31) + { + uint Wd = AArch64.X(32, (int)Rd).ToUInt32(); + + Assert.That((uint)ThreadState.X0, Is.EqualTo(Wd)); + } + else + { + uint WSP = AArch64.SP(32).ToUInt32(); + + Assert.That((uint)ThreadState.X31, Is.EqualTo(WSP)); + } + } + + [Test, Description("ADDS , , {, {#}}")] + public void Adds_X_64bit([Values(0u, 31u)] uint Rd, + [Values(1u, 31u)] uint Rn, + [Values(2u, 31u)] uint Rm, + [Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul, + 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(1)] ulong Xn_SP, + [Values((ulong)0x0000000000000000, (ulong)0x7FFFFFFFFFFFFFFF, + (ulong)0x8000000000000000, (ulong)0xFFFFFFFFFFFFFFFF)] [Random(2)] ulong Xm, + [Values(0b011u, 0b111u)] uint extend, // + [Values(0u, 1u, 2u, 3u, 4u)] uint amount) + { + uint Opcode = 0xAB206000; // ADDS X0, X0, X0, UXTX #0 + Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); + Opcode |= ((extend & 7) << 13) | ((amount & 7) << 10); + Bits Op = new Bits(Opcode); + + AThreadState ThreadState = SingleOpcode(Opcode, X1: Xn_SP, X2: Xm, X31: Xn_SP); + + AArch64.X((int)Rn, new Bits(Xn_SP)); + AArch64.X((int)Rm, new Bits(Xm)); + AArch64.SP(new Bits(Xn_SP)); + Base.Adds_Rx(Op[31], Op[20, 16], Op[15, 13], Op[12, 10], Op[9, 5], Op[4, 0]); + + if (Rd != 31) + { + ulong Xd = AArch64.X(64, (int)Rd).ToUInt64(); + + Assert.That((ulong)ThreadState.X0, Is.EqualTo(Xd)); + } + else + { + ulong _X31 = AArch64.SP(64).ToUInt64(); + + Assert.That((ulong)ThreadState.X31, Is.EqualTo(_X31)); + } + Assert.Multiple(() => + { + Assert.That(ThreadState.Negative, Is.EqualTo(Shared.PSTATE.N)); + Assert.That(ThreadState.Zero, Is.EqualTo(Shared.PSTATE.Z)); + Assert.That(ThreadState.Carry, Is.EqualTo(Shared.PSTATE.C)); + Assert.That(ThreadState.Overflow, Is.EqualTo(Shared.PSTATE.V)); + }); + } + + [Test, Description("ADDS , , {, {#}}")] + public void Adds_W_64bit([Values(0u, 31u)] uint Rd, + [Values(1u, 31u)] uint Rn, + [Values(2u, 31u)] uint Rm, + [Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul, + 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(1)] ulong Xn_SP, + [Values((uint)0x00000000, (uint)0x7FFFFFFF, + (uint)0x80000000, (uint)0xFFFFFFFF)] [Random(2)] uint Wm, + [Values(0b000u, 0b001u, 0b010u, // + [Values(0u, 1u, 2u, 3u, 4u)] uint amount) + { + uint Opcode = 0xAB200000; // ADDS X0, X0, W0, UXTB #0 + Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); + Opcode |= ((extend & 7) << 13) | ((amount & 7) << 10); + Bits Op = new Bits(Opcode); + + AThreadState ThreadState = SingleOpcode(Opcode, X1: Xn_SP, X2: Wm, X31: Xn_SP); + + AArch64.X((int)Rn, new Bits(Xn_SP)); + AArch64.X((int)Rm, new Bits(Wm)); + AArch64.SP(new Bits(Xn_SP)); + Base.Adds_Rx(Op[31], Op[20, 16], Op[15, 13], Op[12, 10], Op[9, 5], Op[4, 0]); + + if (Rd != 31) + { + ulong Xd = AArch64.X(64, (int)Rd).ToUInt64(); + + Assert.That((ulong)ThreadState.X0, Is.EqualTo(Xd)); + } + else + { + ulong _X31 = AArch64.SP(64).ToUInt64(); + + Assert.That((ulong)ThreadState.X31, Is.EqualTo(_X31)); + } + Assert.Multiple(() => + { + Assert.That(ThreadState.Negative, Is.EqualTo(Shared.PSTATE.N)); + Assert.That(ThreadState.Zero, Is.EqualTo(Shared.PSTATE.Z)); + Assert.That(ThreadState.Carry, Is.EqualTo(Shared.PSTATE.C)); + Assert.That(ThreadState.Overflow, Is.EqualTo(Shared.PSTATE.V)); + }); + } + + [Test, Description("ADDS , , {, {#}}")] + public void Adds_H_64bit([Values(0u, 31u)] uint Rd, + [Values(1u, 31u)] uint Rn, + [Values(2u, 31u)] uint Rm, + [Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul, + 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(1)] ulong Xn_SP, + [Values((ushort)0x0000, (ushort)0x7FFF, + (ushort)0x8000, (ushort)0xFFFF)] [Random(2)] ushort Wm, + [Values(0b000u, 0b001u, 0b010u, // + [Values(0u, 1u, 2u, 3u, 4u)] uint amount) + { + uint Opcode = 0xAB200000; // ADDS X0, X0, W0, UXTB #0 + Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); + Opcode |= ((extend & 7) << 13) | ((amount & 7) << 10); + Bits Op = new Bits(Opcode); + + AThreadState ThreadState = SingleOpcode(Opcode, X1: Xn_SP, X2: Wm, X31: Xn_SP); + + AArch64.X((int)Rn, new Bits(Xn_SP)); + AArch64.X((int)Rm, new Bits(Wm)); + AArch64.SP(new Bits(Xn_SP)); + Base.Adds_Rx(Op[31], Op[20, 16], Op[15, 13], Op[12, 10], Op[9, 5], Op[4, 0]); + + if (Rd != 31) + { + ulong Xd = AArch64.X(64, (int)Rd).ToUInt64(); + + Assert.That((ulong)ThreadState.X0, Is.EqualTo(Xd)); + } + else + { + ulong _X31 = AArch64.SP(64).ToUInt64(); + + Assert.That((ulong)ThreadState.X31, Is.EqualTo(_X31)); + } + Assert.Multiple(() => + { + Assert.That(ThreadState.Negative, Is.EqualTo(Shared.PSTATE.N)); + Assert.That(ThreadState.Zero, Is.EqualTo(Shared.PSTATE.Z)); + Assert.That(ThreadState.Carry, Is.EqualTo(Shared.PSTATE.C)); + Assert.That(ThreadState.Overflow, Is.EqualTo(Shared.PSTATE.V)); + }); + } + + [Test, Description("ADDS , , {, {#}}")] + public void Adds_B_64bit([Values(0u, 31u)] uint Rd, + [Values(1u, 31u)] uint Rn, + [Values(2u, 31u)] uint Rm, + [Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul, + 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(1)] ulong Xn_SP, + [Values((byte)0x00, (byte)0x7F, + (byte)0x80, (byte)0xFF)] [Random(2)] byte Wm, + [Values(0b000u, 0b001u, 0b010u, // + [Values(0u, 1u, 2u, 3u, 4u)] uint amount) + { + uint Opcode = 0xAB200000; // ADDS X0, X0, W0, UXTB #0 + Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); + Opcode |= ((extend & 7) << 13) | ((amount & 7) << 10); + Bits Op = new Bits(Opcode); + + AThreadState ThreadState = SingleOpcode(Opcode, X1: Xn_SP, X2: Wm, X31: Xn_SP); + + AArch64.X((int)Rn, new Bits(Xn_SP)); + AArch64.X((int)Rm, new Bits(Wm)); + AArch64.SP(new Bits(Xn_SP)); + Base.Adds_Rx(Op[31], Op[20, 16], Op[15, 13], Op[12, 10], Op[9, 5], Op[4, 0]); + + if (Rd != 31) + { + ulong Xd = AArch64.X(64, (int)Rd).ToUInt64(); + + Assert.That((ulong)ThreadState.X0, Is.EqualTo(Xd)); + } + else + { + ulong _X31 = AArch64.SP(64).ToUInt64(); + + Assert.That((ulong)ThreadState.X31, Is.EqualTo(_X31)); + } + Assert.Multiple(() => + { + Assert.That(ThreadState.Negative, Is.EqualTo(Shared.PSTATE.N)); + Assert.That(ThreadState.Zero, Is.EqualTo(Shared.PSTATE.Z)); + Assert.That(ThreadState.Carry, Is.EqualTo(Shared.PSTATE.C)); + Assert.That(ThreadState.Overflow, Is.EqualTo(Shared.PSTATE.V)); + }); + } + + [Test, Description("ADDS , , {, {#}}")] + public void Adds_W_32bit([Values(0u, 31u)] uint Rd, + [Values(1u, 31u)] uint Rn, + [Values(2u, 31u)] uint Rm, + [Values(0x00000000u, 0x7FFFFFFFu, + 0x80000000u, 0xFFFFFFFFu)] [Random(1)] uint Wn_WSP, + [Values((uint)0x00000000, (uint)0x7FFFFFFF, + (uint)0x80000000, (uint)0xFFFFFFFF)] [Random(2)] uint Wm, + [Values(0b000u, 0b001u, 0b010u, 0b011u, // + [Values(0u, 1u, 2u, 3u, 4u)] uint amount) + { + uint Opcode = 0x2B200000; // ADDS W0, W0, W0, UXTB #0 + Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); + Opcode |= ((extend & 7) << 13) | ((amount & 7) << 10); + Bits Op = new Bits(Opcode); + + AThreadState ThreadState = SingleOpcode(Opcode, X1: Wn_WSP, X2: Wm, X31: Wn_WSP); + + AArch64.X((int)Rn, new Bits(Wn_WSP)); + AArch64.X((int)Rm, new Bits(Wm)); + AArch64.SP(new Bits(Wn_WSP)); + Base.Adds_Rx(Op[31], Op[20, 16], Op[15, 13], Op[12, 10], Op[9, 5], Op[4, 0]); + + if (Rd != 31) + { + uint Wd = AArch64.X(32, (int)Rd).ToUInt32(); + + Assert.That((uint)ThreadState.X0, Is.EqualTo(Wd)); + } + else + { + uint _W31 = AArch64.SP(32).ToUInt32(); + + Assert.That((uint)ThreadState.X31, Is.EqualTo(_W31)); + } + Assert.Multiple(() => + { + Assert.That(ThreadState.Negative, Is.EqualTo(Shared.PSTATE.N)); + Assert.That(ThreadState.Zero, Is.EqualTo(Shared.PSTATE.Z)); + Assert.That(ThreadState.Carry, Is.EqualTo(Shared.PSTATE.C)); + Assert.That(ThreadState.Overflow, Is.EqualTo(Shared.PSTATE.V)); + }); + } + + [Test, Description("ADDS , , {, {#}}")] + public void Adds_H_32bit([Values(0u, 31u)] uint Rd, + [Values(1u, 31u)] uint Rn, + [Values(2u, 31u)] uint Rm, + [Values(0x00000000u, 0x7FFFFFFFu, + 0x80000000u, 0xFFFFFFFFu)] [Random(1)] uint Wn_WSP, + [Values((ushort)0x0000, (ushort)0x7FFF, + (ushort)0x8000, (ushort)0xFFFF)] [Random(2)] ushort Wm, + [Values(0b000u, 0b001u, 0b010u, 0b011u, // + [Values(0u, 1u, 2u, 3u, 4u)] uint amount) + { + uint Opcode = 0x2B200000; // ADDS W0, W0, W0, UXTB #0 + Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); + Opcode |= ((extend & 7) << 13) | ((amount & 7) << 10); + Bits Op = new Bits(Opcode); + + AThreadState ThreadState = SingleOpcode(Opcode, X1: Wn_WSP, X2: Wm, X31: Wn_WSP); + + AArch64.X((int)Rn, new Bits(Wn_WSP)); + AArch64.X((int)Rm, new Bits(Wm)); + AArch64.SP(new Bits(Wn_WSP)); + Base.Adds_Rx(Op[31], Op[20, 16], Op[15, 13], Op[12, 10], Op[9, 5], Op[4, 0]); + + if (Rd != 31) + { + uint Wd = AArch64.X(32, (int)Rd).ToUInt32(); + + Assert.That((uint)ThreadState.X0, Is.EqualTo(Wd)); + } + else + { + uint _W31 = AArch64.SP(32).ToUInt32(); + + Assert.That((uint)ThreadState.X31, Is.EqualTo(_W31)); + } + Assert.Multiple(() => + { + Assert.That(ThreadState.Negative, Is.EqualTo(Shared.PSTATE.N)); + Assert.That(ThreadState.Zero, Is.EqualTo(Shared.PSTATE.Z)); + Assert.That(ThreadState.Carry, Is.EqualTo(Shared.PSTATE.C)); + Assert.That(ThreadState.Overflow, Is.EqualTo(Shared.PSTATE.V)); + }); + } + + [Test, Description("ADDS , , {, {#}}")] + public void Adds_B_32bit([Values(0u, 31u)] uint Rd, + [Values(1u, 31u)] uint Rn, + [Values(2u, 31u)] uint Rm, + [Values(0x00000000u, 0x7FFFFFFFu, + 0x80000000u, 0xFFFFFFFFu)] [Random(1)] uint Wn_WSP, + [Values((byte)0x00, (byte)0x7F, + (byte)0x80, (byte)0xFF)] [Random(2)] byte Wm, + [Values(0b000u, 0b001u, 0b010u, 0b011u, // + [Values(0u, 1u, 2u, 3u, 4u)] uint amount) + { + uint Opcode = 0x2B200000; // ADDS W0, W0, W0, UXTB #0 + Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); + Opcode |= ((extend & 7) << 13) | ((amount & 7) << 10); + Bits Op = new Bits(Opcode); + + AThreadState ThreadState = SingleOpcode(Opcode, X1: Wn_WSP, X2: Wm, X31: Wn_WSP); + + AArch64.X((int)Rn, new Bits(Wn_WSP)); + AArch64.X((int)Rm, new Bits(Wm)); + AArch64.SP(new Bits(Wn_WSP)); + Base.Adds_Rx(Op[31], Op[20, 16], Op[15, 13], Op[12, 10], Op[9, 5], Op[4, 0]); + + if (Rd != 31) + { + uint Wd = AArch64.X(32, (int)Rd).ToUInt32(); + + Assert.That((uint)ThreadState.X0, Is.EqualTo(Wd)); + } + else + { + uint _W31 = AArch64.SP(32).ToUInt32(); + + Assert.That((uint)ThreadState.X31, Is.EqualTo(_W31)); + } + Assert.Multiple(() => + { + Assert.That(ThreadState.Negative, Is.EqualTo(Shared.PSTATE.N)); + Assert.That(ThreadState.Zero, Is.EqualTo(Shared.PSTATE.Z)); + Assert.That(ThreadState.Carry, Is.EqualTo(Shared.PSTATE.C)); + Assert.That(ThreadState.Overflow, Is.EqualTo(Shared.PSTATE.V)); + }); + } + + [Test, Description("SUB , , {, {#}}")] + public void Sub_X_64bit([Values(0u, 31u)] uint Rd, + [Values(1u, 31u)] uint Rn, + [Values(2u, 31u)] uint Rm, + [Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul, + 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(1)] ulong Xn_SP, + [Values((ulong)0x0000000000000000, (ulong)0x7FFFFFFFFFFFFFFF, + (ulong)0x8000000000000000, (ulong)0xFFFFFFFFFFFFFFFF)] [Random(2)] ulong Xm, + [Values(0b011u, 0b111u)] uint extend, // + [Values(0u, 1u, 2u, 3u, 4u)] uint amount) + { + uint Opcode = 0xCB206000; // SUB X0, X0, X0, UXTX #0 + Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); + Opcode |= ((extend & 7) << 13) | ((amount & 7) << 10); + Bits Op = new Bits(Opcode); + + AThreadState ThreadState; + + if (Rn != 31) + { + ulong _X31 = TestContext.CurrentContext.Random.NextULong(); + ThreadState = SingleOpcode(Opcode, X1: Xn_SP, X2: Xm, X31: _X31); + + AArch64.X((int)Rn, new Bits(Xn_SP)); + } + else + { + ThreadState = SingleOpcode(Opcode, X31: Xn_SP, X2: Xm); + + AArch64.SP(new Bits(Xn_SP)); + } + + AArch64.X((int)Rm, new Bits(Xm)); + Base.Sub_Rx(Op[31], Op[20, 16], Op[15, 13], Op[12, 10], Op[9, 5], Op[4, 0]); + + if (Rd != 31) + { + ulong Xd = AArch64.X(64, (int)Rd).ToUInt64(); + + Assert.That((ulong)ThreadState.X0, Is.EqualTo(Xd)); + } + else + { + ulong SP = AArch64.SP(64).ToUInt64(); + + Assert.That((ulong)ThreadState.X31, Is.EqualTo(SP)); + } + } + + [Test, Description("SUB , , {, {#}}")] + public void Sub_W_64bit([Values(0u, 31u)] uint Rd, + [Values(1u, 31u)] uint Rn, + [Values(2u, 31u)] uint Rm, + [Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul, + 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(1)] ulong Xn_SP, + [Values((uint)0x00000000, (uint)0x7FFFFFFF, + (uint)0x80000000, (uint)0xFFFFFFFF)] [Random(2)] uint Wm, + [Values(0b000u, 0b001u, 0b010u, // + [Values(0u, 1u, 2u, 3u, 4u)] uint amount) + { + uint Opcode = 0xCB200000; // SUB X0, X0, W0, UXTB #0 + Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); + Opcode |= ((extend & 7) << 13) | ((amount & 7) << 10); + Bits Op = new Bits(Opcode); + + AThreadState ThreadState; + + if (Rn != 31) + { + ulong _X31 = TestContext.CurrentContext.Random.NextULong(); + ThreadState = SingleOpcode(Opcode, X1: Xn_SP, X2: Wm, X31: _X31); + + AArch64.X((int)Rn, new Bits(Xn_SP)); + } + else + { + ThreadState = SingleOpcode(Opcode, X31: Xn_SP, X2: Wm); + + AArch64.SP(new Bits(Xn_SP)); + } + + AArch64.X((int)Rm, new Bits(Wm)); + Base.Sub_Rx(Op[31], Op[20, 16], Op[15, 13], Op[12, 10], Op[9, 5], Op[4, 0]); + + if (Rd != 31) + { + ulong Xd = AArch64.X(64, (int)Rd).ToUInt64(); + + Assert.That((ulong)ThreadState.X0, Is.EqualTo(Xd)); + } + else + { + ulong SP = AArch64.SP(64).ToUInt64(); + + Assert.That((ulong)ThreadState.X31, Is.EqualTo(SP)); + } + } + + [Test, Description("SUB , , {, {#}}")] + public void Sub_H_64bit([Values(0u, 31u)] uint Rd, + [Values(1u, 31u)] uint Rn, + [Values(2u, 31u)] uint Rm, + [Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul, + 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(1)] ulong Xn_SP, + [Values((ushort)0x0000, (ushort)0x7FFF, + (ushort)0x8000, (ushort)0xFFFF)] [Random(2)] ushort Wm, + [Values(0b000u, 0b001u, 0b010u, // + [Values(0u, 1u, 2u, 3u, 4u)] uint amount) + { + uint Opcode = 0xCB200000; // SUB X0, X0, W0, UXTB #0 + Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); + Opcode |= ((extend & 7) << 13) | ((amount & 7) << 10); + Bits Op = new Bits(Opcode); + + AThreadState ThreadState; + + if (Rn != 31) + { + ulong _X31 = TestContext.CurrentContext.Random.NextULong(); + ThreadState = SingleOpcode(Opcode, X1: Xn_SP, X2: Wm, X31: _X31); + + AArch64.X((int)Rn, new Bits(Xn_SP)); + } + else + { + ThreadState = SingleOpcode(Opcode, X31: Xn_SP, X2: Wm); + + AArch64.SP(new Bits(Xn_SP)); + } + + AArch64.X((int)Rm, new Bits(Wm)); + Base.Sub_Rx(Op[31], Op[20, 16], Op[15, 13], Op[12, 10], Op[9, 5], Op[4, 0]); + + if (Rd != 31) + { + ulong Xd = AArch64.X(64, (int)Rd).ToUInt64(); + + Assert.That((ulong)ThreadState.X0, Is.EqualTo(Xd)); + } + else + { + ulong SP = AArch64.SP(64).ToUInt64(); + + Assert.That((ulong)ThreadState.X31, Is.EqualTo(SP)); + } + } + + [Test, Description("SUB , , {, {#}}")] + public void Sub_B_64bit([Values(0u, 31u)] uint Rd, + [Values(1u, 31u)] uint Rn, + [Values(2u, 31u)] uint Rm, + [Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul, + 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(1)] ulong Xn_SP, + [Values((byte)0x00, (byte)0x7F, + (byte)0x80, (byte)0xFF)] [Random(2)] byte Wm, + [Values(0b000u, 0b001u, 0b010u, // + [Values(0u, 1u, 2u, 3u, 4u)] uint amount) + { + uint Opcode = 0xCB200000; // SUB X0, X0, W0, UXTB #0 + Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); + Opcode |= ((extend & 7) << 13) | ((amount & 7) << 10); + Bits Op = new Bits(Opcode); + + AThreadState ThreadState; + + if (Rn != 31) + { + ulong _X31 = TestContext.CurrentContext.Random.NextULong(); + ThreadState = SingleOpcode(Opcode, X1: Xn_SP, X2: Wm, X31: _X31); + + AArch64.X((int)Rn, new Bits(Xn_SP)); + } + else + { + ThreadState = SingleOpcode(Opcode, X31: Xn_SP, X2: Wm); + + AArch64.SP(new Bits(Xn_SP)); + } + + AArch64.X((int)Rm, new Bits(Wm)); + Base.Sub_Rx(Op[31], Op[20, 16], Op[15, 13], Op[12, 10], Op[9, 5], Op[4, 0]); + + if (Rd != 31) + { + ulong Xd = AArch64.X(64, (int)Rd).ToUInt64(); + + Assert.That((ulong)ThreadState.X0, Is.EqualTo(Xd)); + } + else + { + ulong SP = AArch64.SP(64).ToUInt64(); + + Assert.That((ulong)ThreadState.X31, Is.EqualTo(SP)); + } + } + + [Test, Description("SUB , , {, {#}}")] + public void Sub_W_32bit([Values(0u, 31u)] uint Rd, + [Values(1u, 31u)] uint Rn, + [Values(2u, 31u)] uint Rm, + [Values(0x00000000u, 0x7FFFFFFFu, + 0x80000000u, 0xFFFFFFFFu)] [Random(1)] uint Wn_WSP, + [Values((uint)0x00000000, (uint)0x7FFFFFFF, + (uint)0x80000000, (uint)0xFFFFFFFF)] [Random(2)] uint Wm, + [Values(0b000u, 0b001u, 0b010u, 0b011u, // + [Values(0u, 1u, 2u, 3u, 4u)] uint amount) + { + uint Opcode = 0x4B200000; // SUB W0, W0, W0, UXTB #0 + Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); + Opcode |= ((extend & 7) << 13) | ((amount & 7) << 10); + Bits Op = new Bits(Opcode); + + AThreadState ThreadState; + + if (Rn != 31) + { + uint _W31 = TestContext.CurrentContext.Random.NextUInt(); + ThreadState = SingleOpcode(Opcode, X1: Wn_WSP, X2: Wm, X31: _W31); + + AArch64.X((int)Rn, new Bits(Wn_WSP)); + } + else + { + ThreadState = SingleOpcode(Opcode, X31: Wn_WSP, X2: Wm); + + AArch64.SP(new Bits(Wn_WSP)); + } + + AArch64.X((int)Rm, new Bits(Wm)); + Base.Sub_Rx(Op[31], Op[20, 16], Op[15, 13], Op[12, 10], Op[9, 5], Op[4, 0]); + + if (Rd != 31) + { + uint Wd = AArch64.X(32, (int)Rd).ToUInt32(); + + Assert.That((uint)ThreadState.X0, Is.EqualTo(Wd)); + } + else + { + uint WSP = AArch64.SP(32).ToUInt32(); + + Assert.That((uint)ThreadState.X31, Is.EqualTo(WSP)); + } + } + + [Test, Description("SUB , , {, {#}}")] + public void Sub_H_32bit([Values(0u, 31u)] uint Rd, + [Values(1u, 31u)] uint Rn, + [Values(2u, 31u)] uint Rm, + [Values(0x00000000u, 0x7FFFFFFFu, + 0x80000000u, 0xFFFFFFFFu)] [Random(1)] uint Wn_WSP, + [Values((ushort)0x0000, (ushort)0x7FFF, + (ushort)0x8000, (ushort)0xFFFF)] [Random(2)] ushort Wm, + [Values(0b000u, 0b001u, 0b010u, 0b011u, // + [Values(0u, 1u, 2u, 3u, 4u)] uint amount) + { + uint Opcode = 0x4B200000; // SUB W0, W0, W0, UXTB #0 + Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); + Opcode |= ((extend & 7) << 13) | ((amount & 7) << 10); + Bits Op = new Bits(Opcode); + + AThreadState ThreadState; + + if (Rn != 31) + { + uint _W31 = TestContext.CurrentContext.Random.NextUInt(); + ThreadState = SingleOpcode(Opcode, X1: Wn_WSP, X2: Wm, X31: _W31); + + AArch64.X((int)Rn, new Bits(Wn_WSP)); + } + else + { + ThreadState = SingleOpcode(Opcode, X31: Wn_WSP, X2: Wm); + + AArch64.SP(new Bits(Wn_WSP)); + } + + AArch64.X((int)Rm, new Bits(Wm)); + Base.Sub_Rx(Op[31], Op[20, 16], Op[15, 13], Op[12, 10], Op[9, 5], Op[4, 0]); + + if (Rd != 31) + { + uint Wd = AArch64.X(32, (int)Rd).ToUInt32(); + + Assert.That((uint)ThreadState.X0, Is.EqualTo(Wd)); + } + else + { + uint WSP = AArch64.SP(32).ToUInt32(); + + Assert.That((uint)ThreadState.X31, Is.EqualTo(WSP)); + } + } + + [Test, Description("SUB , , {, {#}}")] + public void Sub_B_32bit([Values(0u, 31u)] uint Rd, + [Values(1u, 31u)] uint Rn, + [Values(2u, 31u)] uint Rm, + [Values(0x00000000u, 0x7FFFFFFFu, + 0x80000000u, 0xFFFFFFFFu)] [Random(1)] uint Wn_WSP, + [Values((byte)0x00, (byte)0x7F, + (byte)0x80, (byte)0xFF)] [Random(2)] byte Wm, + [Values(0b000u, 0b001u, 0b010u, 0b011u, // + [Values(0u, 1u, 2u, 3u, 4u)] uint amount) + { + uint Opcode = 0x4B200000; // SUB W0, W0, W0, UXTB #0 + Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); + Opcode |= ((extend & 7) << 13) | ((amount & 7) << 10); + Bits Op = new Bits(Opcode); + + AThreadState ThreadState; + + if (Rn != 31) + { + uint _W31 = TestContext.CurrentContext.Random.NextUInt(); + ThreadState = SingleOpcode(Opcode, X1: Wn_WSP, X2: Wm, X31: _W31); + + AArch64.X((int)Rn, new Bits(Wn_WSP)); + } + else + { + ThreadState = SingleOpcode(Opcode, X31: Wn_WSP, X2: Wm); + + AArch64.SP(new Bits(Wn_WSP)); + } + + AArch64.X((int)Rm, new Bits(Wm)); + Base.Sub_Rx(Op[31], Op[20, 16], Op[15, 13], Op[12, 10], Op[9, 5], Op[4, 0]); + + if (Rd != 31) + { + uint Wd = AArch64.X(32, (int)Rd).ToUInt32(); + + Assert.That((uint)ThreadState.X0, Is.EqualTo(Wd)); + } + else + { + uint WSP = AArch64.SP(32).ToUInt32(); + + Assert.That((uint)ThreadState.X31, Is.EqualTo(WSP)); + } + } + + [Test, Description("SUBS , , {, {#}}")] + public void Subs_X_64bit([Values(0u, 31u)] uint Rd, + [Values(1u, 31u)] uint Rn, + [Values(2u, 31u)] uint Rm, + [Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul, + 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(1)] ulong Xn_SP, + [Values((ulong)0x0000000000000000, (ulong)0x7FFFFFFFFFFFFFFF, + (ulong)0x8000000000000000, (ulong)0xFFFFFFFFFFFFFFFF)] [Random(2)] ulong Xm, + [Values(0b011u, 0b111u)] uint extend, // + [Values(0u, 1u, 2u, 3u, 4u)] uint amount) + { + uint Opcode = 0xEB206000; // SUBS X0, X0, X0, UXTX #0 + Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); + Opcode |= ((extend & 7) << 13) | ((amount & 7) << 10); + Bits Op = new Bits(Opcode); + + AThreadState ThreadState = SingleOpcode(Opcode, X1: Xn_SP, X2: Xm, X31: Xn_SP); + + AArch64.X((int)Rn, new Bits(Xn_SP)); + AArch64.X((int)Rm, new Bits(Xm)); + AArch64.SP(new Bits(Xn_SP)); + Base.Subs_Rx(Op[31], Op[20, 16], Op[15, 13], Op[12, 10], Op[9, 5], Op[4, 0]); + + if (Rd != 31) + { + ulong Xd = AArch64.X(64, (int)Rd).ToUInt64(); + + Assert.That((ulong)ThreadState.X0, Is.EqualTo(Xd)); + } + else + { + ulong _X31 = AArch64.SP(64).ToUInt64(); + + Assert.That((ulong)ThreadState.X31, Is.EqualTo(_X31)); + } + Assert.Multiple(() => + { + Assert.That(ThreadState.Negative, Is.EqualTo(Shared.PSTATE.N)); + Assert.That(ThreadState.Zero, Is.EqualTo(Shared.PSTATE.Z)); + Assert.That(ThreadState.Carry, Is.EqualTo(Shared.PSTATE.C)); + Assert.That(ThreadState.Overflow, Is.EqualTo(Shared.PSTATE.V)); + }); + } + + [Test, Description("SUBS , , {, {#}}")] + public void Subs_W_64bit([Values(0u, 31u)] uint Rd, + [Values(1u, 31u)] uint Rn, + [Values(2u, 31u)] uint Rm, + [Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul, + 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(1)] ulong Xn_SP, + [Values((uint)0x00000000, (uint)0x7FFFFFFF, + (uint)0x80000000, (uint)0xFFFFFFFF)] [Random(2)] uint Wm, + [Values(0b000u, 0b001u, 0b010u, // + [Values(0u, 1u, 2u, 3u, 4u)] uint amount) + { + uint Opcode = 0xEB200000; // SUBS X0, X0, W0, UXTB #0 + Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); + Opcode |= ((extend & 7) << 13) | ((amount & 7) << 10); + Bits Op = new Bits(Opcode); + + AThreadState ThreadState = SingleOpcode(Opcode, X1: Xn_SP, X2: Wm, X31: Xn_SP); + + AArch64.X((int)Rn, new Bits(Xn_SP)); + AArch64.X((int)Rm, new Bits(Wm)); + AArch64.SP(new Bits(Xn_SP)); + Base.Subs_Rx(Op[31], Op[20, 16], Op[15, 13], Op[12, 10], Op[9, 5], Op[4, 0]); + + if (Rd != 31) + { + ulong Xd = AArch64.X(64, (int)Rd).ToUInt64(); + + Assert.That((ulong)ThreadState.X0, Is.EqualTo(Xd)); + } + else + { + ulong _X31 = AArch64.SP(64).ToUInt64(); + + Assert.That((ulong)ThreadState.X31, Is.EqualTo(_X31)); + } + Assert.Multiple(() => + { + Assert.That(ThreadState.Negative, Is.EqualTo(Shared.PSTATE.N)); + Assert.That(ThreadState.Zero, Is.EqualTo(Shared.PSTATE.Z)); + Assert.That(ThreadState.Carry, Is.EqualTo(Shared.PSTATE.C)); + Assert.That(ThreadState.Overflow, Is.EqualTo(Shared.PSTATE.V)); + }); + } + + [Test, Description("SUBS , , {, {#}}")] + public void Subs_H_64bit([Values(0u, 31u)] uint Rd, + [Values(1u, 31u)] uint Rn, + [Values(2u, 31u)] uint Rm, + [Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul, + 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(1)] ulong Xn_SP, + [Values((ushort)0x0000, (ushort)0x7FFF, + (ushort)0x8000, (ushort)0xFFFF)] [Random(2)] ushort Wm, + [Values(0b000u, 0b001u, 0b010u, // + [Values(0u, 1u, 2u, 3u, 4u)] uint amount) + { + uint Opcode = 0xEB200000; // SUBS X0, X0, W0, UXTB #0 + Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); + Opcode |= ((extend & 7) << 13) | ((amount & 7) << 10); + Bits Op = new Bits(Opcode); + + AThreadState ThreadState = SingleOpcode(Opcode, X1: Xn_SP, X2: Wm, X31: Xn_SP); + + AArch64.X((int)Rn, new Bits(Xn_SP)); + AArch64.X((int)Rm, new Bits(Wm)); + AArch64.SP(new Bits(Xn_SP)); + Base.Subs_Rx(Op[31], Op[20, 16], Op[15, 13], Op[12, 10], Op[9, 5], Op[4, 0]); + + if (Rd != 31) + { + ulong Xd = AArch64.X(64, (int)Rd).ToUInt64(); + + Assert.That((ulong)ThreadState.X0, Is.EqualTo(Xd)); + } + else + { + ulong _X31 = AArch64.SP(64).ToUInt64(); + + Assert.That((ulong)ThreadState.X31, Is.EqualTo(_X31)); + } + Assert.Multiple(() => + { + Assert.That(ThreadState.Negative, Is.EqualTo(Shared.PSTATE.N)); + Assert.That(ThreadState.Zero, Is.EqualTo(Shared.PSTATE.Z)); + Assert.That(ThreadState.Carry, Is.EqualTo(Shared.PSTATE.C)); + Assert.That(ThreadState.Overflow, Is.EqualTo(Shared.PSTATE.V)); + }); + } + + [Test, Description("SUBS , , {, {#}}")] + public void Subs_B_64bit([Values(0u, 31u)] uint Rd, + [Values(1u, 31u)] uint Rn, + [Values(2u, 31u)] uint Rm, + [Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul, + 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(1)] ulong Xn_SP, + [Values((byte)0x00, (byte)0x7F, + (byte)0x80, (byte)0xFF)] [Random(2)] byte Wm, + [Values(0b000u, 0b001u, 0b010u, // + [Values(0u, 1u, 2u, 3u, 4u)] uint amount) + { + uint Opcode = 0xEB200000; // SUBS X0, X0, W0, UXTB #0 + Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); + Opcode |= ((extend & 7) << 13) | ((amount & 7) << 10); + Bits Op = new Bits(Opcode); + + AThreadState ThreadState = SingleOpcode(Opcode, X1: Xn_SP, X2: Wm, X31: Xn_SP); + + AArch64.X((int)Rn, new Bits(Xn_SP)); + AArch64.X((int)Rm, new Bits(Wm)); + AArch64.SP(new Bits(Xn_SP)); + Base.Subs_Rx(Op[31], Op[20, 16], Op[15, 13], Op[12, 10], Op[9, 5], Op[4, 0]); + + if (Rd != 31) + { + ulong Xd = AArch64.X(64, (int)Rd).ToUInt64(); + + Assert.That((ulong)ThreadState.X0, Is.EqualTo(Xd)); + } + else + { + ulong _X31 = AArch64.SP(64).ToUInt64(); + + Assert.That((ulong)ThreadState.X31, Is.EqualTo(_X31)); + } + Assert.Multiple(() => + { + Assert.That(ThreadState.Negative, Is.EqualTo(Shared.PSTATE.N)); + Assert.That(ThreadState.Zero, Is.EqualTo(Shared.PSTATE.Z)); + Assert.That(ThreadState.Carry, Is.EqualTo(Shared.PSTATE.C)); + Assert.That(ThreadState.Overflow, Is.EqualTo(Shared.PSTATE.V)); + }); + } + + [Test, Description("SUBS , , {, {#}}")] + public void Subs_W_32bit([Values(0u, 31u)] uint Rd, + [Values(1u, 31u)] uint Rn, + [Values(2u, 31u)] uint Rm, + [Values(0x00000000u, 0x7FFFFFFFu, + 0x80000000u, 0xFFFFFFFFu)] [Random(1)] uint Wn_WSP, + [Values((uint)0x00000000, (uint)0x7FFFFFFF, + (uint)0x80000000, (uint)0xFFFFFFFF)] [Random(2)] uint Wm, + [Values(0b000u, 0b001u, 0b010u, 0b011u, // + [Values(0u, 1u, 2u, 3u, 4u)] uint amount) + { + uint Opcode = 0x6B200000; // SUBS W0, W0, W0, UXTB #0 + Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); + Opcode |= ((extend & 7) << 13) | ((amount & 7) << 10); + Bits Op = new Bits(Opcode); + + AThreadState ThreadState = SingleOpcode(Opcode, X1: Wn_WSP, X2: Wm, X31: Wn_WSP); + + AArch64.X((int)Rn, new Bits(Wn_WSP)); + AArch64.X((int)Rm, new Bits(Wm)); + AArch64.SP(new Bits(Wn_WSP)); + Base.Subs_Rx(Op[31], Op[20, 16], Op[15, 13], Op[12, 10], Op[9, 5], Op[4, 0]); + + if (Rd != 31) + { + uint Wd = AArch64.X(32, (int)Rd).ToUInt32(); + + Assert.That((uint)ThreadState.X0, Is.EqualTo(Wd)); + } + else + { + uint _W31 = AArch64.SP(32).ToUInt32(); + + Assert.That((uint)ThreadState.X31, Is.EqualTo(_W31)); + } + Assert.Multiple(() => + { + Assert.That(ThreadState.Negative, Is.EqualTo(Shared.PSTATE.N)); + Assert.That(ThreadState.Zero, Is.EqualTo(Shared.PSTATE.Z)); + Assert.That(ThreadState.Carry, Is.EqualTo(Shared.PSTATE.C)); + Assert.That(ThreadState.Overflow, Is.EqualTo(Shared.PSTATE.V)); + }); + } + + [Test, Description("SUBS , , {, {#}}")] + public void Subs_H_32bit([Values(0u, 31u)] uint Rd, + [Values(1u, 31u)] uint Rn, + [Values(2u, 31u)] uint Rm, + [Values(0x00000000u, 0x7FFFFFFFu, + 0x80000000u, 0xFFFFFFFFu)] [Random(1)] uint Wn_WSP, + [Values((ushort)0x0000, (ushort)0x7FFF, + (ushort)0x8000, (ushort)0xFFFF)] [Random(2)] ushort Wm, + [Values(0b000u, 0b001u, 0b010u, 0b011u, // + [Values(0u, 1u, 2u, 3u, 4u)] uint amount) + { + uint Opcode = 0x6B200000; // SUBS W0, W0, W0, UXTB #0 + Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); + Opcode |= ((extend & 7) << 13) | ((amount & 7) << 10); + Bits Op = new Bits(Opcode); + + AThreadState ThreadState = SingleOpcode(Opcode, X1: Wn_WSP, X2: Wm, X31: Wn_WSP); + + AArch64.X((int)Rn, new Bits(Wn_WSP)); + AArch64.X((int)Rm, new Bits(Wm)); + AArch64.SP(new Bits(Wn_WSP)); + Base.Subs_Rx(Op[31], Op[20, 16], Op[15, 13], Op[12, 10], Op[9, 5], Op[4, 0]); + + if (Rd != 31) + { + uint Wd = AArch64.X(32, (int)Rd).ToUInt32(); + + Assert.That((uint)ThreadState.X0, Is.EqualTo(Wd)); + } + else + { + uint _W31 = AArch64.SP(32).ToUInt32(); + + Assert.That((uint)ThreadState.X31, Is.EqualTo(_W31)); + } + Assert.Multiple(() => + { + Assert.That(ThreadState.Negative, Is.EqualTo(Shared.PSTATE.N)); + Assert.That(ThreadState.Zero, Is.EqualTo(Shared.PSTATE.Z)); + Assert.That(ThreadState.Carry, Is.EqualTo(Shared.PSTATE.C)); + Assert.That(ThreadState.Overflow, Is.EqualTo(Shared.PSTATE.V)); + }); + } + + [Test, Description("SUBS , , {, {#}}")] + public void Subs_B_32bit([Values(0u, 31u)] uint Rd, + [Values(1u, 31u)] uint Rn, + [Values(2u, 31u)] uint Rm, + [Values(0x00000000u, 0x7FFFFFFFu, + 0x80000000u, 0xFFFFFFFFu)] [Random(1)] uint Wn_WSP, + [Values((byte)0x00, (byte)0x7F, + (byte)0x80, (byte)0xFF)] [Random(2)] byte Wm, + [Values(0b000u, 0b001u, 0b010u, 0b011u, // + [Values(0u, 1u, 2u, 3u, 4u)] uint amount) + { + uint Opcode = 0x6B200000; // SUBS W0, W0, W0, UXTB #0 + Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); + Opcode |= ((extend & 7) << 13) | ((amount & 7) << 10); + Bits Op = new Bits(Opcode); + + AThreadState ThreadState = SingleOpcode(Opcode, X1: Wn_WSP, X2: Wm, X31: Wn_WSP); + + AArch64.X((int)Rn, new Bits(Wn_WSP)); + AArch64.X((int)Rm, new Bits(Wm)); + AArch64.SP(new Bits(Wn_WSP)); + Base.Subs_Rx(Op[31], Op[20, 16], Op[15, 13], Op[12, 10], Op[9, 5], Op[4, 0]); + + if (Rd != 31) + { + uint Wd = AArch64.X(32, (int)Rd).ToUInt32(); + + Assert.That((uint)ThreadState.X0, Is.EqualTo(Wd)); + } + else + { + uint _W31 = AArch64.SP(32).ToUInt32(); + + Assert.That((uint)ThreadState.X31, Is.EqualTo(_W31)); + } + Assert.Multiple(() => + { + Assert.That(ThreadState.Negative, Is.EqualTo(Shared.PSTATE.N)); + Assert.That(ThreadState.Zero, Is.EqualTo(Shared.PSTATE.Z)); + Assert.That(ThreadState.Carry, Is.EqualTo(Shared.PSTATE.C)); + Assert.That(ThreadState.Overflow, Is.EqualTo(Shared.PSTATE.V)); + }); + } +#endif + } +} diff --git a/Ryujinx.Tests/Cpu/CpuTestBfm.cs b/Ryujinx.Tests/Cpu/CpuTestBfm.cs new file mode 100644 index 000000000..2952bca4c --- /dev/null +++ b/Ryujinx.Tests/Cpu/CpuTestBfm.cs @@ -0,0 +1,213 @@ +//#define Bfm + +using ChocolArm64.State; + +using NUnit.Framework; + +namespace Ryujinx.Tests.Cpu +{ + using Tester; + using Tester.Types; + + [Category("Bfm"), Ignore("Tested: first half of 2018.")] + public sealed class CpuTestBfm : CpuTest + { +#if Bfm + [SetUp] + public void SetupTester() + { + AArch64.TakeReset(false); + } + + [Test, Description("BFM , , #, #")] + public void Bfm_64bit([Values(0u, 31u)] uint Rd, + [Values(1u, 31u)] uint Rn, + [Random(2)] ulong _Xd, + [Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul, + 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(2)] ulong Xn, + [Values(0u, 31u, 32u, 63u)] [Random(0u, 63u, 2)] uint immr, + [Values(0u, 31u, 32u, 63u)] [Random(0u, 63u, 2)] uint imms) + { + uint Opcode = 0xB3400000; // BFM X0, X0, #0, #0 + Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0); + Opcode |= ((immr & 63) << 16) | ((imms & 63) << 10); + + ulong _X31 = TestContext.CurrentContext.Random.NextULong(); + AThreadState ThreadState = SingleOpcode(Opcode, X0: _Xd, X1: Xn, X31: _X31); + + if (Rd != 31) + { + Bits Op = new Bits(Opcode); + + AArch64.X((int)Rd, new Bits(_Xd)); + AArch64.X((int)Rn, new Bits(Xn)); + Base.Bfm(Op[31], Op[22], Op[21, 16], Op[15, 10], Op[9, 5], Op[4, 0]); + ulong Xd = AArch64.X(64, (int)Rd).ToUInt64(); + + Assert.That((ulong)ThreadState.X0, Is.EqualTo(Xd)); + } + else + { + Assert.That((ulong)ThreadState.X31, Is.EqualTo(_X31)); + } + } + + [Test, Description("BFM , , #, #")] + public void Bfm_32bit([Values(0u, 31u)] uint Rd, + [Values(1u, 31u)] uint Rn, + [Random(2)] uint _Wd, + [Values(0x00000000u, 0x7FFFFFFFu, + 0x80000000u, 0xFFFFFFFFu)] [Random(2)] uint Wn, + [Values(0u, 15u, 16u, 31u)] [Random(0u, 31u, 2)] uint immr, + [Values(0u, 15u, 16u, 31u)] [Random(0u, 31u, 2)] uint imms) + { + uint Opcode = 0x33000000; // BFM W0, W0, #0, #0 + Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0); + Opcode |= ((immr & 63) << 16) | ((imms & 63) << 10); + + uint _W31 = TestContext.CurrentContext.Random.NextUInt(); + AThreadState ThreadState = SingleOpcode(Opcode, X0: _Wd, X1: Wn, X31: _W31); + + if (Rd != 31) + { + Bits Op = new Bits(Opcode); + + AArch64.X((int)Rd, new Bits(_Wd)); + AArch64.X((int)Rn, new Bits(Wn)); + Base.Bfm(Op[31], Op[22], Op[21, 16], Op[15, 10], Op[9, 5], Op[4, 0]); + uint Wd = AArch64.X(32, (int)Rd).ToUInt32(); + + Assert.That((uint)ThreadState.X0, Is.EqualTo(Wd)); + } + else + { + Assert.That((uint)ThreadState.X31, Is.EqualTo(_W31)); + } + } + + [Test, Description("SBFM , , #, #")] + public void Sbfm_64bit([Values(0u, 31u)] uint Rd, + [Values(1u, 31u)] uint Rn, + [Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul, + 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(2)] ulong Xn, + [Values(0u, 31u, 32u, 63u)] [Random(0u, 63u, 2)] uint immr, + [Values(0u, 31u, 32u, 63u)] [Random(0u, 63u, 2)] uint imms) + { + uint Opcode = 0x93400000; // SBFM X0, X0, #0, #0 + Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0); + Opcode |= ((immr & 63) << 16) | ((imms & 63) << 10); + + ulong _X31 = TestContext.CurrentContext.Random.NextULong(); + AThreadState ThreadState = SingleOpcode(Opcode, X1: Xn, X31: _X31); + + if (Rd != 31) + { + Bits Op = new Bits(Opcode); + + AArch64.X((int)Rn, new Bits(Xn)); + Base.Sbfm(Op[31], Op[22], Op[21, 16], Op[15, 10], Op[9, 5], Op[4, 0]); + ulong Xd = AArch64.X(64, (int)Rd).ToUInt64(); + + Assert.That((ulong)ThreadState.X0, Is.EqualTo(Xd)); + } + else + { + Assert.That((ulong)ThreadState.X31, Is.EqualTo(_X31)); + } + } + + [Test, Description("SBFM , , #, #")] + public void Sbfm_32bit([Values(0u, 31u)] uint Rd, + [Values(1u, 31u)] uint Rn, + [Values(0x00000000u, 0x7FFFFFFFu, + 0x80000000u, 0xFFFFFFFFu)] [Random(2)] uint Wn, + [Values(0u, 15u, 16u, 31u)] [Random(0u, 31u, 2)] uint immr, + [Values(0u, 15u, 16u, 31u)] [Random(0u, 31u, 2)] uint imms) + { + uint Opcode = 0x13000000; // SBFM W0, W0, #0, #0 + Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0); + Opcode |= ((immr & 63) << 16) | ((imms & 63) << 10); + + uint _W31 = TestContext.CurrentContext.Random.NextUInt(); + AThreadState ThreadState = SingleOpcode(Opcode, X1: Wn, X31: _W31); + + if (Rd != 31) + { + Bits Op = new Bits(Opcode); + + AArch64.X((int)Rn, new Bits(Wn)); + Base.Sbfm(Op[31], Op[22], Op[21, 16], Op[15, 10], Op[9, 5], Op[4, 0]); + uint Wd = AArch64.X(32, (int)Rd).ToUInt32(); + + Assert.That((uint)ThreadState.X0, Is.EqualTo(Wd)); + } + else + { + Assert.That((uint)ThreadState.X31, Is.EqualTo(_W31)); + } + } + + [Test, Description("UBFM , , #, #")] + public void Ubfm_64bit([Values(0u, 31u)] uint Rd, + [Values(1u, 31u)] uint Rn, + [Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul, + 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(2)] ulong Xn, + [Values(0u, 31u, 32u, 63u)] [Random(0u, 63u, 2)] uint immr, + [Values(0u, 31u, 32u, 63u)] [Random(0u, 63u, 2)] uint imms) + { + uint Opcode = 0xD3400000; // UBFM X0, X0, #0, #0 + Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0); + Opcode |= ((immr & 63) << 16) | ((imms & 63) << 10); + + ulong _X31 = TestContext.CurrentContext.Random.NextULong(); + AThreadState ThreadState = SingleOpcode(Opcode, X1: Xn, X31: _X31); + + if (Rd != 31) + { + Bits Op = new Bits(Opcode); + + AArch64.X((int)Rn, new Bits(Xn)); + Base.Ubfm(Op[31], Op[22], Op[21, 16], Op[15, 10], Op[9, 5], Op[4, 0]); + ulong Xd = AArch64.X(64, (int)Rd).ToUInt64(); + + Assert.That((ulong)ThreadState.X0, Is.EqualTo(Xd)); + } + else + { + Assert.That((ulong)ThreadState.X31, Is.EqualTo(_X31)); + } + } + + [Test, Description("UBFM , , #, #")] + public void Ubfm_32bit([Values(0u, 31u)] uint Rd, + [Values(1u, 31u)] uint Rn, + [Values(0x00000000u, 0x7FFFFFFFu, + 0x80000000u, 0xFFFFFFFFu)] [Random(2)] uint Wn, + [Values(0u, 15u, 16u, 31u)] [Random(0u, 31u, 2)] uint immr, + [Values(0u, 15u, 16u, 31u)] [Random(0u, 31u, 2)] uint imms) + { + uint Opcode = 0x53000000; // UBFM W0, W0, #0, #0 + Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0); + Opcode |= ((immr & 63) << 16) | ((imms & 63) << 10); + + uint _W31 = TestContext.CurrentContext.Random.NextUInt(); + AThreadState ThreadState = SingleOpcode(Opcode, X1: Wn, X31: _W31); + + if (Rd != 31) + { + Bits Op = new Bits(Opcode); + + AArch64.X((int)Rn, new Bits(Wn)); + Base.Ubfm(Op[31], Op[22], Op[21, 16], Op[15, 10], Op[9, 5], Op[4, 0]); + uint Wd = AArch64.X(32, (int)Rd).ToUInt32(); + + Assert.That((uint)ThreadState.X0, Is.EqualTo(Wd)); + } + else + { + Assert.That((uint)ThreadState.X31, Is.EqualTo(_W31)); + } + } +#endif + } +} diff --git a/Ryujinx.Tests/Cpu/CpuTestCcmpImm.cs b/Ryujinx.Tests/Cpu/CpuTestCcmpImm.cs new file mode 100644 index 000000000..38d73878a --- /dev/null +++ b/Ryujinx.Tests/Cpu/CpuTestCcmpImm.cs @@ -0,0 +1,151 @@ +//#define CcmpImm + +using ChocolArm64.State; + +using NUnit.Framework; + +namespace Ryujinx.Tests.Cpu +{ + using Tester; + using Tester.Types; + + [Category("CcmpImm"), Ignore("Tested: first half of 2018.")] + public sealed class CpuTestCcmpImm : CpuTest + { +#if CcmpImm + [SetUp] + public void SetupTester() + { + AArch64.TakeReset(false); + } + + [Test, Description("CCMN , #, #, ")] + public void Ccmn_64bit([Values(1u, 31u)] uint Rn, + [Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul, + 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(1)] ulong Xn, + [Values(0u, 31u)] [Random(0u, 31u, 3)] uint imm, + [Random(0u, 15u, 1)] uint nzcv, + [Values(0b0000u, 0b0001u, 0b0010u, 0b0011u, // + { + uint Opcode = 0xBA400800; // CCMN X0, #0, #0, EQ + Opcode |= ((Rn & 31) << 5); + Opcode |= ((imm & 31) << 16) | ((cond & 15) << 12) | ((nzcv & 15) << 0); + + ulong _X31 = TestContext.CurrentContext.Random.NextULong(); + AThreadState ThreadState = SingleOpcode(Opcode, X1: Xn, X31: _X31); + + Bits Op = new Bits(Opcode); + + AArch64.X((int)Rn, new Bits(Xn)); + Base.Ccmn_Imm(Op[31], Op[20, 16], Op[15, 12], Op[9, 5], Op[3, 0]); + + Assert.Multiple(() => + { + Assert.That(ThreadState.Negative, Is.EqualTo(Shared.PSTATE.N)); + Assert.That(ThreadState.Zero, Is.EqualTo(Shared.PSTATE.Z)); + Assert.That(ThreadState.Carry, Is.EqualTo(Shared.PSTATE.C)); + Assert.That(ThreadState.Overflow, Is.EqualTo(Shared.PSTATE.V)); + }); + } + + [Test, Description("CCMN , #, #, ")] + public void Ccmn_32bit([Values(1u, 31u)] uint Rn, + [Values(0x00000000u, 0x7FFFFFFFu, + 0x80000000u, 0xFFFFFFFFu)] [Random(1)] uint Wn, + [Values(0u, 31u)] [Random(0u, 31u, 3)] uint imm, + [Random(0u, 15u, 1)] uint nzcv, + [Values(0b0000u, 0b0001u, 0b0010u, 0b0011u, // + { + uint Opcode = 0x3A400800; // CCMN W0, #0, #0, EQ + Opcode |= ((Rn & 31) << 5); + Opcode |= ((imm & 31) << 16) | ((cond & 15) << 12) | ((nzcv & 15) << 0); + + uint _W31 = TestContext.CurrentContext.Random.NextUInt(); + AThreadState ThreadState = SingleOpcode(Opcode, X1: Wn, X31: _W31); + + Bits Op = new Bits(Opcode); + + AArch64.X((int)Rn, new Bits(Wn)); + Base.Ccmn_Imm(Op[31], Op[20, 16], Op[15, 12], Op[9, 5], Op[3, 0]); + + Assert.Multiple(() => + { + Assert.That(ThreadState.Negative, Is.EqualTo(Shared.PSTATE.N)); + Assert.That(ThreadState.Zero, Is.EqualTo(Shared.PSTATE.Z)); + Assert.That(ThreadState.Carry, Is.EqualTo(Shared.PSTATE.C)); + Assert.That(ThreadState.Overflow, Is.EqualTo(Shared.PSTATE.V)); + }); + } + + [Test, Description("CCMP , #, #, ")] + public void Ccmp_64bit([Values(1u, 31u)] uint Rn, + [Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul, + 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(1)] ulong Xn, + [Values(0u, 31u)] [Random(0u, 31u, 3)] uint imm, + [Random(0u, 15u, 1)] uint nzcv, + [Values(0b0000u, 0b0001u, 0b0010u, 0b0011u, // + { + uint Opcode = 0xFA400800; // CCMP X0, #0, #0, EQ + Opcode |= ((Rn & 31) << 5); + Opcode |= ((imm & 31) << 16) | ((cond & 15) << 12) | ((nzcv & 15) << 0); + + ulong _X31 = TestContext.CurrentContext.Random.NextULong(); + AThreadState ThreadState = SingleOpcode(Opcode, X1: Xn, X31: _X31); + + Bits Op = new Bits(Opcode); + + AArch64.X((int)Rn, new Bits(Xn)); + Base.Ccmp_Imm(Op[31], Op[20, 16], Op[15, 12], Op[9, 5], Op[3, 0]); + + Assert.Multiple(() => + { + Assert.That(ThreadState.Negative, Is.EqualTo(Shared.PSTATE.N)); + Assert.That(ThreadState.Zero, Is.EqualTo(Shared.PSTATE.Z)); + Assert.That(ThreadState.Carry, Is.EqualTo(Shared.PSTATE.C)); + Assert.That(ThreadState.Overflow, Is.EqualTo(Shared.PSTATE.V)); + }); + } + + [Test, Description("CCMP , #, #, ")] + public void Ccmp_32bit([Values(1u, 31u)] uint Rn, + [Values(0x00000000u, 0x7FFFFFFFu, + 0x80000000u, 0xFFFFFFFFu)] [Random(1)] uint Wn, + [Values(0u, 31u)] [Random(0u, 31u, 3)] uint imm, + [Random(0u, 15u, 1)] uint nzcv, + [Values(0b0000u, 0b0001u, 0b0010u, 0b0011u, // + { + uint Opcode = 0x7A400800; // CCMP W0, #0, #0, EQ + Opcode |= ((Rn & 31) << 5); + Opcode |= ((imm & 31) << 16) | ((cond & 15) << 12) | ((nzcv & 15) << 0); + + uint _W31 = TestContext.CurrentContext.Random.NextUInt(); + AThreadState ThreadState = SingleOpcode(Opcode, X1: Wn, X31: _W31); + + Bits Op = new Bits(Opcode); + + AArch64.X((int)Rn, new Bits(Wn)); + Base.Ccmp_Imm(Op[31], Op[20, 16], Op[15, 12], Op[9, 5], Op[3, 0]); + + Assert.Multiple(() => + { + Assert.That(ThreadState.Negative, Is.EqualTo(Shared.PSTATE.N)); + Assert.That(ThreadState.Zero, Is.EqualTo(Shared.PSTATE.Z)); + Assert.That(ThreadState.Carry, Is.EqualTo(Shared.PSTATE.C)); + Assert.That(ThreadState.Overflow, Is.EqualTo(Shared.PSTATE.V)); + }); + } +#endif + } +} diff --git a/Ryujinx.Tests/Cpu/CpuTestCcmpReg.cs b/Ryujinx.Tests/Cpu/CpuTestCcmpReg.cs new file mode 100644 index 000000000..eb1c3abf2 --- /dev/null +++ b/Ryujinx.Tests/Cpu/CpuTestCcmpReg.cs @@ -0,0 +1,163 @@ +//#define CcmpReg + +using ChocolArm64.State; + +using NUnit.Framework; + +namespace Ryujinx.Tests.Cpu +{ + using Tester; + using Tester.Types; + + [Category("CcmpReg"), Ignore("Tested: first half of 2018.")] + public sealed class CpuTestCcmpReg : CpuTest + { +#if CcmpReg + [SetUp] + public void SetupTester() + { + AArch64.TakeReset(false); + } + + [Test, Description("CCMN , , #, ")] + public void Ccmn_64bit([Values(1u, 31u)] uint Rn, + [Values(2u, 31u)] uint Rm, + [Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul, + 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(1)] ulong Xn, + [Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul, + 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(1)] ulong Xm, + [Random(0u, 15u, 1)] uint nzcv, + [Values(0b0000u, 0b0001u, 0b0010u, 0b0011u, // + { + uint Opcode = 0xBA400000; // CCMN X0, X0, #0, EQ + Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5); + Opcode |= ((cond & 15) << 12) | ((nzcv & 15) << 0); + + ulong _X31 = TestContext.CurrentContext.Random.NextULong(); + AThreadState ThreadState = SingleOpcode(Opcode, X1: Xn, X2: Xm, X31: _X31); + + Bits Op = new Bits(Opcode); + + AArch64.X((int)Rn, new Bits(Xn)); + AArch64.X((int)Rm, new Bits(Xm)); + Base.Ccmn_Reg(Op[31], Op[20, 16], Op[15, 12], Op[9, 5], Op[3, 0]); + + Assert.Multiple(() => + { + Assert.That(ThreadState.Negative, Is.EqualTo(Shared.PSTATE.N)); + Assert.That(ThreadState.Zero, Is.EqualTo(Shared.PSTATE.Z)); + Assert.That(ThreadState.Carry, Is.EqualTo(Shared.PSTATE.C)); + Assert.That(ThreadState.Overflow, Is.EqualTo(Shared.PSTATE.V)); + }); + } + + [Test, Description("CCMN , , #, ")] + public void Ccmn_32bit([Values(1u, 31u)] uint Rn, + [Values(2u, 31u)] uint Rm, + [Values(0x00000000u, 0x7FFFFFFFu, + 0x80000000u, 0xFFFFFFFFu)] [Random(1)] uint Wn, + [Values(0x00000000u, 0x7FFFFFFFu, + 0x80000000u, 0xFFFFFFFFu)] [Random(1)] uint Wm, + [Random(0u, 15u, 1)] uint nzcv, + [Values(0b0000u, 0b0001u, 0b0010u, 0b0011u, // + { + uint Opcode = 0x3A400000; // CCMN W0, W0, #0, EQ + Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5); + Opcode |= ((cond & 15) << 12) | ((nzcv & 15) << 0); + + uint _W31 = TestContext.CurrentContext.Random.NextUInt(); + AThreadState ThreadState = SingleOpcode(Opcode, X1: Wn, X2: Wm, X31: _W31); + + Bits Op = new Bits(Opcode); + + AArch64.X((int)Rn, new Bits(Wn)); + AArch64.X((int)Rm, new Bits(Wm)); + Base.Ccmn_Reg(Op[31], Op[20, 16], Op[15, 12], Op[9, 5], Op[3, 0]); + + Assert.Multiple(() => + { + Assert.That(ThreadState.Negative, Is.EqualTo(Shared.PSTATE.N)); + Assert.That(ThreadState.Zero, Is.EqualTo(Shared.PSTATE.Z)); + Assert.That(ThreadState.Carry, Is.EqualTo(Shared.PSTATE.C)); + Assert.That(ThreadState.Overflow, Is.EqualTo(Shared.PSTATE.V)); + }); + } + + [Test, Description("CCMP , , #, ")] + public void Ccmp_64bit([Values(1u, 31u)] uint Rn, + [Values(2u, 31u)] uint Rm, + [Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul, + 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(1)] ulong Xn, + [Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul, + 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(1)] ulong Xm, + [Random(0u, 15u, 1)] uint nzcv, + [Values(0b0000u, 0b0001u, 0b0010u, 0b0011u, // + { + uint Opcode = 0xFA400000; // CCMP X0, X0, #0, EQ + Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5); + Opcode |= ((cond & 15) << 12) | ((nzcv & 15) << 0); + + ulong _X31 = TestContext.CurrentContext.Random.NextULong(); + AThreadState ThreadState = SingleOpcode(Opcode, X1: Xn, X2: Xm, X31: _X31); + + Bits Op = new Bits(Opcode); + + AArch64.X((int)Rn, new Bits(Xn)); + AArch64.X((int)Rm, new Bits(Xm)); + Base.Ccmp_Reg(Op[31], Op[20, 16], Op[15, 12], Op[9, 5], Op[3, 0]); + + Assert.Multiple(() => + { + Assert.That(ThreadState.Negative, Is.EqualTo(Shared.PSTATE.N)); + Assert.That(ThreadState.Zero, Is.EqualTo(Shared.PSTATE.Z)); + Assert.That(ThreadState.Carry, Is.EqualTo(Shared.PSTATE.C)); + Assert.That(ThreadState.Overflow, Is.EqualTo(Shared.PSTATE.V)); + }); + } + + [Test, Description("CCMP , , #, ")] + public void Ccmp_32bit([Values(1u, 31u)] uint Rn, + [Values(2u, 31u)] uint Rm, + [Values(0x00000000u, 0x7FFFFFFFu, + 0x80000000u, 0xFFFFFFFFu)] [Random(1)] uint Wn, + [Values(0x00000000u, 0x7FFFFFFFu, + 0x80000000u, 0xFFFFFFFFu)] [Random(1)] uint Wm, + [Random(0u, 15u, 1)] uint nzcv, + [Values(0b0000u, 0b0001u, 0b0010u, 0b0011u, // + { + uint Opcode = 0x7A400000; // CCMP W0, W0, #0, EQ + Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5); + Opcode |= ((cond & 15) << 12) | ((nzcv & 15) << 0); + + uint _W31 = TestContext.CurrentContext.Random.NextUInt(); + AThreadState ThreadState = SingleOpcode(Opcode, X1: Wn, X2: Wm, X31: _W31); + + Bits Op = new Bits(Opcode); + + AArch64.X((int)Rn, new Bits(Wn)); + AArch64.X((int)Rm, new Bits(Wm)); + Base.Ccmp_Reg(Op[31], Op[20, 16], Op[15, 12], Op[9, 5], Op[3, 0]); + + Assert.Multiple(() => + { + Assert.That(ThreadState.Negative, Is.EqualTo(Shared.PSTATE.N)); + Assert.That(ThreadState.Zero, Is.EqualTo(Shared.PSTATE.Z)); + Assert.That(ThreadState.Carry, Is.EqualTo(Shared.PSTATE.C)); + Assert.That(ThreadState.Overflow, Is.EqualTo(Shared.PSTATE.V)); + }); + } +#endif + } +} diff --git a/Ryujinx.Tests/Cpu/CpuTestCsel.cs b/Ryujinx.Tests/Cpu/CpuTestCsel.cs new file mode 100644 index 000000000..9dd61957f --- /dev/null +++ b/Ryujinx.Tests/Cpu/CpuTestCsel.cs @@ -0,0 +1,319 @@ +//#define Csel + +using ChocolArm64.State; + +using NUnit.Framework; + +namespace Ryujinx.Tests.Cpu +{ + using Tester; + using Tester.Types; + + [Category("Csel"), Ignore("Tested: first half of 2018.")] + public sealed class CpuTestCsel : CpuTest + { +#if Csel + [SetUp] + public void SetupTester() + { + AArch64.TakeReset(false); + } + + [Test, Description("CSEL , , , ")] + public void Csel_64bit([Values(0u, 31u)] uint Rd, + [Values(1u, 31u)] uint Rn, + [Values(2u, 31u)] uint Rm, + [Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul, + 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(1)] ulong Xn, + [Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul, + 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(1)] ulong Xm, + [Values(0b0000u, 0b0001u, 0b0010u, 0b0011u, // + { + uint Opcode = 0x9A800000; // CSEL X0, X0, X0, EQ + Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); + Opcode |= ((cond & 15) << 12); + + ulong _X31 = TestContext.CurrentContext.Random.NextULong(); + AThreadState ThreadState = SingleOpcode(Opcode, X1: Xn, X2: Xm, X31: _X31); + + if (Rd != 31) + { + Bits Op = new Bits(Opcode); + + AArch64.X((int)Rn, new Bits(Xn)); + AArch64.X((int)Rm, new Bits(Xm)); + Base.Csel(Op[31], Op[20, 16], Op[15, 12], Op[9, 5], Op[4, 0]); + ulong Xd = AArch64.X(64, (int)Rd).ToUInt64(); + + Assert.That((ulong)ThreadState.X0, Is.EqualTo(Xd)); + } + else + { + Assert.That((ulong)ThreadState.X31, Is.EqualTo(_X31)); + } + } + + [Test, Description("CSEL , , , ")] + public void Csel_32bit([Values(0u, 31u)] uint Rd, + [Values(1u, 31u)] uint Rn, + [Values(2u, 31u)] uint Rm, + [Values(0x00000000u, 0x7FFFFFFFu, + 0x80000000u, 0xFFFFFFFFu)] [Random(1)] uint Wn, + [Values(0x00000000u, 0x7FFFFFFFu, + 0x80000000u, 0xFFFFFFFFu)] [Random(1)] uint Wm, + [Values(0b0000u, 0b0001u, 0b0010u, 0b0011u, // + { + uint Opcode = 0x1A800000; // CSEL W0, W0, W0, EQ + Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); + Opcode |= ((cond & 15) << 12); + + uint _W31 = TestContext.CurrentContext.Random.NextUInt(); + AThreadState ThreadState = SingleOpcode(Opcode, X1: Wn, X2: Wm, X31: _W31); + + if (Rd != 31) + { + Bits Op = new Bits(Opcode); + + AArch64.X((int)Rn, new Bits(Wn)); + AArch64.X((int)Rm, new Bits(Wm)); + Base.Csel(Op[31], Op[20, 16], Op[15, 12], Op[9, 5], Op[4, 0]); + uint Wd = AArch64.X(32, (int)Rd).ToUInt32(); + + Assert.That((uint)ThreadState.X0, Is.EqualTo(Wd)); + } + else + { + Assert.That((uint)ThreadState.X31, Is.EqualTo(_W31)); + } + } + + [Test, Description("CSINC , , , ")] + public void Csinc_64bit([Values(0u, 31u)] uint Rd, + [Values(1u, 31u)] uint Rn, + [Values(2u, 31u)] uint Rm, + [Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul, + 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(1)] ulong Xn, + [Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul, + 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(1)] ulong Xm, + [Values(0b0000u, 0b0001u, 0b0010u, 0b0011u, // + { + uint Opcode = 0x9A800400; // CSINC X0, X0, X0, EQ + Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); + Opcode |= ((cond & 15) << 12); + + ulong _X31 = TestContext.CurrentContext.Random.NextULong(); + AThreadState ThreadState = SingleOpcode(Opcode, X1: Xn, X2: Xm, X31: _X31); + + if (Rd != 31) + { + Bits Op = new Bits(Opcode); + + AArch64.X((int)Rn, new Bits(Xn)); + AArch64.X((int)Rm, new Bits(Xm)); + Base.Csinc(Op[31], Op[20, 16], Op[15, 12], Op[9, 5], Op[4, 0]); + ulong Xd = AArch64.X(64, (int)Rd).ToUInt64(); + + Assert.That((ulong)ThreadState.X0, Is.EqualTo(Xd)); + } + else + { + Assert.That((ulong)ThreadState.X31, Is.EqualTo(_X31)); + } + } + + [Test, Description("CSINC , , , ")] + public void Csinc_32bit([Values(0u, 31u)] uint Rd, + [Values(1u, 31u)] uint Rn, + [Values(2u, 31u)] uint Rm, + [Values(0x00000000u, 0x7FFFFFFFu, + 0x80000000u, 0xFFFFFFFFu)] [Random(1)] uint Wn, + [Values(0x00000000u, 0x7FFFFFFFu, + 0x80000000u, 0xFFFFFFFFu)] [Random(1)] uint Wm, + [Values(0b0000u, 0b0001u, 0b0010u, 0b0011u, // + { + uint Opcode = 0x1A800400; // CSINC W0, W0, W0, EQ + Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); + Opcode |= ((cond & 15) << 12); + + uint _W31 = TestContext.CurrentContext.Random.NextUInt(); + AThreadState ThreadState = SingleOpcode(Opcode, X1: Wn, X2: Wm, X31: _W31); + + if (Rd != 31) + { + Bits Op = new Bits(Opcode); + + AArch64.X((int)Rn, new Bits(Wn)); + AArch64.X((int)Rm, new Bits(Wm)); + Base.Csinc(Op[31], Op[20, 16], Op[15, 12], Op[9, 5], Op[4, 0]); + uint Wd = AArch64.X(32, (int)Rd).ToUInt32(); + + Assert.That((uint)ThreadState.X0, Is.EqualTo(Wd)); + } + else + { + Assert.That((uint)ThreadState.X31, Is.EqualTo(_W31)); + } + } + + [Test, Description("CSINV , , , ")] + public void Csinv_64bit([Values(0u, 31u)] uint Rd, + [Values(1u, 31u)] uint Rn, + [Values(2u, 31u)] uint Rm, + [Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul, + 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(1)] ulong Xn, + [Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul, + 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(1)] ulong Xm, + [Values(0b0000u, 0b0001u, 0b0010u, 0b0011u, // + { + uint Opcode = 0xDA800000; // CSINV X0, X0, X0, EQ + Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); + Opcode |= ((cond & 15) << 12); + + ulong _X31 = TestContext.CurrentContext.Random.NextULong(); + AThreadState ThreadState = SingleOpcode(Opcode, X1: Xn, X2: Xm, X31: _X31); + + if (Rd != 31) + { + Bits Op = new Bits(Opcode); + + AArch64.X((int)Rn, new Bits(Xn)); + AArch64.X((int)Rm, new Bits(Xm)); + Base.Csinv(Op[31], Op[20, 16], Op[15, 12], Op[9, 5], Op[4, 0]); + ulong Xd = AArch64.X(64, (int)Rd).ToUInt64(); + + Assert.That((ulong)ThreadState.X0, Is.EqualTo(Xd)); + } + else + { + Assert.That((ulong)ThreadState.X31, Is.EqualTo(_X31)); + } + } + + [Test, Description("CSINV , , , ")] + public void Csinv_32bit([Values(0u, 31u)] uint Rd, + [Values(1u, 31u)] uint Rn, + [Values(2u, 31u)] uint Rm, + [Values(0x00000000u, 0x7FFFFFFFu, + 0x80000000u, 0xFFFFFFFFu)] [Random(1)] uint Wn, + [Values(0x00000000u, 0x7FFFFFFFu, + 0x80000000u, 0xFFFFFFFFu)] [Random(1)] uint Wm, + [Values(0b0000u, 0b0001u, 0b0010u, 0b0011u, // + { + uint Opcode = 0x5A800000; // CSINV W0, W0, W0, EQ + Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); + Opcode |= ((cond & 15) << 12); + + uint _W31 = TestContext.CurrentContext.Random.NextUInt(); + AThreadState ThreadState = SingleOpcode(Opcode, X1: Wn, X2: Wm, X31: _W31); + + if (Rd != 31) + { + Bits Op = new Bits(Opcode); + + AArch64.X((int)Rn, new Bits(Wn)); + AArch64.X((int)Rm, new Bits(Wm)); + Base.Csinv(Op[31], Op[20, 16], Op[15, 12], Op[9, 5], Op[4, 0]); + uint Wd = AArch64.X(32, (int)Rd).ToUInt32(); + + Assert.That((uint)ThreadState.X0, Is.EqualTo(Wd)); + } + else + { + Assert.That((uint)ThreadState.X31, Is.EqualTo(_W31)); + } + } + + [Test, Description("CSNEG , , , ")] + public void Csneg_64bit([Values(0u, 31u)] uint Rd, + [Values(1u, 31u)] uint Rn, + [Values(2u, 31u)] uint Rm, + [Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul, + 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(1)] ulong Xn, + [Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul, + 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(1)] ulong Xm, + [Values(0b0000u, 0b0001u, 0b0010u, 0b0011u, // + { + uint Opcode = 0xDA800400; // CSNEG X0, X0, X0, EQ + Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); + Opcode |= ((cond & 15) << 12); + + ulong _X31 = TestContext.CurrentContext.Random.NextULong(); + AThreadState ThreadState = SingleOpcode(Opcode, X1: Xn, X2: Xm, X31: _X31); + + if (Rd != 31) + { + Bits Op = new Bits(Opcode); + + AArch64.X((int)Rn, new Bits(Xn)); + AArch64.X((int)Rm, new Bits(Xm)); + Base.Csneg(Op[31], Op[20, 16], Op[15, 12], Op[9, 5], Op[4, 0]); + ulong Xd = AArch64.X(64, (int)Rd).ToUInt64(); + + Assert.That((ulong)ThreadState.X0, Is.EqualTo(Xd)); + } + else + { + Assert.That((ulong)ThreadState.X31, Is.EqualTo(_X31)); + } + } + + [Test, Description("CSNEG , , , ")] + public void Csneg_32bit([Values(0u, 31u)] uint Rd, + [Values(1u, 31u)] uint Rn, + [Values(2u, 31u)] uint Rm, + [Values(0x00000000u, 0x7FFFFFFFu, + 0x80000000u, 0xFFFFFFFFu)] [Random(1)] uint Wn, + [Values(0x00000000u, 0x7FFFFFFFu, + 0x80000000u, 0xFFFFFFFFu)] [Random(1)] uint Wm, + [Values(0b0000u, 0b0001u, 0b0010u, 0b0011u, // + { + uint Opcode = 0x5A800400; // CSNEG W0, W0, W0, EQ + Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); + Opcode |= ((cond & 15) << 12); + + uint _W31 = TestContext.CurrentContext.Random.NextUInt(); + AThreadState ThreadState = SingleOpcode(Opcode, X1: Wn, X2: Wm, X31: _W31); + + if (Rd != 31) + { + Bits Op = new Bits(Opcode); + + AArch64.X((int)Rn, new Bits(Wn)); + AArch64.X((int)Rm, new Bits(Wm)); + Base.Csneg(Op[31], Op[20, 16], Op[15, 12], Op[9, 5], Op[4, 0]); + uint Wd = AArch64.X(32, (int)Rd).ToUInt32(); + + Assert.That((uint)ThreadState.X0, Is.EqualTo(Wd)); + } + else + { + Assert.That((uint)ThreadState.X31, Is.EqualTo(_W31)); + } + } +#endif + } +} diff --git a/Ryujinx.Tests/Cpu/CpuTestMisc.cs b/Ryujinx.Tests/Cpu/CpuTestMisc.cs index 3a995fe26..647d46c00 100644 --- a/Ryujinx.Tests/Cpu/CpuTestMisc.cs +++ b/Ryujinx.Tests/Cpu/CpuTestMisc.cs @@ -1,22 +1,12 @@ using ChocolArm64.State; + using NUnit.Framework; namespace Ryujinx.Tests.Cpu { - public class CpuTestMisc : CpuTest + [Category("Misc"), Explicit] + public sealed class CpuTestMisc : CpuTest { - [TestCase(0ul)] - [TestCase(1ul)] - [TestCase(2ul)] - [TestCase(42ul)] - public void SanityCheck(ulong A) - { - // NOP - uint Opcode = 0xD503201F; - AThreadState ThreadState = SingleOpcode(Opcode, X0: A); - Assert.AreEqual(A, ThreadState.X0); - } - [TestCase(0xFFFFFFFDu)] // Roots. [TestCase(0x00000005u)] public void Misc1(uint A) @@ -46,27 +36,28 @@ namespace Ryujinx.Tests.Cpu Opcode(0xD4200000); Opcode(0xD65F03C0); ExecuteOpcodes(); - Assert.AreEqual(0, GetThreadState().X0); + + Assert.That(GetThreadState().X0, Is.Zero); } - [TestCase(-20f, -5f)] // 18 integer solutions. - [TestCase(-12f, -6f)] - [TestCase(-12f, 3f)] - [TestCase(-8f, -8f)] - [TestCase(-6f, -12f)] - [TestCase(-5f, -20f)] - [TestCase(-4f, 2f)] - [TestCase(-3f, 12f)] - [TestCase(-2f, 4f)] - [TestCase(2f, -4f)] - [TestCase(3f, -12f)] - [TestCase(4f, -2f)] - [TestCase(5f, 20f)] - [TestCase(6f, 12f)] - [TestCase(8f, 8f)] - [TestCase(12f, -3f)] - [TestCase(12f, 6f)] - [TestCase(20f, 5f)] + [TestCase(-20f, -5f)] // 18 integer solutions. + [TestCase(-12f, -6f)] + [TestCase(-12f, 3f)] + [TestCase( -8f, -8f)] + [TestCase( -6f, -12f)] + [TestCase( -5f, -20f)] + [TestCase( -4f, 2f)] + [TestCase( -3f, 12f)] + [TestCase( -2f, 4f)] + [TestCase( 2f, -4f)] + [TestCase( 3f, -12f)] + [TestCase( 4f, -2f)] + [TestCase( 5f, 20f)] + [TestCase( 6f, 12f)] + [TestCase( 8f, 8f)] + [TestCase( 12f, -3f)] + [TestCase( 12f, 6f)] + [TestCase( 20f, 5f)] public void Misc2(float A, float B) { // 1 / ((1 / A + 1 / B) ^ 2) = 16 @@ -92,27 +83,28 @@ namespace Ryujinx.Tests.Cpu Opcode(0xD4200000); Opcode(0xD65F03C0); ExecuteOpcodes(); - Assert.AreEqual(16f, GetThreadState().V0.S0); + + Assert.That(GetThreadState().V0.S0, Is.EqualTo(16f)); } - [TestCase(-20d, -5d)] // 18 integer solutions. - [TestCase(-12d, -6d)] - [TestCase(-12d, 3d)] - [TestCase(-8d, -8d)] - [TestCase(-6d, -12d)] - [TestCase(-5d, -20d)] - [TestCase(-4d, 2d)] - [TestCase(-3d, 12d)] - [TestCase(-2d, 4d)] - [TestCase(2d, -4d)] - [TestCase(3d, -12d)] - [TestCase(4d, -2d)] - [TestCase(5d, 20d)] - [TestCase(6d, 12d)] - [TestCase(8d, 8d)] - [TestCase(12d, -3d)] - [TestCase(12d, 6d)] - [TestCase(20d, 5d)] + [TestCase(-20d, -5d)] // 18 integer solutions. + [TestCase(-12d, -6d)] + [TestCase(-12d, 3d)] + [TestCase( -8d, -8d)] + [TestCase( -6d, -12d)] + [TestCase( -5d, -20d)] + [TestCase( -4d, 2d)] + [TestCase( -3d, 12d)] + [TestCase( -2d, 4d)] + [TestCase( 2d, -4d)] + [TestCase( 3d, -12d)] + [TestCase( 4d, -2d)] + [TestCase( 5d, 20d)] + [TestCase( 6d, 12d)] + [TestCase( 8d, 8d)] + [TestCase( 12d, -3d)] + [TestCase( 12d, 6d)] + [TestCase( 20d, 5d)] public void Misc3(double A, double B) { // 1 / ((1 / A + 1 / B) ^ 2) = 16 @@ -138,74 +130,12 @@ namespace Ryujinx.Tests.Cpu Opcode(0xD4200000); Opcode(0xD65F03C0); ExecuteOpcodes(); - Assert.AreEqual(16d, GetThreadState().V0.D0); + + Assert.That(GetThreadState().V0.D0, Is.EqualTo(16d)); } [Test] - public void MiscR() - { - ulong Result = 5; - - /* - 0x0000000000000000: MOV X0, #2 - 0x0000000000000004: MOV X1, #3 - 0x0000000000000008: ADD X0, X0, X1 - 0x000000000000000C: BRK #0 - 0x0000000000000010: RET - */ - - Opcode(0xD2800040); - Opcode(0xD2800061); - Opcode(0x8B010000); - Opcode(0xD4200000); - Opcode(0xD65F03C0); - ExecuteOpcodes(); - Assert.AreEqual(Result, GetThreadState().X0); - - Reset(); - - /* - 0x0000000000000000: MOV X0, #3 - 0x0000000000000004: MOV X1, #2 - 0x0000000000000008: ADD X0, X0, X1 - 0x000000000000000C: BRK #0 - 0x0000000000000010: RET - */ - - Opcode(0xD2800060); - Opcode(0xD2800041); - Opcode(0x8B010000); - Opcode(0xD4200000); - Opcode(0xD65F03C0); - ExecuteOpcodes(); - Assert.AreEqual(Result, GetThreadState().X0); - } - - [Test, Explicit] - public void Misc5() - { - /* - 0x0000000000000000: SUBS X0, X0, #1 - 0x0000000000000004: B.NE #0 - 0x0000000000000008: BRK #0 - 0x000000000000000C: RET - */ - - SetThreadState(X0: 0x100000000); - Opcode(0xF1000400); - Opcode(0x54FFFFE1); - Opcode(0xD4200000); - Opcode(0xD65F03C0); - ExecuteOpcodes(); - Assert.Multiple(() => - { - Assert.AreEqual(0, GetThreadState().X0); - Assert.IsTrue(GetThreadState().Zero); - }); - } - - [Test] - public void MiscF([Range(0, 92, 1)] int A) + public void MiscF([Range(0u, 92u, 1u)] uint A) { ulong F_n(uint n) { @@ -250,7 +180,7 @@ namespace Ryujinx.Tests.Cpu 0x0000000000000050: RET */ - SetThreadState(X0: (uint)A); + SetThreadState(X0: A); Opcode(0x2A0003E4); Opcode(0x340001C0); Opcode(0x7100041F); @@ -273,7 +203,62 @@ namespace Ryujinx.Tests.Cpu Opcode(0xD4200000); Opcode(0xD65F03C0); ExecuteOpcodes(); - Assert.AreEqual(F_n((uint)A), GetThreadState().X0); + + Assert.That(GetThreadState().X0, Is.EqualTo(F_n(A))); + } + + [Test] + public void MiscR() + { + const ulong Result = 5; + + /* + 0x0000000000000000: MOV X0, #2 + 0x0000000000000004: MOV X1, #3 + 0x0000000000000008: ADD X0, X0, X1 + 0x000000000000000C: BRK #0 + 0x0000000000000010: RET + */ + + Opcode(0xD2800040); + Opcode(0xD2800061); + Opcode(0x8B010000); + Opcode(0xD4200000); + Opcode(0xD65F03C0); + ExecuteOpcodes(); + + Assert.That(GetThreadState().X0, Is.EqualTo(Result)); + + Reset(); + + /* + 0x0000000000000000: MOV X0, #3 + 0x0000000000000004: MOV X1, #2 + 0x0000000000000008: ADD X0, X0, X1 + 0x000000000000000C: BRK #0 + 0x0000000000000010: RET + */ + + Opcode(0xD2800060); + Opcode(0xD2800041); + Opcode(0x8B010000); + Opcode(0xD4200000); + Opcode(0xD65F03C0); + ExecuteOpcodes(); + + Assert.That(GetThreadState().X0, Is.EqualTo(Result)); + } + + [TestCase( 0ul)] + [TestCase( 1ul)] + [TestCase( 2ul)] + [TestCase(42ul)] + public void SanityCheck(ulong A) + { + uint Opcode = 0xD503201F; // NOP + AThreadState ThreadState = SingleOpcode(Opcode, X0: A); + + Assert.That(ThreadState.X0, Is.EqualTo(A)); } } } diff --git a/Ryujinx.Tests/Cpu/CpuTestMov.cs b/Ryujinx.Tests/Cpu/CpuTestMov.cs new file mode 100644 index 000000000..9c7e3255a --- /dev/null +++ b/Ryujinx.Tests/Cpu/CpuTestMov.cs @@ -0,0 +1,189 @@ +//#define Mov + +using ChocolArm64.State; + +using NUnit.Framework; + +namespace Ryujinx.Tests.Cpu +{ + using Tester; + using Tester.Types; + + [Category("Mov"), Ignore("Tested: first half of 2018.")] + public sealed class CpuTestMov : CpuTest + { +#if Mov + [SetUp] + public void SetupTester() + { + AArch64.TakeReset(false); + } + + [Test, Description("MOVK , #{, LSL #}")] + public void Movk_64bit([Values(0u, 31u)] uint Rd, + [Random(12)] ulong _Xd, + [Values(0u, 65535u)] [Random(0u, 65535u, 10)] uint imm, + [Values(0u, 16u, 32u, 48u)] uint shift) + { + uint Opcode = 0xF2800000; // MOVK X0, #0, LSL #0 + Opcode |= ((Rd & 31) << 0); + Opcode |= (((shift / 16) & 3) << 21) | ((imm & 65535) << 5); + + ulong _X31 = TestContext.CurrentContext.Random.NextULong(); + AThreadState ThreadState = SingleOpcode(Opcode, X0: _Xd, X31: _X31); + + if (Rd != 31) + { + Bits Op = new Bits(Opcode); + + AArch64.X((int)Rd, new Bits(_Xd)); + Base.Movk(Op[31], Op[22, 21], Op[20, 5], Op[4, 0]); + ulong Xd = AArch64.X(64, (int)Rd).ToUInt64(); + + Assert.That((ulong)ThreadState.X0, Is.EqualTo(Xd)); + } + else + { + Assert.That((ulong)ThreadState.X31, Is.EqualTo(_X31)); + } + } + + [Test, Description("MOVK , #{, LSL #}")] + public void Movk_32bit([Values(0u, 31u)] uint Rd, + [Random(12)] uint _Wd, + [Values(0u, 65535u)] [Random(0u, 65535u, 10)] uint imm, + [Values(0u, 16u)] uint shift) + { + uint Opcode = 0x72800000; // MOVK W0, #0, LSL #0 + Opcode |= ((Rd & 31) << 0); + Opcode |= (((shift / 16) & 3) << 21) | ((imm & 65535) << 5); + + uint _W31 = TestContext.CurrentContext.Random.NextUInt(); + AThreadState ThreadState = SingleOpcode(Opcode, X0: _Wd, X31: _W31); + + if (Rd != 31) + { + Bits Op = new Bits(Opcode); + + AArch64.X((int)Rd, new Bits(_Wd)); + Base.Movk(Op[31], Op[22, 21], Op[20, 5], Op[4, 0]); + uint Wd = AArch64.X(32, (int)Rd).ToUInt32(); + + Assert.That((uint)ThreadState.X0, Is.EqualTo(Wd)); + } + else + { + Assert.That((uint)ThreadState.X31, Is.EqualTo(_W31)); + } + } + + [Test, Description("MOVN , #{, LSL #}")] + public void Movn_64bit([Values(0u, 31u)] uint Rd, + [Values(0u, 65535u)] [Random(0u, 65535u, 128)] uint imm, + [Values(0u, 16u, 32u, 48u)] uint shift) + { + uint Opcode = 0x92800000; // MOVN X0, #0, LSL #0 + Opcode |= ((Rd & 31) << 0); + Opcode |= (((shift / 16) & 3) << 21) | ((imm & 65535) << 5); + + ulong _X31 = TestContext.CurrentContext.Random.NextULong(); + AThreadState ThreadState = SingleOpcode(Opcode, X31: _X31); + + if (Rd != 31) + { + Bits Op = new Bits(Opcode); + + Base.Movn(Op[31], Op[22, 21], Op[20, 5], Op[4, 0]); + ulong Xd = AArch64.X(64, (int)Rd).ToUInt64(); + + Assert.That((ulong)ThreadState.X0, Is.EqualTo(Xd)); + } + else + { + Assert.That((ulong)ThreadState.X31, Is.EqualTo(_X31)); + } + } + + [Test, Description("MOVN , #{, LSL #}")] + public void Movn_32bit([Values(0u, 31u)] uint Rd, + [Values(0u, 65535u)] [Random(0u, 65535u, 128)] uint imm, + [Values(0u, 16u)] uint shift) + { + uint Opcode = 0x12800000; // MOVN W0, #0, LSL #0 + Opcode |= ((Rd & 31) << 0); + Opcode |= (((shift / 16) & 3) << 21) | ((imm & 65535) << 5); + + uint _W31 = TestContext.CurrentContext.Random.NextUInt(); + AThreadState ThreadState = SingleOpcode(Opcode, X31: _W31); + + if (Rd != 31) + { + Bits Op = new Bits(Opcode); + + Base.Movn(Op[31], Op[22, 21], Op[20, 5], Op[4, 0]); + uint Wd = AArch64.X(32, (int)Rd).ToUInt32(); + + Assert.That((uint)ThreadState.X0, Is.EqualTo(Wd)); + } + else + { + Assert.That((uint)ThreadState.X31, Is.EqualTo(_W31)); + } + } + + [Test, Description("MOVZ , #{, LSL #}")] + public void Movz_64bit([Values(0u, 31u)] uint Rd, + [Values(0u, 65535u)] [Random(0u, 65535u, 128)] uint imm, + [Values(0u, 16u, 32u, 48u)] uint shift) + { + uint Opcode = 0xD2800000; // MOVZ X0, #0, LSL #0 + Opcode |= ((Rd & 31) << 0); + Opcode |= (((shift / 16) & 3) << 21) | ((imm & 65535) << 5); + + ulong _X31 = TestContext.CurrentContext.Random.NextULong(); + AThreadState ThreadState = SingleOpcode(Opcode, X31: _X31); + + if (Rd != 31) + { + Bits Op = new Bits(Opcode); + + Base.Movz(Op[31], Op[22, 21], Op[20, 5], Op[4, 0]); + ulong Xd = AArch64.X(64, (int)Rd).ToUInt64(); + + Assert.That((ulong)ThreadState.X0, Is.EqualTo(Xd)); + } + else + { + Assert.That((ulong)ThreadState.X31, Is.EqualTo(_X31)); + } + } + + [Test, Description("MOVZ , #{, LSL #}")] + public void Movz_32bit([Values(0u, 31u)] uint Rd, + [Values(0u, 65535u)] [Random(0u, 65535u, 128)] uint imm, + [Values(0u, 16u)] uint shift) + { + uint Opcode = 0x52800000; // MOVZ W0, #0, LSL #0 + Opcode |= ((Rd & 31) << 0); + Opcode |= (((shift / 16) & 3) << 21) | ((imm & 65535) << 5); + + uint _W31 = TestContext.CurrentContext.Random.NextUInt(); + AThreadState ThreadState = SingleOpcode(Opcode, X31: _W31); + + if (Rd != 31) + { + Bits Op = new Bits(Opcode); + + Base.Movz(Op[31], Op[22, 21], Op[20, 5], Op[4, 0]); + uint Wd = AArch64.X(32, (int)Rd).ToUInt32(); + + Assert.That((uint)ThreadState.X0, Is.EqualTo(Wd)); + } + else + { + Assert.That((uint)ThreadState.X31, Is.EqualTo(_W31)); + } + } +#endif + } +} diff --git a/Ryujinx.Tests/Cpu/CpuTestMul.cs b/Ryujinx.Tests/Cpu/CpuTestMul.cs new file mode 100644 index 000000000..9bdc1fa65 --- /dev/null +++ b/Ryujinx.Tests/Cpu/CpuTestMul.cs @@ -0,0 +1,375 @@ +//#define Mul + +using ChocolArm64.State; + +using NUnit.Framework; + +namespace Ryujinx.Tests.Cpu +{ + using Tester; + using Tester.Types; + + [Category("Mul"), Ignore("Tested: first half of 2018.")] + public sealed class CpuTestMul : CpuTest + { +#if Mul + [SetUp] + public void SetupTester() + { + AArch64.TakeReset(false); + } + + [Test, Description("MADD , , , ")] + public void Madd_64bit([Values(0u, 31u)] uint Rd, + [Values(1u, 31u)] uint Rn, + [Values(2u, 31u)] uint Rm, + [Values(3u, 31u)] uint Ra, + [Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul, + 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(2)] ulong Xn, + [Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul, + 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(2)] ulong Xm, + [Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul, + 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(2)] ulong Xa) + { + uint Opcode = 0x9B000000; // MADD X0, X0, X0, X0 + Opcode |= ((Rm & 31) << 16) | ((Ra & 31) << 10) | ((Rn & 31) << 5) | ((Rd & 31) << 0); + + ulong _X31 = TestContext.CurrentContext.Random.NextULong(); + AThreadState ThreadState = SingleOpcode(Opcode, X1: Xn, X2: Xm, X3: Xa, X31: _X31); + + if (Rd != 31) + { + Bits Op = new Bits(Opcode); + + AArch64.X((int)Rn, new Bits(Xn)); + AArch64.X((int)Rm, new Bits(Xm)); + AArch64.X((int)Ra, new Bits(Xa)); + Base.Madd(Op[31], Op[20, 16], Op[14, 10], Op[9, 5], Op[4, 0]); + ulong Xd = AArch64.X(64, (int)Rd).ToUInt64(); + + Assert.That((ulong)ThreadState.X0, Is.EqualTo(Xd)); + } + else + { + Assert.That((ulong)ThreadState.X31, Is.EqualTo(_X31)); + } + } + + [Test, Description("MADD , , , ")] + public void Madd_32bit([Values(0u, 31u)] uint Rd, + [Values(1u, 31u)] uint Rn, + [Values(2u, 31u)] uint Rm, + [Values(3u, 31u)] uint Ra, + [Values(0x00000000u, 0x7FFFFFFFu, + 0x80000000u, 0xFFFFFFFFu)] [Random(2)] uint Wn, + [Values(0x00000000u, 0x7FFFFFFFu, + 0x80000000u, 0xFFFFFFFFu)] [Random(2)] uint Wm, + [Values(0x00000000u, 0x7FFFFFFFu, + 0x80000000u, 0xFFFFFFFFu)] [Random(2)] uint Wa) + { + uint Opcode = 0x1B000000; // MADD W0, W0, W0, W0 + Opcode |= ((Rm & 31) << 16) | ((Ra & 31) << 10) | ((Rn & 31) << 5) | ((Rd & 31) << 0); + + uint _W31 = TestContext.CurrentContext.Random.NextUInt(); + AThreadState ThreadState = SingleOpcode(Opcode, X1: Wn, X2: Wm, X3: Wa, X31: _W31); + + if (Rd != 31) + { + Bits Op = new Bits(Opcode); + + AArch64.X((int)Rn, new Bits(Wn)); + AArch64.X((int)Rm, new Bits(Wm)); + AArch64.X((int)Ra, new Bits(Wa)); + Base.Madd(Op[31], Op[20, 16], Op[14, 10], Op[9, 5], Op[4, 0]); + uint Wd = AArch64.X(32, (int)Rd).ToUInt32(); + + Assert.That((uint)ThreadState.X0, Is.EqualTo(Wd)); + } + else + { + Assert.That((uint)ThreadState.X31, Is.EqualTo(_W31)); + } + } + + [Test, Description("MSUB , , , ")] + public void Msub_64bit([Values(0u, 31u)] uint Rd, + [Values(1u, 31u)] uint Rn, + [Values(2u, 31u)] uint Rm, + [Values(3u, 31u)] uint Ra, + [Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul, + 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(2)] ulong Xn, + [Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul, + 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(2)] ulong Xm, + [Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul, + 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(2)] ulong Xa) + { + uint Opcode = 0x9B008000; // MSUB X0, X0, X0, X0 + Opcode |= ((Rm & 31) << 16) | ((Ra & 31) << 10) | ((Rn & 31) << 5) | ((Rd & 31) << 0); + + ulong _X31 = TestContext.CurrentContext.Random.NextULong(); + AThreadState ThreadState = SingleOpcode(Opcode, X1: Xn, X2: Xm, X3: Xa, X31: _X31); + + if (Rd != 31) + { + Bits Op = new Bits(Opcode); + + AArch64.X((int)Rn, new Bits(Xn)); + AArch64.X((int)Rm, new Bits(Xm)); + AArch64.X((int)Ra, new Bits(Xa)); + Base.Msub(Op[31], Op[20, 16], Op[14, 10], Op[9, 5], Op[4, 0]); + ulong Xd = AArch64.X(64, (int)Rd).ToUInt64(); + + Assert.That((ulong)ThreadState.X0, Is.EqualTo(Xd)); + } + else + { + Assert.That((ulong)ThreadState.X31, Is.EqualTo(_X31)); + } + } + + [Test, Description("MSUB , , , ")] + public void Msub_32bit([Values(0u, 31u)] uint Rd, + [Values(1u, 31u)] uint Rn, + [Values(2u, 31u)] uint Rm, + [Values(3u, 31u)] uint Ra, + [Values(0x00000000u, 0x7FFFFFFFu, + 0x80000000u, 0xFFFFFFFFu)] [Random(2)] uint Wn, + [Values(0x00000000u, 0x7FFFFFFFu, + 0x80000000u, 0xFFFFFFFFu)] [Random(2)] uint Wm, + [Values(0x00000000u, 0x7FFFFFFFu, + 0x80000000u, 0xFFFFFFFFu)] [Random(2)] uint Wa) + { + uint Opcode = 0x1B008000; // MSUB W0, W0, W0, W0 + Opcode |= ((Rm & 31) << 16) | ((Ra & 31) << 10) | ((Rn & 31) << 5) | ((Rd & 31) << 0); + + uint _W31 = TestContext.CurrentContext.Random.NextUInt(); + AThreadState ThreadState = SingleOpcode(Opcode, X1: Wn, X2: Wm, X3: Wa, X31: _W31); + + if (Rd != 31) + { + Bits Op = new Bits(Opcode); + + AArch64.X((int)Rn, new Bits(Wn)); + AArch64.X((int)Rm, new Bits(Wm)); + AArch64.X((int)Ra, new Bits(Wa)); + Base.Msub(Op[31], Op[20, 16], Op[14, 10], Op[9, 5], Op[4, 0]); + uint Wd = AArch64.X(32, (int)Rd).ToUInt32(); + + Assert.That((uint)ThreadState.X0, Is.EqualTo(Wd)); + } + else + { + Assert.That((uint)ThreadState.X31, Is.EqualTo(_W31)); + } + } + + [Test, Description("SMADDL , , , ")] + public void Smaddl_64bit([Values(0u, 31u)] uint Rd, + [Values(1u, 31u)] uint Rn, + [Values(2u, 31u)] uint Rm, + [Values(3u, 31u)] uint Ra, + [Values(0x00000000u, 0x7FFFFFFFu, + 0x80000000u, 0xFFFFFFFFu)] [Random(2)] uint Wn, + [Values(0x00000000u, 0x7FFFFFFFu, + 0x80000000u, 0xFFFFFFFFu)] [Random(2)] uint Wm, + [Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul, + 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(2)] ulong Xa) + { + uint Opcode = 0x9B200000; // SMADDL X0, W0, W0, X0 + Opcode |= ((Rm & 31) << 16) | ((Ra & 31) << 10) | ((Rn & 31) << 5) | ((Rd & 31) << 0); + + ulong _X31 = TestContext.CurrentContext.Random.NextULong(); + AThreadState ThreadState = SingleOpcode(Opcode, X1: Wn, X2: Wm, X3: Xa, X31: _X31); + + if (Rd != 31) + { + Bits Op = new Bits(Opcode); + + AArch64.X((int)Rn, new Bits(Wn)); + AArch64.X((int)Rm, new Bits(Wm)); + AArch64.X((int)Ra, new Bits(Xa)); + Base.Smaddl(Op[20, 16], Op[14, 10], Op[9, 5], Op[4, 0]); + ulong Xd = AArch64.X(64, (int)Rd).ToUInt64(); + + Assert.That((ulong)ThreadState.X0, Is.EqualTo(Xd)); + } + else + { + Assert.That((ulong)ThreadState.X31, Is.EqualTo(_X31)); + } + } + + [Test, Description("UMADDL , , , ")] + public void Umaddl_64bit([Values(0u, 31u)] uint Rd, + [Values(1u, 31u)] uint Rn, + [Values(2u, 31u)] uint Rm, + [Values(3u, 31u)] uint Ra, + [Values(0x00000000u, 0x7FFFFFFFu, + 0x80000000u, 0xFFFFFFFFu)] [Random(2)] uint Wn, + [Values(0x00000000u, 0x7FFFFFFFu, + 0x80000000u, 0xFFFFFFFFu)] [Random(2)] uint Wm, + [Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul, + 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(2)] ulong Xa) + { + uint Opcode = 0x9BA00000; // UMADDL X0, W0, W0, X0 + Opcode |= ((Rm & 31) << 16) | ((Ra & 31) << 10) | ((Rn & 31) << 5) | ((Rd & 31) << 0); + + ulong _X31 = TestContext.CurrentContext.Random.NextULong(); + AThreadState ThreadState = SingleOpcode(Opcode, X1: Wn, X2: Wm, X3: Xa, X31: _X31); + + if (Rd != 31) + { + Bits Op = new Bits(Opcode); + + AArch64.X((int)Rn, new Bits(Wn)); + AArch64.X((int)Rm, new Bits(Wm)); + AArch64.X((int)Ra, new Bits(Xa)); + Base.Umaddl(Op[20, 16], Op[14, 10], Op[9, 5], Op[4, 0]); + ulong Xd = AArch64.X(64, (int)Rd).ToUInt64(); + + Assert.That((ulong)ThreadState.X0, Is.EqualTo(Xd)); + } + else + { + Assert.That((ulong)ThreadState.X31, Is.EqualTo(_X31)); + } + } + + [Test, Description("SMSUBL , , , ")] + public void Smsubl_64bit([Values(0u, 31u)] uint Rd, + [Values(1u, 31u)] uint Rn, + [Values(2u, 31u)] uint Rm, + [Values(3u, 31u)] uint Ra, + [Values(0x00000000u, 0x7FFFFFFFu, + 0x80000000u, 0xFFFFFFFFu)] [Random(2)] uint Wn, + [Values(0x00000000u, 0x7FFFFFFFu, + 0x80000000u, 0xFFFFFFFFu)] [Random(2)] uint Wm, + [Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul, + 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(2)] ulong Xa) + { + uint Opcode = 0x9B208000; // SMSUBL X0, W0, W0, X0 + Opcode |= ((Rm & 31) << 16) | ((Ra & 31) << 10) | ((Rn & 31) << 5) | ((Rd & 31) << 0); + + ulong _X31 = TestContext.CurrentContext.Random.NextULong(); + AThreadState ThreadState = SingleOpcode(Opcode, X1: Wn, X2: Wm, X3: Xa, X31: _X31); + + if (Rd != 31) + { + Bits Op = new Bits(Opcode); + + AArch64.X((int)Rn, new Bits(Wn)); + AArch64.X((int)Rm, new Bits(Wm)); + AArch64.X((int)Ra, new Bits(Xa)); + Base.Smsubl(Op[20, 16], Op[14, 10], Op[9, 5], Op[4, 0]); + ulong Xd = AArch64.X(64, (int)Rd).ToUInt64(); + + Assert.That((ulong)ThreadState.X0, Is.EqualTo(Xd)); + } + else + { + Assert.That((ulong)ThreadState.X31, Is.EqualTo(_X31)); + } + } + + [Test, Description("UMSUBL , , , ")] + public void Umsubl_64bit([Values(0u, 31u)] uint Rd, + [Values(1u, 31u)] uint Rn, + [Values(2u, 31u)] uint Rm, + [Values(3u, 31u)] uint Ra, + [Values(0x00000000u, 0x7FFFFFFFu, + 0x80000000u, 0xFFFFFFFFu)] [Random(2)] uint Wn, + [Values(0x00000000u, 0x7FFFFFFFu, + 0x80000000u, 0xFFFFFFFFu)] [Random(2)] uint Wm, + [Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul, + 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(2)] ulong Xa) + { + uint Opcode = 0x9BA08000; // UMSUBL X0, W0, W0, X0 + Opcode |= ((Rm & 31) << 16) | ((Ra & 31) << 10) | ((Rn & 31) << 5) | ((Rd & 31) << 0); + + ulong _X31 = TestContext.CurrentContext.Random.NextULong(); + AThreadState ThreadState = SingleOpcode(Opcode, X1: Wn, X2: Wm, X3: Xa, X31: _X31); + + if (Rd != 31) + { + Bits Op = new Bits(Opcode); + + AArch64.X((int)Rn, new Bits(Wn)); + AArch64.X((int)Rm, new Bits(Wm)); + AArch64.X((int)Ra, new Bits(Xa)); + Base.Umsubl(Op[20, 16], Op[14, 10], Op[9, 5], Op[4, 0]); + ulong Xd = AArch64.X(64, (int)Rd).ToUInt64(); + + Assert.That((ulong)ThreadState.X0, Is.EqualTo(Xd)); + } + else + { + Assert.That((ulong)ThreadState.X31, Is.EqualTo(_X31)); + } + } + + [Test, Description("SMULH , , ")] + public void Smulh_64bit([Values(0u, 31u)] uint Rd, + [Values(1u, 31u)] uint Rn, + [Values(2u, 31u)] uint Rm, + [Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul, + 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(16)] ulong Xn, + [Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul, + 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(16)] ulong Xm) + { + uint Opcode = 0x9B407C00; // SMULH X0, X0, X0 + Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); + + ulong _X31 = TestContext.CurrentContext.Random.NextULong(); + AThreadState ThreadState = SingleOpcode(Opcode, X1: Xn, X2: Xm, X31: _X31); + + if (Rd != 31) + { + Bits Op = new Bits(Opcode); + + AArch64.X((int)Rn, new Bits(Xn)); + AArch64.X((int)Rm, new Bits(Xm)); + Base.Smulh(Op[20, 16], Op[9, 5], Op[4, 0]); + ulong Xd = AArch64.X(64, (int)Rd).ToUInt64(); + + Assert.That((ulong)ThreadState.X0, Is.EqualTo(Xd)); + } + else + { + Assert.That((ulong)ThreadState.X31, Is.EqualTo(_X31)); + } + } + + [Test, Description("UMULH , , ")] + public void Umulh_64bit([Values(0u, 31u)] uint Rd, + [Values(1u, 31u)] uint Rn, + [Values(2u, 31u)] uint Rm, + [Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul, + 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(16)] ulong Xn, + [Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul, + 0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(16)] ulong Xm) + { + uint Opcode = 0x9BC07C00; // UMULH X0, X0, X0 + Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0); + + ulong _X31 = TestContext.CurrentContext.Random.NextULong(); + AThreadState ThreadState = SingleOpcode(Opcode, X1: Xn, X2: Xm, X31: _X31); + + if (Rd != 31) + { + Bits Op = new Bits(Opcode); + + AArch64.X((int)Rn, new Bits(Xn)); + AArch64.X((int)Rm, new Bits(Xm)); + Base.Umulh(Op[20, 16], Op[9, 5], Op[4, 0]); + ulong Xd = AArch64.X(64, (int)Rd).ToUInt64(); + + Assert.That((ulong)ThreadState.X0, Is.EqualTo(Xd)); + } + else + { + Assert.That((ulong)ThreadState.X31, Is.EqualTo(_X31)); + } + } +#endif + } +} diff --git a/Ryujinx.Tests/Cpu/Tester/Instructions.cs b/Ryujinx.Tests/Cpu/Tester/Instructions.cs new file mode 100644 index 000000000..7a51923f8 --- /dev/null +++ b/Ryujinx.Tests/Cpu/Tester/Instructions.cs @@ -0,0 +1,1682 @@ +// https://github.com/LDj3SNuD/ARM_v8-A_AArch64_Instructions_Tester/blob/master/Tester/Instructions.cs + +// https://meriac.github.io/archex/A64_v83A_ISA/index.xml +/* https://meriac.github.io/archex/A64_v83A_ISA/fpsimdindex.xml */ + +using System.Numerics; + +namespace Ryujinx.Tests.Cpu.Tester +{ + using Types; + + using static AArch64; + using static Shared; + + internal static class Base + { +#region "Alu" + // https://meriac.github.io/archex/A64_v83A_ISA/cls_int.xml + public static void Cls(bool sf, Bits Rn, Bits Rd) + { + /* Decode */ + int d = (int)UInt(Rd); + int n = (int)UInt(Rn); + int datasize = (sf ? 64 : 32); + + /* Operation */ + Bits operand1 = X(datasize, n); + + BigInteger result = (BigInteger)CountLeadingSignBits(operand1); + + X(d, result.SubBigInteger(datasize - 1, 0)); + } + + // https://meriac.github.io/archex/A64_v83A_ISA/clz_int.xml + public static void Clz(bool sf, Bits Rn, Bits Rd) + { + /* Decode */ + int d = (int)UInt(Rd); + int n = (int)UInt(Rn); + int datasize = (sf ? 64 : 32); + + /* Operation */ + Bits operand1 = X(datasize, n); + + BigInteger result = (BigInteger)CountLeadingZeroBits(operand1); + + X(d, result.SubBigInteger(datasize - 1, 0)); + } + + // https://meriac.github.io/archex/A64_v83A_ISA/rbit_int.xml + public static void Rbit(bool sf, Bits Rn, Bits Rd) + { + /* Decode */ + int d = (int)UInt(Rd); + int n = (int)UInt(Rn); + int datasize = (sf ? 64 : 32); + + /* Operation */ + Bits result = new Bits(datasize); + Bits operand = X(datasize, n); + + for (int i = 0; i <= datasize - 1; i++) + { + result[datasize - 1 - i] = operand[i]; + } + + X(d, result); + } + + // https://meriac.github.io/archex/A64_v83A_ISA/rev16_int.xml + public static void Rev16(bool sf, Bits Rn, Bits Rd) + { + /* Bits opc = "01"; */ + + /* Decode */ + int d = (int)UInt(Rd); + int n = (int)UInt(Rn); + int datasize = (sf ? 64 : 32); + + int container_size = 16; + + /* Operation */ + Bits result = new Bits(datasize); + Bits operand = X(datasize, n); + + int containers = datasize / container_size; + int elements_per_container = container_size / 8; + int index = 0; + int rev_index; + + for (int c = 0; c <= containers - 1; c++) + { + rev_index = index + ((elements_per_container - 1) * 8); + + for (int e = 0; e <= elements_per_container - 1; e++) + { + result[rev_index + 7, rev_index] = operand[index + 7, index]; + + index = index + 8; + rev_index = rev_index - 8; + } + } + + X(d, result); + } + + // https://meriac.github.io/archex/A64_v83A_ISA/rev32_int.xml + // (https://meriac.github.io/archex/A64_v83A_ISA/rev.xml) + public static void Rev32(bool sf, Bits Rn, Bits Rd) + { + /* Bits opc = "10"; */ + + /* Decode */ + int d = (int)UInt(Rd); + int n = (int)UInt(Rn); + int datasize = (sf ? 64 : 32); + + int container_size = 32; + + /* Operation */ + Bits result = new Bits(datasize); + Bits operand = X(datasize, n); + + int containers = datasize / container_size; + int elements_per_container = container_size / 8; + int index = 0; + int rev_index; + + for (int c = 0; c <= containers - 1; c++) + { + rev_index = index + ((elements_per_container - 1) * 8); + + for (int e = 0; e <= elements_per_container - 1; e++) + { + result[rev_index + 7, rev_index] = operand[index + 7, index]; + + index = index + 8; + rev_index = rev_index - 8; + } + } + + X(d, result); + } + + // https://meriac.github.io/archex/A64_v83A_ISA/rev64_rev.xml + // (https://meriac.github.io/archex/A64_v83A_ISA/rev.xml) + public static void Rev64(Bits Rn, Bits Rd) + { + /* Bits opc = "11"; */ + + /* Decode */ + int d = (int)UInt(Rd); + int n = (int)UInt(Rn); + + int container_size = 64; + + /* Operation */ + Bits result = new Bits(64); + Bits operand = X(64, n); + + int containers = 64 / container_size; + int elements_per_container = container_size / 8; + int index = 0; + int rev_index; + + for (int c = 0; c <= containers - 1; c++) + { + rev_index = index + ((elements_per_container - 1) * 8); + + for (int e = 0; e <= elements_per_container - 1; e++) + { + result[rev_index + 7, rev_index] = operand[index + 7, index]; + + index = index + 8; + rev_index = rev_index - 8; + } + } + + X(d, result); + } +#endregion + +#region "AluImm" + // https://meriac.github.io/archex/A64_v83A_ISA/add_addsub_imm.xml + public static void Add_Imm(bool sf, Bits shift, Bits imm12, Bits Rn, Bits Rd) + { + /* Decode */ + int d = (int)UInt(Rd); + int n = (int)UInt(Rn); + int datasize = (sf ? 64 : 32); + + Bits imm; + + switch (shift) + { + default: + case Bits bits when bits == "00": + imm = ZeroExtend(imm12, datasize); + break; + case Bits bits when bits == "01": + imm = ZeroExtend(Bits.Concat(imm12, Zeros(12)), datasize); + break; + /* when '1x' ReservedValue(); */ + } + + /* Operation */ + Bits result; + Bits operand1 = (n == 31 ? SP(datasize) : X(datasize, n)); + + (result, _) = AddWithCarry(datasize, operand1, imm, false); + + if (d == 31) + { + SP(result); + } + else + { + X(d, result); + } + } + + // https://meriac.github.io/archex/A64_v83A_ISA/adds_addsub_imm.xml + public static void Adds_Imm(bool sf, Bits shift, Bits imm12, Bits Rn, Bits Rd) + { + /* Decode */ + int d = (int)UInt(Rd); + int n = (int)UInt(Rn); + int datasize = (sf ? 64 : 32); + + Bits imm; + + switch (shift) + { + default: + case Bits bits when bits == "00": + imm = ZeroExtend(imm12, datasize); + break; + case Bits bits when bits == "01": + imm = ZeroExtend(Bits.Concat(imm12, Zeros(12)), datasize); + break; + /* when '1x' ReservedValue(); */ + } + + /* Operation */ + Bits result; + Bits operand1 = (n == 31 ? SP(datasize) : X(datasize, n)); + Bits nzcv; + + (result, nzcv) = AddWithCarry(datasize, operand1, imm, false); + + PSTATE.NZCV(nzcv); + + X(d, result); + } + + // https://meriac.github.io/archex/A64_v83A_ISA/and_log_imm.xml + public static void And_Imm(bool sf, bool N, Bits immr, Bits imms, Bits Rn, Bits Rd) + { + /* Decode */ + int d = (int)UInt(Rd); + int n = (int)UInt(Rn); + int datasize = (sf ? 64 : 32); + + Bits imm; + + /* if sf == '0' && N != '0' then ReservedValue(); */ + + (imm, _) = DecodeBitMasks(datasize, N, imms, immr, true); + + /* Operation */ + Bits operand1 = X(datasize, n); + + Bits result = AND(operand1, imm); + + if (d == 31) + { + SP(result); + } + else + { + X(d, result); + } + } + + // https://meriac.github.io/archex/A64_v83A_ISA/ands_log_imm.xml + public static void Ands_Imm(bool sf, bool N, Bits immr, Bits imms, Bits Rn, Bits Rd) + { + /* Decode */ + int d = (int)UInt(Rd); + int n = (int)UInt(Rn); + int datasize = (sf ? 64 : 32); + + Bits imm; + + /* if sf == '0' && N != '0' then ReservedValue(); */ + + (imm, _) = DecodeBitMasks(datasize, N, imms, immr, true); + + /* Operation */ + Bits operand1 = X(datasize, n); + + Bits result = AND(operand1, imm); + + PSTATE.NZCV(result[datasize - 1], IsZeroBit(result), false, false); + + X(d, result); + } + + // https://meriac.github.io/archex/A64_v83A_ISA/eor_log_imm.xml + public static void Eor_Imm(bool sf, bool N, Bits immr, Bits imms, Bits Rn, Bits Rd) + { + /* Decode */ + int d = (int)UInt(Rd); + int n = (int)UInt(Rn); + int datasize = (sf ? 64 : 32); + + Bits imm; + + /* if sf == '0' && N != '0' then ReservedValue(); */ + + (imm, _) = DecodeBitMasks(datasize, N, imms, immr, true); + + /* Operation */ + Bits operand1 = X(datasize, n); + + Bits result = EOR(operand1, imm); + + if (d == 31) + { + SP(result); + } + else + { + X(d, result); + } + } + + // https://meriac.github.io/archex/A64_v83A_ISA/orr_log_imm.xml + public static void Orr_Imm(bool sf, bool N, Bits immr, Bits imms, Bits Rn, Bits Rd) + { + /* Decode */ + int d = (int)UInt(Rd); + int n = (int)UInt(Rn); + int datasize = (sf ? 64 : 32); + + Bits imm; + + /* if sf == '0' && N != '0' then ReservedValue(); */ + + (imm, _) = DecodeBitMasks(datasize, N, imms, immr, true); + + /* Operation */ + Bits operand1 = X(datasize, n); + + Bits result = OR(operand1, imm); + + if (d == 31) + { + SP(result); + } + else + { + X(d, result); + } + } + + // https://meriac.github.io/archex/A64_v83A_ISA/sub_addsub_imm.xml + public static void Sub_Imm(bool sf, Bits shift, Bits imm12, Bits Rn, Bits Rd) + { + /* Decode */ + int d = (int)UInt(Rd); + int n = (int)UInt(Rn); + int datasize = (sf ? 64 : 32); + + Bits imm; + + switch (shift) + { + default: + case Bits bits when bits == "00": + imm = ZeroExtend(imm12, datasize); + break; + case Bits bits when bits == "01": + imm = ZeroExtend(Bits.Concat(imm12, Zeros(12)), datasize); + break; + /* when '1x' ReservedValue(); */ + } + + /* Operation */ + Bits result; + Bits operand1 = (n == 31 ? SP(datasize) : X(datasize, n)); + Bits operand2 = NOT(imm); + + (result, _) = AddWithCarry(datasize, operand1, operand2, true); + + if (d == 31) + { + SP(result); + } + else + { + X(d, result); + } + } + + // https://meriac.github.io/archex/A64_v83A_ISA/subs_addsub_imm.xml + public static void Subs_Imm(bool sf, Bits shift, Bits imm12, Bits Rn, Bits Rd) + { + /* Decode */ + int d = (int)UInt(Rd); + int n = (int)UInt(Rn); + int datasize = (sf ? 64 : 32); + + Bits imm; + + switch (shift) + { + default: + case Bits bits when bits == "00": + imm = ZeroExtend(imm12, datasize); + break; + case Bits bits when bits == "01": + imm = ZeroExtend(Bits.Concat(imm12, Zeros(12)), datasize); + break; + /* when '1x' ReservedValue(); */ + } + + /* Operation */ + Bits result; + Bits operand1 = (n == 31 ? SP(datasize) : X(datasize, n)); + Bits operand2 = NOT(imm); + Bits nzcv; + + (result, nzcv) = AddWithCarry(datasize, operand1, operand2, true); + + PSTATE.NZCV(nzcv); + + X(d, result); + } +#endregion + +#region "AluRs" + // https://meriac.github.io/archex/A64_v83A_ISA/adc.xml + public static void Adc(bool sf, Bits Rm, Bits Rn, Bits Rd) + { + /* Decode */ + int d = (int)UInt(Rd); + int n = (int)UInt(Rn); + int m = (int)UInt(Rm); + int datasize = (sf ? 64 : 32); + + /* Operation */ + Bits result; + Bits operand1 = X(datasize, n); + Bits operand2 = X(datasize, m); + + (result, _) = AddWithCarry(datasize, operand1, operand2, PSTATE.C); + + X(d, result); + } + + // https://meriac.github.io/archex/A64_v83A_ISA/adcs.xml + public static void Adcs(bool sf, Bits Rm, Bits Rn, Bits Rd) + { + /* Decode */ + int d = (int)UInt(Rd); + int n = (int)UInt(Rn); + int m = (int)UInt(Rm); + int datasize = (sf ? 64 : 32); + + /* Operation */ + Bits result; + Bits operand1 = X(datasize, n); + Bits operand2 = X(datasize, m); + Bits nzcv; + + (result, nzcv) = AddWithCarry(datasize, operand1, operand2, PSTATE.C); + + PSTATE.NZCV(nzcv); + + X(d, result); + } + + // https://meriac.github.io/archex/A64_v83A_ISA/add_addsub_shift.xml + public static void Add_Rs(bool sf, Bits shift, Bits Rm, Bits imm6, Bits Rn, Bits Rd) + { + /* Decode */ + int d = (int)UInt(Rd); + int n = (int)UInt(Rn); + int m = (int)UInt(Rm); + int datasize = (sf ? 64 : 32); + + /* if shift == '11' then ReservedValue(); */ + /* if sf == '0' && imm6<5> == '1' then ReservedValue(); */ + + ShiftType shift_type = DecodeShift(shift); + int shift_amount = (int)UInt(imm6); + + /* Operation */ + Bits result; + Bits operand1 = X(datasize, n); + Bits operand2 = ShiftReg(datasize, m, shift_type, shift_amount); + + (result, _) = AddWithCarry(datasize, operand1, operand2, false); + + X(d, result); + } + + // https://meriac.github.io/archex/A64_v83A_ISA/adds_addsub_shift.xml + public static void Adds_Rs(bool sf, Bits shift, Bits Rm, Bits imm6, Bits Rn, Bits Rd) + { + /* Decode */ + int d = (int)UInt(Rd); + int n = (int)UInt(Rn); + int m = (int)UInt(Rm); + int datasize = (sf ? 64 : 32); + + /* if shift == '11' then ReservedValue(); */ + /* if sf == '0' && imm6<5> == '1' then ReservedValue(); */ + + ShiftType shift_type = DecodeShift(shift); + int shift_amount = (int)UInt(imm6); + + /* Operation */ + Bits result; + Bits operand1 = X(datasize, n); + Bits operand2 = ShiftReg(datasize, m, shift_type, shift_amount); + Bits nzcv; + + (result, nzcv) = AddWithCarry(datasize, operand1, operand2, false); + + PSTATE.NZCV(nzcv); + + X(d, result); + } + + // https://meriac.github.io/archex/A64_v83A_ISA/and_log_shift.xml + public static void And_Rs(bool sf, Bits shift, Bits Rm, Bits imm6, Bits Rn, Bits Rd) + { + /* Decode */ + int d = (int)UInt(Rd); + int n = (int)UInt(Rn); + int m = (int)UInt(Rm); + int datasize = (sf ? 64 : 32); + + /* if sf == '0' && imm6<5> == '1' then ReservedValue(); */ + + ShiftType shift_type = DecodeShift(shift); + int shift_amount = (int)UInt(imm6); + + /* Operation */ + Bits operand1 = X(datasize, n); + Bits operand2 = ShiftReg(datasize, m, shift_type, shift_amount); + + Bits result = AND(operand1, operand2); + + X(d, result); + } + + // https://meriac.github.io/archex/A64_v83A_ISA/ands_log_shift.xml + public static void Ands_Rs(bool sf, Bits shift, Bits Rm, Bits imm6, Bits Rn, Bits Rd) + { + /* Decode */ + int d = (int)UInt(Rd); + int n = (int)UInt(Rn); + int m = (int)UInt(Rm); + int datasize = (sf ? 64 : 32); + + /* if sf == '0' && imm6<5> == '1' then ReservedValue(); */ + + ShiftType shift_type = DecodeShift(shift); + int shift_amount = (int)UInt(imm6); + + /* Operation */ + Bits operand1 = X(datasize, n); + Bits operand2 = ShiftReg(datasize, m, shift_type, shift_amount); + + Bits result = AND(operand1, operand2); + + PSTATE.NZCV(result[datasize - 1], IsZeroBit(result), false, false); + + X(d, result); + } + + // https://meriac.github.io/archex/A64_v83A_ISA/asrv.xml + public static void Asrv(bool sf, Bits Rm, Bits Rn, Bits Rd) + { + Bits op2 = "10"; + + /* Decode */ + int d = (int)UInt(Rd); + int n = (int)UInt(Rn); + int m = (int)UInt(Rm); + int datasize = (sf ? 64 : 32); + + ShiftType shift_type = DecodeShift(op2); + + /* Operation */ + Bits operand2 = X(datasize, m); + + Bits result = ShiftReg(datasize, n, shift_type, (int)(UInt(operand2) % datasize)); // BigInteger.Modulus Operator (BigInteger, BigInteger) + + X(d, result); + } + + // https://meriac.github.io/archex/A64_v83A_ISA/bic_log_shift.xml + public static void Bic(bool sf, Bits shift, Bits Rm, Bits imm6, Bits Rn, Bits Rd) + { + /* Decode */ + int d = (int)UInt(Rd); + int n = (int)UInt(Rn); + int m = (int)UInt(Rm); + int datasize = (sf ? 64 : 32); + + /* if sf == '0' && imm6<5> == '1' then ReservedValue(); */ + + ShiftType shift_type = DecodeShift(shift); + int shift_amount = (int)UInt(imm6); + + /* Operation */ + Bits operand1 = X(datasize, n); + Bits operand2 = ShiftReg(datasize, m, shift_type, shift_amount); + + operand2 = NOT(operand2); + + Bits result = AND(operand1, operand2); + + X(d, result); + } + + // https://meriac.github.io/archex/A64_v83A_ISA/bics.xml + public static void Bics(bool sf, Bits shift, Bits Rm, Bits imm6, Bits Rn, Bits Rd) + { + /* Decode */ + int d = (int)UInt(Rd); + int n = (int)UInt(Rn); + int m = (int)UInt(Rm); + int datasize = (sf ? 64 : 32); + + /* if sf == '0' && imm6<5> == '1' then ReservedValue(); */ + + ShiftType shift_type = DecodeShift(shift); + int shift_amount = (int)UInt(imm6); + + /* Operation */ + Bits operand1 = X(datasize, n); + Bits operand2 = ShiftReg(datasize, m, shift_type, shift_amount); + + operand2 = NOT(operand2); + + Bits result = AND(operand1, operand2); + + PSTATE.NZCV(result[datasize - 1], IsZeroBit(result), false, false); + + X(d, result); + } + + // https://meriac.github.io/archex/A64_v83A_ISA/crc32.xml + public static void Crc32(bool sf, Bits Rm, Bits sz, Bits Rn, Bits Rd) + { + /* Decode */ + int d = (int)UInt(Rd); + int n = (int)UInt(Rn); + int m = (int)UInt(Rm); + + /* if sf == '1' && sz != '11' then UnallocatedEncoding(); */ + /* if sf == '0' && sz == '11' then UnallocatedEncoding(); */ + + int size = 8 << (int)UInt(sz); + + /* Operation */ + /* if !HaveCRCExt() then UnallocatedEncoding(); */ + + Bits acc = X(32, n); // accumulator + Bits val = X(size, m); // input value + Bits poly = new Bits(0x04C11DB7u); + + Bits tempacc = Bits.Concat(BitReverse(acc), Zeros(size)); + Bits tempval = Bits.Concat(BitReverse(val), Zeros(32)); + + // Poly32Mod2 on a bitstring does a polynomial Modulus over {0,1} operation + X(d, BitReverse(Poly32Mod2(EOR(tempacc, tempval), poly))); + } + + // https://meriac.github.io/archex/A64_v83A_ISA/crc32c.xml + public static void Crc32c(bool sf, Bits Rm, Bits sz, Bits Rn, Bits Rd) + { + /* Decode */ + int d = (int)UInt(Rd); + int n = (int)UInt(Rn); + int m = (int)UInt(Rm); + + /* if sf == '1' && sz != '11' then UnallocatedEncoding(); */ + /* if sf == '0' && sz == '11' then UnallocatedEncoding(); */ + + int size = 8 << (int)UInt(sz); + + /* Operation */ + /* if !HaveCRCExt() then UnallocatedEncoding(); */ + + Bits acc = X(32, n); // accumulator + Bits val = X(size, m); // input value + Bits poly = new Bits(0x1EDC6F41u); + + Bits tempacc = Bits.Concat(BitReverse(acc), Zeros(size)); + Bits tempval = Bits.Concat(BitReverse(val), Zeros(32)); + + // Poly32Mod2 on a bitstring does a polynomial Modulus over {0,1} operation + X(d, BitReverse(Poly32Mod2(EOR(tempacc, tempval), poly))); + } + + // https://meriac.github.io/archex/A64_v83A_ISA/eon.xml + public static void Eon(bool sf, Bits shift, Bits Rm, Bits imm6, Bits Rn, Bits Rd) + { + /* Decode */ + int d = (int)UInt(Rd); + int n = (int)UInt(Rn); + int m = (int)UInt(Rm); + int datasize = (sf ? 64 : 32); + + /* if sf == '0' && imm6<5> == '1' then ReservedValue(); */ + + ShiftType shift_type = DecodeShift(shift); + int shift_amount = (int)UInt(imm6); + + /* Operation */ + Bits operand1 = X(datasize, n); + Bits operand2 = ShiftReg(datasize, m, shift_type, shift_amount); + + operand2 = NOT(operand2); + + Bits result = EOR(operand1, operand2); + + X(d, result); + } + + // https://meriac.github.io/archex/A64_v83A_ISA/eor_log_shift.xml + public static void Eor_Rs(bool sf, Bits shift, Bits Rm, Bits imm6, Bits Rn, Bits Rd) + { + /* Decode */ + int d = (int)UInt(Rd); + int n = (int)UInt(Rn); + int m = (int)UInt(Rm); + int datasize = (sf ? 64 : 32); + + /* if sf == '0' && imm6<5> == '1' then ReservedValue(); */ + + ShiftType shift_type = DecodeShift(shift); + int shift_amount = (int)UInt(imm6); + + /* Operation */ + Bits operand1 = X(datasize, n); + Bits operand2 = ShiftReg(datasize, m, shift_type, shift_amount); + + Bits result = EOR(operand1, operand2); + + X(d, result); + } + + // https://meriac.github.io/archex/A64_v83A_ISA/extr.xml + public static void Extr(bool sf, bool N, Bits Rm, Bits imms, Bits Rn, Bits Rd) + { + /* Decode */ + int d = (int)UInt(Rd); + int n = (int)UInt(Rn); + int m = (int)UInt(Rm); + int datasize = (sf ? 64 : 32); + + /* if N != sf then UnallocatedEncoding(); */ + /* if sf == '0' && imms<5> == '1' then ReservedValue(); */ + + int lsb = (int)UInt(imms); + + /* Operation */ + Bits operand1 = X(datasize, n); + Bits operand2 = X(datasize, m); + Bits concat = Bits.Concat(operand1, operand2); + + Bits result = concat[lsb + datasize - 1, lsb]; + + X(d, result); + } + + // https://meriac.github.io/archex/A64_v83A_ISA/lslv.xml + public static void Lslv(bool sf, Bits Rm, Bits Rn, Bits Rd) + { + Bits op2 = "00"; + + /* Decode */ + int d = (int)UInt(Rd); + int n = (int)UInt(Rn); + int m = (int)UInt(Rm); + int datasize = (sf ? 64 : 32); + + ShiftType shift_type = DecodeShift(op2); + + /* Operation */ + Bits operand2 = X(datasize, m); + + Bits result = ShiftReg(datasize, n, shift_type, (int)(UInt(operand2) % datasize)); // BigInteger.Modulus Operator (BigInteger, BigInteger) + + X(d, result); + } + + // https://meriac.github.io/archex/A64_v83A_ISA/lsrv.xml + public static void Lsrv(bool sf, Bits Rm, Bits Rn, Bits Rd) + { + Bits op2 = "01"; + + /* Decode */ + int d = (int)UInt(Rd); + int n = (int)UInt(Rn); + int m = (int)UInt(Rm); + int datasize = (sf ? 64 : 32); + + ShiftType shift_type = DecodeShift(op2); + + /* Operation */ + Bits operand2 = X(datasize, m); + + Bits result = ShiftReg(datasize, n, shift_type, (int)(UInt(operand2) % datasize)); // BigInteger.Modulus Operator (BigInteger, BigInteger) + + X(d, result); + } + + // https://meriac.github.io/archex/A64_v83A_ISA/orn_log_shift.xml + public static void Orn(bool sf, Bits shift, Bits Rm, Bits imm6, Bits Rn, Bits Rd) + { + /* Decode */ + int d = (int)UInt(Rd); + int n = (int)UInt(Rn); + int m = (int)UInt(Rm); + int datasize = (sf ? 64 : 32); + + /* if sf == '0' && imm6<5> == '1' then ReservedValue(); */ + + ShiftType shift_type = DecodeShift(shift); + int shift_amount = (int)UInt(imm6); + + /* Operation */ + Bits operand1 = X(datasize, n); + Bits operand2 = ShiftReg(datasize, m, shift_type, shift_amount); + + operand2 = NOT(operand2); + + Bits result = OR(operand1, operand2); + + X(d, result); + } + + // https://meriac.github.io/archex/A64_v83A_ISA/orr_log_shift.xml + public static void Orr_Rs(bool sf, Bits shift, Bits Rm, Bits imm6, Bits Rn, Bits Rd) + { + /* Decode */ + int d = (int)UInt(Rd); + int n = (int)UInt(Rn); + int m = (int)UInt(Rm); + int datasize = (sf ? 64 : 32); + + /* if sf == '0' && imm6<5> == '1' then ReservedValue(); */ + + ShiftType shift_type = DecodeShift(shift); + int shift_amount = (int)UInt(imm6); + + /* Operation */ + Bits operand1 = X(datasize, n); + Bits operand2 = ShiftReg(datasize, m, shift_type, shift_amount); + + Bits result = OR(operand1, operand2); + + X(d, result); + } + + // https://meriac.github.io/archex/A64_v83A_ISA/rorv.xml + public static void Rorv(bool sf, Bits Rm, Bits Rn, Bits Rd) + { + Bits op2 = "11"; + + /* Decode */ + int d = (int)UInt(Rd); + int n = (int)UInt(Rn); + int m = (int)UInt(Rm); + int datasize = (sf ? 64 : 32); + + ShiftType shift_type = DecodeShift(op2); + + /* Operation */ + Bits operand2 = X(datasize, m); + + Bits result = ShiftReg(datasize, n, shift_type, (int)(UInt(operand2) % datasize)); // BigInteger.Modulus Operator (BigInteger, BigInteger) + + X(d, result); + } + + // https://meriac.github.io/archex/A64_v83A_ISA/sbc.xml + public static void Sbc(bool sf, Bits Rm, Bits Rn, Bits Rd) + { + /* Decode */ + int d = (int)UInt(Rd); + int n = (int)UInt(Rn); + int m = (int)UInt(Rm); + int datasize = (sf ? 64 : 32); + + /* Operation */ + Bits result; + Bits operand1 = X(datasize, n); + Bits operand2 = X(datasize, m); + + operand2 = NOT(operand2); + + (result, _) = AddWithCarry(datasize, operand1, operand2, PSTATE.C); + + X(d, result); + } + + // https://meriac.github.io/archex/A64_v83A_ISA/sbcs.xml + public static void Sbcs(bool sf, Bits Rm, Bits Rn, Bits Rd) + { + /* Decode */ + int d = (int)UInt(Rd); + int n = (int)UInt(Rn); + int m = (int)UInt(Rm); + int datasize = (sf ? 64 : 32); + + /* Operation */ + Bits result; + Bits operand1 = X(datasize, n); + Bits operand2 = X(datasize, m); + Bits nzcv; + + operand2 = NOT(operand2); + + (result, nzcv) = AddWithCarry(datasize, operand1, operand2, PSTATE.C); + + PSTATE.NZCV(nzcv); + + X(d, result); + } + + // https://meriac.github.io/archex/A64_v83A_ISA/sdiv.xml + public static void Sdiv(bool sf, Bits Rm, Bits Rn, Bits Rd) + { + /* Decode */ + int d = (int)UInt(Rd); + int n = (int)UInt(Rn); + int m = (int)UInt(Rm); + int datasize = (sf ? 64 : 32); + + /* Operation */ + BigInteger result; + Bits operand1 = X(datasize, n); + Bits operand2 = X(datasize, m); + + if (IsZero(operand2)) + { + result = (BigInteger)0m; + } + else + { + result = RoundTowardsZero(Real(Int(operand1, false)) / Real(Int(operand2, false))); + } + + X(d, result.SubBigInteger(datasize - 1, 0)); + } + + // https://meriac.github.io/archex/A64_v83A_ISA/sub_addsub_shift.xml + public static void Sub_Rs(bool sf, Bits shift, Bits Rm, Bits imm6, Bits Rn, Bits Rd) + { + /* Decode */ + int d = (int)UInt(Rd); + int n = (int)UInt(Rn); + int m = (int)UInt(Rm); + int datasize = (sf ? 64 : 32); + + /* if shift == '11' then ReservedValue(); */ + /* if sf == '0' && imm6<5> == '1' then ReservedValue(); */ + + ShiftType shift_type = DecodeShift(shift); + int shift_amount = (int)UInt(imm6); + + /* Operation */ + Bits result; + Bits operand1 = X(datasize, n); + Bits operand2 = ShiftReg(datasize, m, shift_type, shift_amount); + + operand2 = NOT(operand2); + + (result, _) = AddWithCarry(datasize, operand1, operand2, true); + + X(d, result); + } + + // https://meriac.github.io/archex/A64_v83A_ISA/subs_addsub_shift.xml + public static void Subs_Rs(bool sf, Bits shift, Bits Rm, Bits imm6, Bits Rn, Bits Rd) + { + /* Decode */ + int d = (int)UInt(Rd); + int n = (int)UInt(Rn); + int m = (int)UInt(Rm); + int datasize = (sf ? 64 : 32); + + /* if shift == '11' then ReservedValue(); */ + /* if sf == '0' && imm6<5> == '1' then ReservedValue(); */ + + ShiftType shift_type = DecodeShift(shift); + int shift_amount = (int)UInt(imm6); + + /* Operation */ + Bits result; + Bits operand1 = X(datasize, n); + Bits operand2 = ShiftReg(datasize, m, shift_type, shift_amount); + Bits nzcv; + + operand2 = NOT(operand2); + + (result, nzcv) = AddWithCarry(datasize, operand1, operand2, true); + + PSTATE.NZCV(nzcv); + + X(d, result); + } + + // https://meriac.github.io/archex/A64_v83A_ISA/udiv.xml + public static void Udiv(bool sf, Bits Rm, Bits Rn, Bits Rd) + { + /* Decode */ + int d = (int)UInt(Rd); + int n = (int)UInt(Rn); + int m = (int)UInt(Rm); + int datasize = (sf ? 64 : 32); + + /* Operation */ + BigInteger result; + Bits operand1 = X(datasize, n); + Bits operand2 = X(datasize, m); + + if (IsZero(operand2)) + { + result = (BigInteger)0m; + } + else + { + result = RoundTowardsZero(Real(Int(operand1, true)) / Real(Int(operand2, true))); + } + + X(d, result.SubBigInteger(datasize - 1, 0)); + } +#endregion + +#region "AluRx" + // https://meriac.github.io/archex/A64_v83A_ISA/add_addsub_ext.xml + public static void Add_Rx(bool sf, Bits Rm, Bits option, Bits imm3, Bits Rn, Bits Rd) + { + /* Decode */ + int d = (int)UInt(Rd); + int n = (int)UInt(Rn); + int m = (int)UInt(Rm); + int datasize = (sf ? 64 : 32); + + ExtendType extend_type = DecodeRegExtend(option); + int shift = (int)UInt(imm3); + + /* if shift > 4 then ReservedValue(); */ + + /* Operation */ + Bits result; + Bits operand1 = (n == 31 ? SP(datasize) : X(datasize, n)); + Bits operand2 = ExtendReg(datasize, m, extend_type, shift); + + (result, _) = AddWithCarry(datasize, operand1, operand2, false); + + if (d == 31) + { + SP(result); + } + else + { + X(d, result); + } + } + + // https://meriac.github.io/archex/A64_v83A_ISA/adds_addsub_ext.xml + public static void Adds_Rx(bool sf, Bits Rm, Bits option, Bits imm3, Bits Rn, Bits Rd) + { + /* Decode */ + int d = (int)UInt(Rd); + int n = (int)UInt(Rn); + int m = (int)UInt(Rm); + int datasize = (sf ? 64 : 32); + + ExtendType extend_type = DecodeRegExtend(option); + int shift = (int)UInt(imm3); + + /* if shift > 4 then ReservedValue(); */ + + /* Operation */ + Bits result; + Bits operand1 = (n == 31 ? SP(datasize) : X(datasize, n)); + Bits operand2 = ExtendReg(datasize, m, extend_type, shift); + Bits nzcv; + + (result, nzcv) = AddWithCarry(datasize, operand1, operand2, false); + + PSTATE.NZCV(nzcv); + + X(d, result); + } + + // https://meriac.github.io/archex/A64_v83A_ISA/sub_addsub_ext.xml + public static void Sub_Rx(bool sf, Bits Rm, Bits option, Bits imm3, Bits Rn, Bits Rd) + { + /* Decode */ + int d = (int)UInt(Rd); + int n = (int)UInt(Rn); + int m = (int)UInt(Rm); + int datasize = (sf ? 64 : 32); + + ExtendType extend_type = DecodeRegExtend(option); + int shift = (int)UInt(imm3); + + /* if shift > 4 then ReservedValue(); */ + + /* Operation */ + Bits result; + Bits operand1 = (n == 31 ? SP(datasize) : X(datasize, n)); + Bits operand2 = ExtendReg(datasize, m, extend_type, shift); + + operand2 = NOT(operand2); + + (result, _) = AddWithCarry(datasize, operand1, operand2, true); + + if (d == 31) + { + SP(result); + } + else + { + X(d, result); + } + } + + // https://meriac.github.io/archex/A64_v83A_ISA/subs_addsub_ext.xml + public static void Subs_Rx(bool sf, Bits Rm, Bits option, Bits imm3, Bits Rn, Bits Rd) + { + /* Decode */ + int d = (int)UInt(Rd); + int n = (int)UInt(Rn); + int m = (int)UInt(Rm); + int datasize = (sf ? 64 : 32); + + ExtendType extend_type = DecodeRegExtend(option); + int shift = (int)UInt(imm3); + + /* if shift > 4 then ReservedValue(); */ + + /* Operation */ + Bits result; + Bits operand1 = (n == 31 ? SP(datasize) : X(datasize, n)); + Bits operand2 = ExtendReg(datasize, m, extend_type, shift); + Bits nzcv; + + operand2 = NOT(operand2); + + (result, nzcv) = AddWithCarry(datasize, operand1, operand2, true); + + PSTATE.NZCV(nzcv); + + X(d, result); + } +#endregion + +#region "Bfm" + // https://meriac.github.io/archex/A64_v83A_ISA/bfm.xml + public static void Bfm(bool sf, bool N, Bits immr, Bits imms, Bits Rn, Bits Rd) + { + /* Decode */ + int d = (int)UInt(Rd); + int n = (int)UInt(Rn); + int datasize = (sf ? 64 : 32); + + int R; + Bits wmask; + Bits tmask; + + /* if sf == '1' && N != '1' then ReservedValue(); */ + /* if sf == '0' && (N != '0' || immr<5> != '0' || imms<5> != '0') then ReservedValue(); */ + + R = (int)UInt(immr); + (wmask, tmask) = DecodeBitMasks(datasize, N, imms, immr, false); + + /* Operation */ + Bits dst = X(datasize, d); + Bits src = X(datasize, n); + + // perform bitfield move on low bits + Bits bot = OR(AND(dst, NOT(wmask)), AND(ROR(src, R), wmask)); + + // combine extension bits and result bits + X(d, OR(AND(dst, NOT(tmask)), AND(bot, tmask))); + } + + // https://meriac.github.io/archex/A64_v83A_ISA/sbfm.xml + public static void Sbfm(bool sf, bool N, Bits immr, Bits imms, Bits Rn, Bits Rd) + { + /* Decode */ + int d = (int)UInt(Rd); + int n = (int)UInt(Rn); + int datasize = (sf ? 64 : 32); + + int R; + int S; + Bits wmask; + Bits tmask; + + /* if sf == '1' && N != '1' then ReservedValue(); */ + /* if sf == '0' && (N != '0' || immr<5> != '0' || imms<5> != '0') then ReservedValue(); */ + + R = (int)UInt(immr); + S = (int)UInt(imms); + (wmask, tmask) = DecodeBitMasks(datasize, N, imms, immr, false); + + /* Operation */ + Bits src = X(datasize, n); + + // perform bitfield move on low bits + Bits bot = AND(ROR(src, R), wmask); + + // determine extension bits (sign, zero or dest register) + Bits top = Replicate(datasize, src[S]); + + // combine extension bits and result bits + X(d, OR(AND(top, NOT(tmask)), AND(bot, tmask))); + } + + // https://meriac.github.io/archex/A64_v83A_ISA/ubfm.xml + public static void Ubfm(bool sf, bool N, Bits immr, Bits imms, Bits Rn, Bits Rd) + { + /* Decode */ + int d = (int)UInt(Rd); + int n = (int)UInt(Rn); + int datasize = (sf ? 64 : 32); + + int R; + Bits wmask; + Bits tmask; + + /* if sf == '1' && N != '1' then ReservedValue(); */ + /* if sf == '0' && (N != '0' || immr<5> != '0' || imms<5> != '0') then ReservedValue(); */ + + R = (int)UInt(immr); + (wmask, tmask) = DecodeBitMasks(datasize, N, imms, immr, false); + + /* Operation */ + Bits src = X(datasize, n); + + // perform bitfield move on low bits + Bits bot = AND(ROR(src, R), wmask); + + // combine extension bits and result bits + X(d, AND(bot, tmask)); + } +#endregion + +#region "CcmpImm" + // https://meriac.github.io/archex/A64_v83A_ISA/ccmn_imm.xml + public static void Ccmn_Imm(bool sf, Bits imm5, Bits cond, Bits Rn, Bits nzcv) + { + /* Decode */ + int n = (int)UInt(Rn); + int datasize = (sf ? 64 : 32); + + Bits flags = nzcv; + Bits imm = ZeroExtend(imm5, datasize); + + /* Operation */ + Bits operand1 = X(datasize, n); + + if (ConditionHolds(cond)) + { + (_, flags) = AddWithCarry(datasize, operand1, imm, false); + } + + PSTATE.NZCV(flags); + } + + // https://meriac.github.io/archex/A64_v83A_ISA/ccmp_imm.xml + public static void Ccmp_Imm(bool sf, Bits imm5, Bits cond, Bits Rn, Bits nzcv) + { + /* Decode */ + int n = (int)UInt(Rn); + int datasize = (sf ? 64 : 32); + + Bits flags = nzcv; + Bits imm = ZeroExtend(imm5, datasize); + + /* Operation */ + Bits operand1 = X(datasize, n); + Bits operand2; + + if (ConditionHolds(cond)) + { + operand2 = NOT(imm); + (_, flags) = AddWithCarry(datasize, operand1, operand2, true); + } + + PSTATE.NZCV(flags); + } +#endregion + +#region "CcmpReg" + // https://meriac.github.io/archex/A64_v83A_ISA/ccmn_reg.xml + public static void Ccmn_Reg(bool sf, Bits Rm, Bits cond, Bits Rn, Bits nzcv) + { + /* Decode */ + int n = (int)UInt(Rn); + int m = (int)UInt(Rm); + int datasize = (sf ? 64 : 32); + + Bits flags = nzcv; + + /* Operation */ + Bits operand1 = X(datasize, n); + Bits operand2 = X(datasize, m); + + if (ConditionHolds(cond)) + { + (_, flags) = AddWithCarry(datasize, operand1, operand2, false); + } + + PSTATE.NZCV(flags); + } + + // https://meriac.github.io/archex/A64_v83A_ISA/ccmp_reg.xml + public static void Ccmp_Reg(bool sf, Bits Rm, Bits cond, Bits Rn, Bits nzcv) + { + /* Decode */ + int n = (int)UInt(Rn); + int m = (int)UInt(Rm); + int datasize = (sf ? 64 : 32); + + Bits flags = nzcv; + + /* Operation */ + Bits operand1 = X(datasize, n); + Bits operand2 = X(datasize, m); + + if (ConditionHolds(cond)) + { + operand2 = NOT(operand2); + (_, flags) = AddWithCarry(datasize, operand1, operand2, true); + } + + PSTATE.NZCV(flags); + } +#endregion + +#region "Csel" + // https://meriac.github.io/archex/A64_v83A_ISA/csel.xml + public static void Csel(bool sf, Bits Rm, Bits cond, Bits Rn, Bits Rd) + { + /* Decode */ + int d = (int)UInt(Rd); + int n = (int)UInt(Rn); + int m = (int)UInt(Rm); + int datasize = (sf ? 64 : 32); + + /* Operation */ + Bits result; + Bits operand1 = X(datasize, n); + Bits operand2 = X(datasize, m); + + if (ConditionHolds(cond)) + { + result = operand1; + } + else + { + result = operand2; + } + + X(d, result); + } + + // https://meriac.github.io/archex/A64_v83A_ISA/csinc.xml + public static void Csinc(bool sf, Bits Rm, Bits cond, Bits Rn, Bits Rd) + { + /* Decode */ + int d = (int)UInt(Rd); + int n = (int)UInt(Rn); + int m = (int)UInt(Rm); + int datasize = (sf ? 64 : 32); + + /* Operation */ + Bits result; + Bits operand1 = X(datasize, n); + Bits operand2 = X(datasize, m); + + if (ConditionHolds(cond)) + { + result = operand1; + } + else + { + result = operand2 + 1; + } + + X(d, result); + } + + // https://meriac.github.io/archex/A64_v83A_ISA/csinv.xml + public static void Csinv(bool sf, Bits Rm, Bits cond, Bits Rn, Bits Rd) + { + /* Decode */ + int d = (int)UInt(Rd); + int n = (int)UInt(Rn); + int m = (int)UInt(Rm); + int datasize = (sf ? 64 : 32); + + /* Operation */ + Bits result; + Bits operand1 = X(datasize, n); + Bits operand2 = X(datasize, m); + + if (ConditionHolds(cond)) + { + result = operand1; + } + else + { + result = NOT(operand2); + } + + X(d, result); + } + + // https://meriac.github.io/archex/A64_v83A_ISA/csneg.xml + public static void Csneg(bool sf, Bits Rm, Bits cond, Bits Rn, Bits Rd) + { + /* Decode */ + int d = (int)UInt(Rd); + int n = (int)UInt(Rn); + int m = (int)UInt(Rm); + int datasize = (sf ? 64 : 32); + + /* Operation */ + Bits result; + Bits operand1 = X(datasize, n); + Bits operand2 = X(datasize, m); + + if (ConditionHolds(cond)) + { + result = operand1; + } + else + { + result = NOT(operand2); + result = result + 1; + } + + X(d, result); + } +#endregion + +#region "Mov" + // https://meriac.github.io/archex/A64_v83A_ISA/movk.xml + public static void Movk(bool sf, Bits hw, Bits imm16, Bits Rd) + { + /* Decode */ + int d = (int)UInt(Rd); + int datasize = (sf ? 64 : 32); + + /* if sf == '0' && hw<1> == '1' then UnallocatedEncoding(); */ + + int pos = (int)UInt(Bits.Concat(hw, "0000")); + + /* Operation */ + Bits result = X(datasize, d); + + result[pos + 15, pos] = imm16; + + X(d, result); + } + + // https://meriac.github.io/archex/A64_v83A_ISA/movn.xml + public static void Movn(bool sf, Bits hw, Bits imm16, Bits Rd) + { + /* Decode */ + int d = (int)UInt(Rd); + int datasize = (sf ? 64 : 32); + + /* if sf == '0' && hw<1> == '1' then UnallocatedEncoding(); */ + + int pos = (int)UInt(Bits.Concat(hw, "0000")); + + /* Operation */ + Bits result = Zeros(datasize); + + result[pos + 15, pos] = imm16; + result = NOT(result); + + X(d, result); + } + + // https://meriac.github.io/archex/A64_v83A_ISA/movz.xml + public static void Movz(bool sf, Bits hw, Bits imm16, Bits Rd) + { + /* Decode */ + int d = (int)UInt(Rd); + int datasize = (sf ? 64 : 32); + + /* if sf == '0' && hw<1> == '1' then UnallocatedEncoding(); */ + + int pos = (int)UInt(Bits.Concat(hw, "0000")); + + /* Operation */ + Bits result = Zeros(datasize); + + result[pos + 15, pos] = imm16; + + X(d, result); + } +#endregion + +#region "Mul" + // https://meriac.github.io/archex/A64_v83A_ISA/madd.xml + public static void Madd(bool sf, Bits Rm, Bits Ra, Bits Rn, Bits Rd) + { + /* Decode */ + int d = (int)UInt(Rd); + int n = (int)UInt(Rn); + int m = (int)UInt(Rm); + int a = (int)UInt(Ra); + int datasize = (sf ? 64 : 32); + + /* Operation */ + Bits operand1 = X(datasize, n); + Bits operand2 = X(datasize, m); + Bits operand3 = X(datasize, a); + + BigInteger result = UInt(operand3) + (UInt(operand1) * UInt(operand2)); + + X(d, result.SubBigInteger(datasize - 1, 0)); + } + + // https://meriac.github.io/archex/A64_v83A_ISA/msub.xml + public static void Msub(bool sf, Bits Rm, Bits Ra, Bits Rn, Bits Rd) + { + /* Decode */ + int d = (int)UInt(Rd); + int n = (int)UInt(Rn); + int m = (int)UInt(Rm); + int a = (int)UInt(Ra); + int datasize = (sf ? 64 : 32); + + /* Operation */ + Bits operand1 = X(datasize, n); + Bits operand2 = X(datasize, m); + Bits operand3 = X(datasize, a); + + BigInteger result = UInt(operand3) - (UInt(operand1) * UInt(operand2)); + + X(d, result.SubBigInteger(datasize - 1, 0)); + } + + // https://meriac.github.io/archex/A64_v83A_ISA/smaddl.xml + public static void Smaddl(Bits Rm, Bits Ra, Bits Rn, Bits Rd) + { + /* Decode */ + int d = (int)UInt(Rd); + int n = (int)UInt(Rn); + int m = (int)UInt(Rm); + int a = (int)UInt(Ra); + + /* Operation */ + Bits operand1 = X(32, n); + Bits operand2 = X(32, m); + Bits operand3 = X(64, a); + + BigInteger result = Int(operand3, false) + (Int(operand1, false) * Int(operand2, false)); + + X(d, result.SubBigInteger(63, 0)); + } + + // https://meriac.github.io/archex/A64_v83A_ISA/umaddl.xml + public static void Umaddl(Bits Rm, Bits Ra, Bits Rn, Bits Rd) + { + /* Decode */ + int d = (int)UInt(Rd); + int n = (int)UInt(Rn); + int m = (int)UInt(Rm); + int a = (int)UInt(Ra); + + /* Operation */ + Bits operand1 = X(32, n); + Bits operand2 = X(32, m); + Bits operand3 = X(64, a); + + BigInteger result = Int(operand3, true) + (Int(operand1, true) * Int(operand2, true)); + + X(d, result.SubBigInteger(63, 0)); + } + + // https://meriac.github.io/archex/A64_v83A_ISA/smsubl.xml + public static void Smsubl(Bits Rm, Bits Ra, Bits Rn, Bits Rd) + { + /* Decode */ + int d = (int)UInt(Rd); + int n = (int)UInt(Rn); + int m = (int)UInt(Rm); + int a = (int)UInt(Ra); + + /* Operation */ + Bits operand1 = X(32, n); + Bits operand2 = X(32, m); + Bits operand3 = X(64, a); + + BigInteger result = Int(operand3, false) - (Int(operand1, false) * Int(operand2, false)); + + X(d, result.SubBigInteger(63, 0)); + } + + // https://meriac.github.io/archex/A64_v83A_ISA/umsubl.xml + public static void Umsubl(Bits Rm, Bits Ra, Bits Rn, Bits Rd) + { + /* Decode */ + int d = (int)UInt(Rd); + int n = (int)UInt(Rn); + int m = (int)UInt(Rm); + int a = (int)UInt(Ra); + + /* Operation */ + Bits operand1 = X(32, n); + Bits operand2 = X(32, m); + Bits operand3 = X(64, a); + + BigInteger result = Int(operand3, true) - (Int(operand1, true) * Int(operand2, true)); + + X(d, result.SubBigInteger(63, 0)); + } + + // https://meriac.github.io/archex/A64_v83A_ISA/smulh.xml + public static void Smulh(Bits Rm, Bits Rn, Bits Rd) + { + /* Decode */ + int d = (int)UInt(Rd); + int n = (int)UInt(Rn); + int m = (int)UInt(Rm); + + /* Operation */ + Bits operand1 = X(64, n); + Bits operand2 = X(64, m); + + BigInteger result = Int(operand1, false) * Int(operand2, false); + + X(d, result.SubBigInteger(127, 64)); + } + + // https://meriac.github.io/archex/A64_v83A_ISA/umulh.xml + public static void Umulh(Bits Rm, Bits Rn, Bits Rd) + { + /* Decode */ + int d = (int)UInt(Rd); + int n = (int)UInt(Rn); + int m = (int)UInt(Rm); + + /* Operation */ + Bits operand1 = X(64, n); + Bits operand2 = X(64, m); + + BigInteger result = Int(operand1, true) * Int(operand2, true); + + X(d, result.SubBigInteger(127, 64)); + } +#endregion + } + + /* + internal static class Advanced + { + } + */ +} diff --git a/Ryujinx.Tests/Cpu/Tester/Pseudocode.cs b/Ryujinx.Tests/Cpu/Tester/Pseudocode.cs new file mode 100644 index 000000000..1da17c497 --- /dev/null +++ b/Ryujinx.Tests/Cpu/Tester/Pseudocode.cs @@ -0,0 +1,958 @@ +// https://github.com/LDj3SNuD/ARM_v8-A_AArch64_Instructions_Tester/blob/master/Tester/Pseudocode.cs + +// https://meriac.github.io/archex/A64_v83A_ISA/shared_pseudocode.xml +// https://alastairreid.github.io/asl-lexical-syntax/ + +// | ------------------------|----------------------------------- | +// | ASL | C# | +// | ------------------------|----------------------------------- | +// | bit, bits(1); boolean | bool | +// | bits | Bits | +// | integer | BigInteger, int | +// | real | decimal | +// | ------------------------|----------------------------------- | +// | '0'; FALSE | false | +// | '1'; TRUE | true | +// | '010' | "010" | +// | bitsX IN {bitsY, bitsZ} | (bitsX == bitsY || bitsX == bitsZ) | +// | DIV | / | +// | MOD | % | +// | ------------------------|----------------------------------- | + +using System; +using System.Numerics; + +namespace Ryujinx.Tests.Cpu.Tester +{ + using Types; + + using static Shared; + + internal static class AArch64 + { +#region "exceptions/exceptions/" + /* #AArch64.ResetControlRegisters.1 */ + public static void ResetControlRegisters(bool cold_reset) + { + PSTATE.N = cold_reset; + PSTATE.Z = cold_reset; + PSTATE.C = cold_reset; + PSTATE.V = cold_reset; + } + + /* */ + public static void TakeReset(bool cold_reset) + { + /* assert !HighestELUsingAArch32(); */ + + // Enter the highest implemented Exception level in AArch64 state + if (HaveEL(EL3)) + { + PSTATE.EL = EL3; + } + else if (HaveEL(EL2)) + { + PSTATE.EL = EL2; + } + else + { + PSTATE.EL = EL1; + } + + // Reset the system registers and other system components + AArch64.ResetControlRegisters(cold_reset); + + // Reset all other PSTATE fields + PSTATE.SP = true; // Select stack pointer + + // All registers, bits and fields not reset by the above pseudocode or by the BranchTo() call + // below are UNKNOWN bitstrings after reset. In particular, the return information registers + // ELR_ELx and SPSR_ELx have UNKNOWN values, so that it + // is impossible to return from a reset in an architecturally defined way. + AArch64.ResetGeneralRegisters(); + AArch64.ResetSpecialRegisters(); + } +#endregion + +#region "functions/registers/" + /* #AArch64.ResetGeneralRegisters.0 */ + public static void ResetGeneralRegisters() + { + for (int i = 0; i <= 30; i++) + { + /* X[i] = bits(64) UNKNOWN; */ + _R[i].SetAll(false); + } + } + + /* #AArch64.ResetSpecialRegisters.0 */ + public static void ResetSpecialRegisters() + { + // AArch64 special registers + /* SP_EL0 = bits(64) UNKNOWN; */ + SP_EL0.SetAll(false); + /* SP_EL1 = bits(64) UNKNOWN; */ + SP_EL1.SetAll(false); + } + + // #impl-aarch64.SP.write.0 + public static void SP(Bits value) + { + /* int width = value.Count; */ + + /* assert width IN {32,64}; */ + + if (!PSTATE.SP) + { + SP_EL0 = ZeroExtend(64, value); + } + else + { + switch (PSTATE.EL) + { + case Bits bits when bits == EL0: + SP_EL0 = ZeroExtend(64, value); + break; + default: + case Bits bits when bits == EL1: + SP_EL1 = ZeroExtend(64, value); + break; + /*case Bits bits when bits == EL2: + SP_EL2 = ZeroExtend(64, value); + break; + case Bits bits when bits == EL3: + SP_EL3 = ZeroExtend(64, value); + break;*/ + } + } + } + + // #impl-aarch64.SP.read.0 + public static Bits SP(int width) + { + /* assert width IN {8,16,32,64}; */ + + if (!PSTATE.SP) + { + return SP_EL0[width - 1, 0]; + } + else + { + switch (PSTATE.EL) + { + case Bits bits when bits == EL0: + return SP_EL0[width - 1, 0]; + default: + case Bits bits when bits == EL1: + return SP_EL1[width - 1, 0]; + /*case Bits bits when bits == EL2: + return SP_EL2[width - 1, 0]; + case Bits bits when bits == EL3: + return SP_EL3[width - 1, 0];*/ + } + } + } + + // #impl-aarch64.X.write.1 + public static void X(int n, Bits value) + { + /* int width = value.Count; */ + + /* assert n >= 0 && n <= 31; */ + /* assert width IN {32,64}; */ + + if (n != 31) + { + _R[n] = ZeroExtend(64, value); + } + } + + /* #impl-aarch64.X.read.1 */ + public static Bits X(int width, int n) + { + /* assert n >= 0 && n <= 31; */ + /* assert width IN {8,16,32,64}; */ + + if (n != 31) + { + return _R[n][width - 1, 0]; + } + else + { + return Zeros(width); + } + } +#endregion + +#region "instrs/extendreg/" + /* #impl-aarch64.DecodeRegExtend.1 */ + public static ExtendType DecodeRegExtend(Bits op) + { + switch (op) + { + default: + case Bits bits when bits == "000": + return ExtendType.ExtendType_UXTB; + case Bits bits when bits == "001": + return ExtendType.ExtendType_UXTH; + case Bits bits when bits == "010": + return ExtendType.ExtendType_UXTW; + case Bits bits when bits == "011": + return ExtendType.ExtendType_UXTX; + case Bits bits when bits == "100": + return ExtendType.ExtendType_SXTB; + case Bits bits when bits == "101": + return ExtendType.ExtendType_SXTH; + case Bits bits when bits == "110": + return ExtendType.ExtendType_SXTW; + case Bits bits when bits == "111": + return ExtendType.ExtendType_SXTX; + } + } + + /* #impl-aarch64.ExtendReg.3 */ + public static Bits ExtendReg(int N, int reg, ExtendType type, int shift) + { + /* assert shift >= 0 && shift <= 4; */ + Bits val = X(N, reg); + bool unsigned; + int len; + + switch (type) + { + default: + case ExtendType.ExtendType_SXTB: + unsigned = false; len = 8; + break; + case ExtendType.ExtendType_SXTH: + unsigned = false; len = 16; + break; + case ExtendType.ExtendType_SXTW: + unsigned = false; len = 32; + break; + case ExtendType.ExtendType_SXTX: + unsigned = false; len = 64; + break; + case ExtendType.ExtendType_UXTB: + unsigned = true; len = 8; + break; + case ExtendType.ExtendType_UXTH: + unsigned = true; len = 16; + break; + case ExtendType.ExtendType_UXTW: + unsigned = true; len = 32; + break; + case ExtendType.ExtendType_UXTX: + unsigned = true; len = 64; + break; + } + + // Note the extended width of the intermediate value and + // that sign extension occurs from bit , not + // from bit . This is equivalent to the instruction + // [SU]BFIZ Rtmp, Rreg, #shift, #len + // It may also be seen as a sign/zero extend followed by a shift: + // LSL(Extend(val, N, unsigned), shift); + + len = Min(len, N - shift); + return Extend(Bits.Concat(val[len - 1, 0], Zeros(shift)), N, unsigned); + } + + // #ExtendType + public enum ExtendType {ExtendType_SXTB, ExtendType_SXTH, ExtendType_SXTW, ExtendType_SXTX, + ExtendType_UXTB, ExtendType_UXTH, ExtendType_UXTW, ExtendType_UXTX}; +#endregion + +#region "instrs/integer/bitmasks/" + /* #impl-aarch64.DecodeBitMasks.4 */ + public static (Bits, Bits) DecodeBitMasks(int M, bool immN, Bits imms, Bits immr, bool immediate) + { + Bits tmask, wmask; + Bits tmask_and, wmask_and; + Bits tmask_or, wmask_or; + Bits levels; + + // Compute log2 of element size + // 2^len must be in range [2, M] + int len = HighestSetBit(Bits.Concat(immN, NOT(imms))); + /* if len < 1 then ReservedValue(); */ + /* assert M >= (1 << len); */ + + // Determine S, R and S - R parameters + levels = ZeroExtend(Ones(len), 6); + + // For logical immediates an all-ones value of S is reserved + // since it would generate a useless all-ones result (many times) + /* if immediate && (imms AND levels) == levels then ReservedValue(); */ + + BigInteger S = UInt(AND(imms, levels)); + BigInteger R = UInt(AND(immr, levels)); + BigInteger diff = S - R; // 6-bit subtract with borrow + + // Compute "top mask" + tmask_and = OR(diff.SubBigInteger(5, 0), NOT(levels)); + tmask_or = AND(diff.SubBigInteger(5, 0), levels); + + tmask = Ones(64); + tmask = OR(AND(tmask, Replicate(Bits.Concat(Replicate(tmask_and[0], 1), Ones( 1)), 32)), Replicate(Bits.Concat(Zeros( 1), Replicate(tmask_or[0], 1)), 32)); + tmask = OR(AND(tmask, Replicate(Bits.Concat(Replicate(tmask_and[1], 2), Ones( 2)), 16)), Replicate(Bits.Concat(Zeros( 2), Replicate(tmask_or[1], 2)), 16)); + tmask = OR(AND(tmask, Replicate(Bits.Concat(Replicate(tmask_and[2], 4), Ones( 4)), 8)), Replicate(Bits.Concat(Zeros( 4), Replicate(tmask_or[2], 4)), 8)); + tmask = OR(AND(tmask, Replicate(Bits.Concat(Replicate(tmask_and[3], 8), Ones( 8)), 4)), Replicate(Bits.Concat(Zeros( 8), Replicate(tmask_or[3], 8)), 4)); + tmask = OR(AND(tmask, Replicate(Bits.Concat(Replicate(tmask_and[4], 16), Ones(16)), 2)), Replicate(Bits.Concat(Zeros(16), Replicate(tmask_or[4], 16)), 2)); + tmask = OR(AND(tmask, Replicate(Bits.Concat(Replicate(tmask_and[5], 32), Ones(32)), 1)), Replicate(Bits.Concat(Zeros(32), Replicate(tmask_or[5], 32)), 1)); + + // Compute "wraparound mask" + wmask_and = OR(immr, NOT(levels)); + wmask_or = AND(immr, levels); + + wmask = Zeros(64); + wmask = OR(AND(wmask, Replicate(Bits.Concat(Ones( 1), Replicate(wmask_and[0], 1)), 32)), Replicate(Bits.Concat(Replicate(wmask_or[0], 1), Zeros( 1)), 32)); + wmask = OR(AND(wmask, Replicate(Bits.Concat(Ones( 2), Replicate(wmask_and[1], 2)), 16)), Replicate(Bits.Concat(Replicate(wmask_or[1], 2), Zeros( 2)), 16)); + wmask = OR(AND(wmask, Replicate(Bits.Concat(Ones( 4), Replicate(wmask_and[2], 4)), 8)), Replicate(Bits.Concat(Replicate(wmask_or[2], 4), Zeros( 4)), 8)); + wmask = OR(AND(wmask, Replicate(Bits.Concat(Ones( 8), Replicate(wmask_and[3], 8)), 4)), Replicate(Bits.Concat(Replicate(wmask_or[3], 8), Zeros( 8)), 4)); + wmask = OR(AND(wmask, Replicate(Bits.Concat(Ones(16), Replicate(wmask_and[4], 16)), 2)), Replicate(Bits.Concat(Replicate(wmask_or[4], 16), Zeros(16)), 2)); + wmask = OR(AND(wmask, Replicate(Bits.Concat(Ones(32), Replicate(wmask_and[5], 32)), 1)), Replicate(Bits.Concat(Replicate(wmask_or[5], 32), Zeros(32)), 1)); + + if (diff.SubBigInteger(6)) // borrow from S - R + { + wmask = AND(wmask, tmask); + } + else + { + wmask = OR(wmask, tmask); + } + + return (wmask[M - 1, 0], tmask[M - 1, 0]); + } +#endregion + +#region "instrs/integer/shiftreg/" + /* #impl-aarch64.DecodeShift.1 */ + public static ShiftType DecodeShift(Bits op) + { + switch (op) + { + default: + case Bits bits when bits == "00": + return ShiftType.ShiftType_LSL; + case Bits bits when bits == "01": + return ShiftType.ShiftType_LSR; + case Bits bits when bits == "10": + return ShiftType.ShiftType_ASR; + case Bits bits when bits == "11": + return ShiftType.ShiftType_ROR; + } + } + + /* #impl-aarch64.ShiftReg.3 */ + public static Bits ShiftReg(int N, int reg, ShiftType type, int amount) + { + Bits result = X(N, reg); + + switch (type) + { + default: + case ShiftType.ShiftType_LSL: + result = LSL(result, amount); + break; + case ShiftType.ShiftType_LSR: + result = LSR(result, amount); + break; + case ShiftType.ShiftType_ASR: + result = ASR(result, amount); + break; + case ShiftType.ShiftType_ROR: + result = ROR(result, amount); + break; + } + + return result; + } + + // #ShiftType + public enum ShiftType {ShiftType_LSL, ShiftType_LSR, ShiftType_ASR, ShiftType_ROR}; +#endregion + } + + internal static class Shared + { + static Shared() + { + _R = new Bits[31]; + for (int i = 0; i <= 30; i++) + { + _R[i] = new Bits(64, false); + } + + SP_EL0 = new Bits(64, false); + SP_EL1 = new Bits(64, false); + + PSTATE.N = false; + PSTATE.Z = false; + PSTATE.C = false; + PSTATE.V = false; + PSTATE.EL = EL1; + PSTATE.SP = true; + } + +#region "functions/common/" + /* */ + public static Bits AND(Bits x, Bits y) + { + return x.And(y); + } + + // #impl-shared.ASR.2 + public static Bits ASR(Bits x, int shift) + { + int N = x.Count; + + /* assert shift >= 0; */ + + Bits result; + + if (shift == 0) + { + result = new Bits(x); + } + else + { + (result, _) = ASR_C(x, shift); + } + + return result; + } + + // #impl-shared.ASR_C.2 + public static (Bits, bool) ASR_C(Bits x, int shift) + { + int N = x.Count; + + /* assert shift > 0; */ + + Bits extended_x = SignExtend(x, shift + N); + Bits result = extended_x[shift + N - 1, shift]; + bool carry_out = extended_x[shift - 1]; + + return (result, carry_out); + } + + // #impl-shared.CountLeadingSignBits.1 + public static int CountLeadingSignBits(Bits x) + { + int N = x.Count; + + return CountLeadingZeroBits(EOR(x[N - 1, 1], x[N - 2, 0])); + } + + // #impl-shared.CountLeadingZeroBits.1 + public static int CountLeadingZeroBits(Bits x) + { + int N = x.Count; + + return (N - 1 - HighestSetBit(x)); + } + + /* */ + public static Bits EOR(Bits x, Bits y) + { + return x.Xor(y); + } + + // #impl-shared.Extend.3 + public static Bits Extend(Bits x, int N, bool unsigned) + { + if (unsigned) + { + return ZeroExtend(x, N); + } + else + { + return SignExtend(x, N); + } + } + + /* #impl-shared.Extend.2 */ + public static Bits Extend(int N, Bits x, bool unsigned) + { + return Extend(x, N, unsigned); + } + + // #impl-shared.HighestSetBit.1 + public static int HighestSetBit(Bits x) + { + int N = x.Count; + + for (int i = N - 1; i >= 0; i--) + { + if (x[i]) + { + return i; + } + } + + return -1; + } + + // #impl-shared.Int.2 + public static BigInteger Int(Bits x, bool unsigned) + { + return (unsigned ? UInt(x) : SInt(x)); + } + + // #impl-shared.IsOnes.1 + public static bool IsOnes(Bits x) + { + int N = x.Count; + + return (x == Ones(N)); + } + + // #impl-shared.IsZero.1 + public static bool IsZero(Bits x) + { + int N = x.Count; + + return (x == Zeros(N)); + } + + // #impl-shared.IsZeroBit.1 + public static bool IsZeroBit(Bits x) + { + return IsZero(x); + } + + // #impl-shared.LSL.2 + public static Bits LSL(Bits x, int shift) + { + int N = x.Count; + + /* assert shift >= 0; */ + + Bits result; + + if (shift == 0) + { + result = new Bits(x); + } + else + { + (result, _) = LSL_C(x, shift); + } + + return result; + } + + // #impl-shared.LSL_C.2 + public static (Bits, bool) LSL_C(Bits x, int shift) + { + int N = x.Count; + + /* assert shift > 0; */ + + Bits extended_x = Bits.Concat(x, Zeros(shift)); + Bits result = extended_x[N - 1, 0]; + bool carry_out = extended_x[N]; + + return (result, carry_out); + } + + // #impl-shared.LSR.2 + public static Bits LSR(Bits x, int shift) + { + int N = x.Count; + + /* assert shift >= 0; */ + + Bits result; + + if (shift == 0) + { + result = new Bits(x); + } + else + { + (result, _) = LSR_C(x, shift); + } + + return result; + } + + // #impl-shared.LSR_C.2 + public static (Bits, bool) LSR_C(Bits x, int shift) + { + int N = x.Count; + + /* assert shift > 0; */ + + Bits extended_x = ZeroExtend(x, shift + N); + Bits result = extended_x[shift + N - 1, shift]; + bool carry_out = extended_x[shift - 1]; + + return (result, carry_out); + } + + // #impl-shared.Min.2 + public static int Min(int a, int b) + { + if (a <= b) + { + return a; + } + else + { + return b; + } + } + + /* #impl-shared.NOT.1 */ + public static Bits NOT(Bits x) + { + return x.Not(); + } + + // #impl-shared.Ones.1 + public static Bits Ones(int N) + { + return Replicate(true, N); + } + + /* */ + public static Bits OR(Bits x, Bits y) + { + return x.Or(y); + } + + /* */ + public static decimal Real(BigInteger value) + { + return (decimal)value; + } + + // #impl-shared.ROR.2 + public static Bits ROR(Bits x, int shift) + { + /* assert shift >= 0; */ + + Bits result; + + if (shift == 0) + { + result = new Bits(x); + } + else + { + (result, _) = ROR_C(x, shift); + } + + return result; + } + + // #impl-shared.ROR_C.2 + public static (Bits, bool) ROR_C(Bits x, int shift) + { + int N = x.Count; + + /* assert shift != 0; */ + + int m = shift % N; + Bits result = OR(LSR(x, m), LSL(x, N - m)); + bool carry_out = result[N - 1]; + + return (result, carry_out); + } + + /* #impl-shared.Replicate.1 */ + public static Bits Replicate(int N, Bits x) + { + int M = x.Count; + + /* assert N MOD M == 0; */ + + return Replicate(x, N / M); + } + + /* #impl-shared.Replicate.2 */ + public static Bits Replicate(Bits x, int N) + { + int M = x.Count; + + bool[] dst = new bool[M * N]; + + for (int i = 0; i < N; i++) + { + x.CopyTo(dst, i * M); + } + + return new Bits(dst); + } + + /* #impl-shared.RoundDown.1 */ + public static BigInteger RoundDown(decimal x) + { + return (BigInteger)Decimal.Floor(x); + } + + // #impl-shared.RoundTowardsZero.1 + public static BigInteger RoundTowardsZero(decimal x) + { + if (x == 0.0m) + { + return (BigInteger)0m; + } + else if (x >= 0.0m) + { + return RoundDown(x); + } + else + { + return RoundUp(x); + } + } + + /* #impl-shared.RoundUp.1 */ + public static BigInteger RoundUp(decimal x) + { + return (BigInteger)Decimal.Ceiling(x); + } + + // #impl-shared.SInt.1 + public static BigInteger SInt(Bits x) + { + int N = x.Count; + + BigInteger result = 0; + + for (int i = 0; i <= N - 1; i++) + { + if (x[i]) + { + result = result + BigInteger.Pow(2, i); + } + } + + if (x[N - 1]) + { + result = result - BigInteger.Pow(2, N); + } + + return result; + } + + // #impl-shared.SignExtend.2 + public static Bits SignExtend(Bits x, int N) + { + int M = x.Count; + + /* assert N >= M; */ + + return Bits.Concat(Replicate(x[M - 1], N - M), x); + } + + /* #impl-shared.SignExtend.1 */ + public static Bits SignExtend(int N, Bits x) + { + return SignExtend(x, N); + } + + // #impl-shared.UInt.1 + public static BigInteger UInt(Bits x) + { + int N = x.Count; + + BigInteger result = 0; + + for (int i = 0; i <= N - 1; i++) + { + if (x[i]) + { + result = result + BigInteger.Pow(2, i); + } + } + + return result; + } + + // #impl-shared.ZeroExtend.2 + public static Bits ZeroExtend(Bits x, int N) + { + int M = x.Count; + + /* assert N >= M; */ + + return Bits.Concat(Zeros(N - M), x); + } + + /* #impl-shared.ZeroExtend.1 */ + public static Bits ZeroExtend(int N, Bits x) + { + return ZeroExtend(x, N); + } + + // #impl-shared.Zeros.1 + /* #impl-shared.Zeros.0 */ + public static Bits Zeros(int N) + { + return Replicate(false, N); + } +#endregion + +#region "functions/crc/" + // #impl-shared.BitReverse.1 + public static Bits BitReverse(Bits data) + { + int N = data.Count; + + Bits result = new Bits(N); + + for (int i = 0; i <= N - 1; i++) + { + result[N - i - 1] = data[i]; + } + + return result; + } + + // #impl-shared.Poly32Mod2.2 + public static Bits Poly32Mod2(Bits _data, Bits poly) + { + int N = _data.Count; + + /* assert N > 32; */ + + Bits data = new Bits(_data); + + for (int i = N - 1; i >= 32; i--) + { + if (data[i]) + { + data[i - 1, 0] = EOR(data[i - 1, 0], Bits.Concat(poly, Zeros(i - 32))); + } + } + + return data[31, 0]; + } +#endregion + +#region "functions/integer/" + /* #impl-shared.AddWithCarry.3 */ + public static (Bits, Bits) AddWithCarry(int N, Bits x, Bits y, bool carry_in) + { + BigInteger unsigned_sum = UInt(x) + UInt(y) + UInt(carry_in); + BigInteger signed_sum = SInt(x) + SInt(y) + UInt(carry_in); + + Bits result = unsigned_sum.SubBigInteger(N - 1, 0); // same value as signed_sum + + bool n = result[N - 1]; + bool z = IsZero(result); + bool c = !(UInt(result) == unsigned_sum); + bool v = !(SInt(result) == signed_sum); + + return (result, Bits.Concat(n, z, c, v)); + } +#endregion + +#region "functions/registers/" + public static readonly Bits[] _R; + + public static Bits SP_EL0; + public static Bits SP_EL1; +#endregion + +#region "functions/system/" + // #impl-shared.ConditionHolds.1 + public static bool ConditionHolds(Bits cond) + { + bool result; + + // Evaluate base condition. + switch (cond[3, 1]) + { + case Bits bits when bits == "000": + result = (PSTATE.Z == true); // EQ or NE + break; + case Bits bits when bits == "001": + result = (PSTATE.C == true); // CS or CC + break; + case Bits bits when bits == "010": + result = (PSTATE.N == true); // MI or PL + break; + case Bits bits when bits == "011": + result = (PSTATE.V == true); // VS or VC + break; + case Bits bits when bits == "100": + result = (PSTATE.C == true && PSTATE.Z == false); // HI or LS + break; + case Bits bits when bits == "101": + result = (PSTATE.N == PSTATE.V); // GE or LT + break; + case Bits bits when bits == "110": + result = (PSTATE.N == PSTATE.V && PSTATE.Z == false); // GT or LE + break; + default: + case Bits bits when bits == "111": + result = true; // AL + break; + } + + // Condition flag values in the set '111x' indicate always true + // Otherwise, invert condition if necessary. + if (cond[0] == true && cond != "1111") + { + result = !result; + } + + return result; + } + + // #EL3 + public static readonly Bits EL3 = "11"; + // #EL2 + public static readonly Bits EL2 = "10"; + // #EL1 + public static readonly Bits EL1 = "01"; + // #EL0 + public static readonly Bits EL0 = "00"; + + /* #impl-shared.HaveEL.1 */ + public static bool HaveEL(Bits el) + { + if (el == EL1 || el == EL0) + { + return true; // EL1 and EL0 must exist + } + + return false; + } + + public static ProcState PSTATE; + + /* #ProcState */ + internal struct ProcState + { + public void NZCV(Bits nzcv) // ASL: ".<,,,>". + { + N = nzcv[3]; + Z = nzcv[2]; + C = nzcv[1]; + V = nzcv[0]; + } + + public void NZCV(bool n, bool z, bool c, bool v) // ASL: ".<,,,>". + { + N = n; + Z = z; + C = c; + V = v; + } + + public bool N; // Negative condition flag + public bool Z; // Zero condition flag + public bool C; // Carry condition flag + public bool V; // oVerflow condition flag + public Bits EL; // Exception Level + public bool SP; // Stack pointer select: 0=SP0, 1=SPx [AArch64 only] + } +#endregion + } +} diff --git a/Ryujinx.Tests/Cpu/Tester/Types/Bits.cs b/Ryujinx.Tests/Cpu/Tester/Types/Bits.cs new file mode 100644 index 000000000..f4ee966cf --- /dev/null +++ b/Ryujinx.Tests/Cpu/Tester/Types/Bits.cs @@ -0,0 +1,248 @@ +// https://github.com/LDj3SNuD/ARM_v8-A_AArch64_Instructions_Tester/blob/master/Tester/Types/Bits.cs + +// https://github.com/dotnet/corefx/blob/master/src/System.Collections/src/System/Collections/BitArray.cs + +using System; +using System.Collections; +using System.Numerics; + +namespace Ryujinx.Tests.Cpu.Tester.Types +{ + internal sealed class Bits : ICollection, IEnumerable, IEquatable + { + private BitArray bits; + + public Bits(bool[] values) => bits = new BitArray(values); + public Bits(byte[] bytes) => bits = new BitArray(bytes); + public Bits(Bits bits) => this.bits = new BitArray(bits.bits); + private Bits(BitArray bitArray) => bits = new BitArray(bitArray); + public Bits(int length) => bits = new BitArray(length); + public Bits(int length, bool defaultValue) => bits = new BitArray(length, defaultValue); + public Bits(ulong value) => bits = new BitArray(BitConverter.GetBytes(value)); + public Bits(uint value) => bits = new BitArray(BitConverter.GetBytes(value)); + public Bits(ushort value) => bits = new BitArray(BitConverter.GetBytes(value)); + public Bits(byte value) => bits = new BitArray(new byte[1] {value}); + + public ulong ToUInt64() + { + byte[] dst = new byte[8]; + + bits.CopyTo(dst, 0); + + return BitConverter.ToUInt64(dst, 0); + } + public uint ToUInt32() + { + byte[] dst = new byte[4]; + + bits.CopyTo(dst, 0); + + return BitConverter.ToUInt32(dst, 0); + } + private BitArray ToBitArray() => new BitArray(bits); + + public bool this[int index] // ASL: "<>". + { + get + { + return bits.Get(index); + } + set + { + bits.Set(index, value); + } + } + public Bits this[int highIndex, int lowIndex] // ASL: "<:>". + { + get + { + if (highIndex < lowIndex) + { + throw new IndexOutOfRangeException(); + } + + bool[] dst = new bool[highIndex - lowIndex + 1]; + + for (int i = lowIndex, n = 0; i <= highIndex; i++, n++) + { + dst[n] = bits.Get(i); + } + + return new Bits(dst); + } + set + { + if (highIndex < lowIndex) + { + throw new IndexOutOfRangeException(); + } + + for (int i = lowIndex, n = 0; i <= highIndex; i++, n++) + { + bits.Set(i, value.Get(n)); + } + } + } + + public bool IsReadOnly { get => false; } // Mutable. + public int Count { get => bits.Count; } + public bool IsSynchronized { get => bits.IsSynchronized; } + public object SyncRoot { get => bits.SyncRoot; } + public Bits And(Bits value) => new Bits(new BitArray(this.bits).And(value.bits)); // Immutable. + public void CopyTo(Array array, int index) => bits.CopyTo(array, index); + public bool Get(int index) => bits.Get(index); + public IEnumerator GetEnumerator() => bits.GetEnumerator(); + //public Bits LeftShift(int count) => new Bits(new BitArray(bits).LeftShift(count)); // Immutable. + public Bits Not() => new Bits(new BitArray(bits).Not()); // Immutable. + public Bits Or(Bits value) => new Bits(new BitArray(this.bits).Or(value.bits)); // Immutable. + //public Bits RightShift(int count) => new Bits(new BitArray(bits).RightShift(count)); // Immutable. + public void Set(int index, bool value) => bits.Set(index, value); + public void SetAll(bool value) => bits.SetAll(value); + public Bits Xor(Bits value) => new Bits(new BitArray(this.bits).Xor(value.bits)); // Immutable. + + public static Bits Concat(Bits highBits, Bits lowBits) // ASL: ":". + { + if (((object)lowBits == null) || ((object)highBits == null)) + { + throw new ArgumentNullException(); + } + + bool[] dst = new bool[lowBits.Count + highBits.Count]; + + lowBits.CopyTo(dst, 0); + highBits.CopyTo(dst, lowBits.Count); + + return new Bits(dst); + } + public static Bits Concat(bool bit3, bool bit2, bool bit1, bool bit0) // ASL: ":::". + { + return new Bits(new bool[] {bit0, bit1, bit2, bit3}); + } + + public static implicit operator Bits(bool value) => new Bits(1, value); + public static implicit operator Bits(string value) + { + if (String.IsNullOrEmpty(value)) + { + throw new InvalidCastException(); + } + + bool[] dst = new bool[value.Length]; + + for (int i = value.Length - 1, n = 0; i >= 0; i--, n++) + { + if (value[i] == '1') + { + dst[n] = true; + } + else if (value[i] == '0') + { + dst[n] = false; + } + else + { + throw new InvalidCastException(); + } + } + + return new Bits(dst); + } + public static explicit operator bool(Bits bit) + { + if (((object)bit == null) || (bit.Count != 1)) + { + throw new InvalidCastException(); + } + + return bit.Get(0); + } + + public static Bits operator +(Bits left, BigInteger right) // ASL: "+". + { + if (((object)left == null) || ((object)right == null)) + { + throw new ArgumentNullException(); + } + + BigInteger dst; + + if (left.Count <= 32) + { + dst = left.ToUInt32() + right; + } + else if (left.Count <= 64) + { + dst = left.ToUInt64() + right; + } + else + { + throw new ArgumentOutOfRangeException(); + } + + return dst.SubBigInteger(left.Count - 1, 0); + } + public static bool operator ==(Bits left, Bits right) // ASL: "==". + { + if (((object)left == null) || ((object)right == null)) + { + throw new ArgumentNullException(); + } + + if (left.Count != right.Count) + { + return false; + } + + for (int i = 0; i <= left.Count - 1; i++) + { + if (left.Get(i) != right.Get(i)) + { + return false; + } + } + + return true; + } + public static bool operator !=(Bits left, Bits right) // ASL: "!=". + { + return !(left == right); + } + + public bool Equals(Bits right) // ASL: "==". + { + if ((object)right == null) + { + throw new ArgumentNullException(); + } + + Bits left = this; + + if (left.Count != right.Count) + { + return false; + } + + for (int i = 0; i <= left.Count - 1; i++) + { + if (left.Get(i) != right.Get(i)) + { + return false; + } + } + + return true; + } + public override bool Equals(object obj) + { + if (obj == null) + { + throw new ArgumentNullException(); + } + + Bits right = obj as Bits; + + return Equals(right); + } + public override int GetHashCode() => bits.GetHashCode(); + } +} diff --git a/Ryujinx.Tests/Cpu/Tester/Types/Integer.cs b/Ryujinx.Tests/Cpu/Tester/Types/Integer.cs new file mode 100644 index 000000000..c72f3e252 --- /dev/null +++ b/Ryujinx.Tests/Cpu/Tester/Types/Integer.cs @@ -0,0 +1,42 @@ +// https://github.com/LDj3SNuD/ARM_v8-A_AArch64_Instructions_Tester/blob/master/Tester/Types/Integer.cs + +using System; +using System.Numerics; + +namespace Ryujinx.Tests.Cpu.Tester.Types +{ + internal static class Integer + { + public static Bits SubBigInteger(this BigInteger x, int highIndex, int lowIndex) // ASL: "<:>". + { + if (highIndex < lowIndex) + { + throw new IndexOutOfRangeException(); + } + + Bits src = new Bits(x.ToByteArray()); + bool[] dst = new bool[highIndex - lowIndex + 1]; + + for (int i = lowIndex, n = 0; i <= highIndex; i++, n++) + { + if (i <= src.Count - 1) + { + dst[n] = src[i]; + } + else + { + dst[n] = (x.Sign != -1 ? false : true); // Zero / Sign Extension. + } + } + + return new Bits(dst); + } + + public static bool SubBigInteger(this BigInteger x, int index) // ASL: "<>". + { + Bits dst = x.SubBigInteger(index, index); + + return (bool)dst; + } + } +} diff --git a/Ryujinx.Tests/Ryujinx.Tests.csproj b/Ryujinx.Tests/Ryujinx.Tests.csproj index ae4ea6c33..77d86ec4f 100644 --- a/Ryujinx.Tests/Ryujinx.Tests.csproj +++ b/Ryujinx.Tests/Ryujinx.Tests.csproj @@ -1,15 +1,17 @@ netcoreapp2.0 + win10-x64 + Exe false false - - - + + +