From b1ad45acdd7536ffaf1bd8812628e1524477fe8c Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?J=2E=20Neusch=C3=A4fer?= Date: Fri, 5 Jan 2024 06:30:54 +0100 Subject: [PATCH] Fix memory barriers on ARMv5 The ARM926EJ-S Technical Reference Manual states: > You can only access CP15 registers with MRC and MCR instructions in a > privileged mode. CDP, LDC, STC, MCRR, and MRRC instructions, and unprivileged > MRC or MCR instructions to CP15 cause the Undefined instruction exception to > be taken. Furthermore, `MCR p15, 0, , c7, c10, 5` (later called Data Memory Barrier) is not specified for the ARM926. Thus, SDL should not use these cache instructions on ARMv5. (cherry picked from commit 139a0931a3ee9808f13e7faecdf9fc4590348f9e) --- include/SDL_atomic.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/SDL_atomic.h b/include/SDL_atomic.h index 99cdb894e..1fa18f49f 100644 --- a/include/SDL_atomic.h +++ b/include/SDL_atomic.h @@ -209,7 +209,7 @@ typedef void (*SDL_KernelMemoryBarrierFunc)(); #if defined(__ARM_ARCH_7__) || defined(__ARM_ARCH_7A__) || defined(__ARM_ARCH_7EM__) || defined(__ARM_ARCH_7R__) || defined(__ARM_ARCH_7M__) || defined(__ARM_ARCH_7S__) || defined(__ARM_ARCH_8A__) #define SDL_MemoryBarrierRelease() __asm__ __volatile__ ("dmb ish" : : : "memory") #define SDL_MemoryBarrierAcquire() __asm__ __volatile__ ("dmb ish" : : : "memory") -#elif defined(__ARM_ARCH_6__) || defined(__ARM_ARCH_6J__) || defined(__ARM_ARCH_6K__) || defined(__ARM_ARCH_6T2__) || defined(__ARM_ARCH_6Z__) || defined(__ARM_ARCH_6ZK__) || defined(__ARM_ARCH_5TE__) +#elif defined(__ARM_ARCH_6__) || defined(__ARM_ARCH_6J__) || defined(__ARM_ARCH_6K__) || defined(__ARM_ARCH_6T2__) || defined(__ARM_ARCH_6Z__) || defined(__ARM_ARCH_6ZK__) #ifdef __thumb__ /* The mcr instruction isn't available in thumb mode, use real functions */ #define SDL_MEMORY_BARRIER_USES_FUNCTION