diff --git a/include/sirit/sirit.h b/include/sirit/sirit.h
index 5cf61a0..344fbb0 100644
--- a/include/sirit/sirit.h
+++ b/include/sirit/sirit.h
@@ -262,11 +262,18 @@ class Module {
     /// The least-significant bits will be zero filled.
     Id OpShiftLeftLogical(Id result_type, Id base, Id shift);
 
+    /// Result is 1 if both Operand 1 and Operand 2 are 1. Result is 0 if either
+    /// Operand 1 or Operand 2 are 0.
+    Id OpBitwiseAnd(Id result_type, Id operand_1, Id operand_2);
+
     // Arithmetic
 
     /// Unsigned-integer division of Operand 1 divided by Operand 2.
     Id OpUDiv(Id result_type, Id operand_1, Id operand_2);
 
+    /// Integer addition of Operand 1 and Operand 2.
+    Id OpIAdd(Id result_type, Id operand_1, Id operand_2);
+
   private:
     Id AddCode(std::unique_ptr<Op> op);
 
diff --git a/src/insts/arithmetic.cpp b/src/insts/arithmetic.cpp
index 30363e0..e785188 100644
--- a/src/insts/arithmetic.cpp
+++ b/src/insts/arithmetic.cpp
@@ -11,11 +11,15 @@
 
 namespace Sirit {
 
-Id Module::OpUDiv(Id result_type, Id operand_1, Id operand_2) {
-    auto op{std::make_unique<Op>(spv::Op::OpUDiv, bound++, result_type)};
-    op->Add(operand_1);
-    op->Add(operand_2);
-    return AddCode(std::move(op));
-}
+#define DEFINE_BINARY(funcname, opcode)                                        \
+    Id Module::funcname(Id result_type, Id operand_1, Id operand_2) {          \
+        auto op{std::make_unique<Op>(opcode, bound++, result_type)};           \
+        op->Add(operand_1);                                                    \
+        op->Add(operand_2);                                                    \
+        return AddCode(std::move(op));                                         \
+    }
+
+DEFINE_BINARY(OpUDiv, spv::Op::OpUDiv)
+DEFINE_BINARY(OpIAdd, spv::Op::OpIAdd)
 
 } // namespace Sirit
\ No newline at end of file
diff --git a/src/insts/bit.cpp b/src/insts/bit.cpp
index a8bdc7f..2497f21 100644
--- a/src/insts/bit.cpp
+++ b/src/insts/bit.cpp
@@ -35,4 +35,11 @@ Id Module::OpShiftLeftLogical(Id result_type, Id base, Id shift) {
     return AddCode(std::move(op));
 }
 
+Id Module::OpBitwiseAnd(Id result_type, Id operand_1, Id operand_2) {
+    auto op{std::make_unique<Op>(spv::Op::OpBitwiseAnd, bound++, result_type)};
+    op->Add(operand_1);
+    op->Add(operand_2);
+    return AddCode(std::move(op));
+}
+
 } // namespace Sirit
\ No newline at end of file