From 0023d048aad31b953d06c05e52979edfb797379f Mon Sep 17 00:00:00 2001 From: Konrad Rzeszutek Wilk Date: Tue, 3 Jul 2018 00:24:08 -0400 Subject: [PATCH] i386: define the AMD 'amd-ssbd' CPUID feature bit AMD future CPUs expose _two_ ways to utilize the Intel equivalant of the Speculative Store Bypass Disable. The first is via the virtualized VIRT_SPEC CTRL MSR (0xC001_011f) and the second is via the SPEC_CTRL MSR (0x48). The document titled: 124441_AMD64_SpeculativeStoreBypassDisable_Whitepaper_final.pdf gives priority of SPEC CTRL MSR over the VIRT SPEC CTRL MSR. A copy of this document is available at https://bugzilla.kernel.org/show_bug.cgi?id=199889 Anyhow, this means that on future AMD CPUs there will be _two_ ways to deal with SSBD. Backports commit a764f3f7197f4d7ad8fe8424269933de912224cb from qemu --- qemu/target/i386/cpu.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/qemu/target/i386/cpu.c b/qemu/target/i386/cpu.c index 6628208b..e30b3516 100644 --- a/qemu/target/i386/cpu.c +++ b/qemu/target/i386/cpu.c @@ -909,7 +909,7 @@ static FeatureWordInfo feature_word_info[FEATURE_WORDS] = { "ibpb", NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, - NULL, "virt-ssbd", NULL, NULL, + "amd-ssbd", "virt-ssbd", NULL, NULL, NULL, NULL, NULL, NULL, }, 0x80000008,