From 002b392a151b13aed4cd20659ec5982670aeb64a Mon Sep 17 00:00:00 2001 From: Paul Burton Date: Sun, 25 Feb 2018 03:49:31 -0500 Subject: [PATCH] target-mips: support CP0.Config4.AE bit The read-only Config4.AE bit set denotes extended 10 bits ASID. Backports commit a0c8060841f2d56fb3504292c18522b957972e4c from qemu --- qemu/target-mips/cpu.h | 1 + qemu/target-mips/translate.c | 3 ++- 2 files changed, 3 insertions(+), 1 deletion(-) diff --git a/qemu/target-mips/cpu.h b/qemu/target-mips/cpu.h index 150564c0..b79c88e7 100644 --- a/qemu/target-mips/cpu.h +++ b/qemu/target-mips/cpu.h @@ -469,6 +469,7 @@ struct CPUMIPSState { int32_t CP0_Config4_rw_bitmask; #define CP0C4_M 31 #define CP0C4_IE 29 +#define CP0C4_AE 28 #define CP0C4_KScrExist 16 #define CP0C4_MMUExtDef 14 #define CP0C4_FTLBPageSize 8 diff --git a/qemu/target-mips/translate.c b/qemu/target-mips/translate.c index 199ce92a..5264ad73 100644 --- a/qemu/target-mips/translate.c +++ b/qemu/target-mips/translate.c @@ -20434,7 +20434,8 @@ void cpu_state_reset(CPUMIPSState *env) if (env->CP0_Config3 & (1 << CP0C3_CMGCR)) { env->CP0_CMGCRBase = 0x1fbf8000 >> 4; } - env->CP0_EntryHi_ASID_mask = 0xff; + env->CP0_EntryHi_ASID_mask = (env->CP0_Config4 & (1 << CP0C4_AE)) ? + 0x3ff : 0xff; env->CP0_Status = (1 << CP0St_BEV) | (1 << CP0St_ERL); /* vectored interrupts not implemented, timer on int 7, no performance counters. */