From 003b2155a118df742bd9b5693463c64fcbb74460 Mon Sep 17 00:00:00 2001 From: Xiao Guangrong Date: Sat, 17 Feb 2018 15:34:45 -0500 Subject: [PATCH] target-i386: Enable clflushopt/clwb/pcommit instructions These instructions are used by NVDIMM drivers and the specification is located at: https://software.intel.com/sites/default/files/managed/0d/53/319433-022.pdf There instructions are available on Skylake Server. Backports commit f7fda280948a5e74aeb076ef346b991ecb173c56 from qemu --- qemu/target-i386/cpu.c | 6 +++--- qemu/target-i386/cpu.h | 3 +++ 2 files changed, 6 insertions(+), 3 deletions(-) diff --git a/qemu/target-i386/cpu.c b/qemu/target-i386/cpu.c index 03ee50b0..9e83558e 100644 --- a/qemu/target-i386/cpu.c +++ b/qemu/target-i386/cpu.c @@ -226,8 +226,8 @@ static const char *ext4_feature_name[] = { static const char *cpuid_7_0_ebx_feature_name[] = { "fsgsbase", "tsc_adjust", NULL, "bmi1", "hle", "avx2", NULL, "smep", "bmi2", "erms", "invpcid", "rtm", NULL, NULL, "mpx", NULL, - "avx512f", NULL, "rdseed", "adx", "smap", NULL, NULL, NULL, - NULL, NULL, "avx512pf", "avx512er", "avx512cd", NULL, NULL, NULL, + "avx512f", NULL, "rdseed", "adx", "smap", NULL, "pcommit", "clflushopt", + "clwb", NULL, "avx512pf", "avx512er", "avx512cd", NULL, NULL, NULL, }; static const char *cpuid_apm_edx_feature_name[] = { @@ -787,7 +787,7 @@ static X86CPUDefinition builtin_x86_defs[] = { // FEAT_1_EDX PPRO_FEATURES, // FEAT_1_ECX - CPUID_EXT_SSE3, + CPUID_EXT_SSSE3, }, }, { diff --git a/qemu/target-i386/cpu.h b/qemu/target-i386/cpu.h index 905c6885..05ce8bf5 100644 --- a/qemu/target-i386/cpu.h +++ b/qemu/target-i386/cpu.h @@ -577,6 +577,9 @@ typedef uint32_t FeatureWordArray[FEATURE_WORDS]; #define CPUID_7_0_EBX_RDSEED (1U << 18) #define CPUID_7_0_EBX_ADX (1U << 19) #define CPUID_7_0_EBX_SMAP (1U << 20) +#define CPUID_7_0_EBX_PCOMMIT (1U << 22) /* Persistent Commit */ +#define CPUID_7_0_EBX_CLFLUSHOPT (1U << 23) /* Flush a Cache Line Optimized */ +#define CPUID_7_0_EBX_CLWB (1U << 24) /* Cache Line Write Back */ #define CPUID_7_0_EBX_AVX512PF (1U << 26) /* AVX-512 Prefetch */ #define CPUID_7_0_EBX_AVX512ER (1U << 27) /* AVX-512 Exponential and Reciprocal */ #define CPUID_7_0_EBX_AVX512CD (1U << 28) /* AVX-512 Conflict Detection */