diff --git a/bindings/dotnet/UnicornManaged/Const/Arm64.fs b/bindings/dotnet/UnicornManaged/Const/Arm64.fs
index 4801732f..fb13574d 100644
--- a/bindings/dotnet/UnicornManaged/Const/Arm64.fs
+++ b/bindings/dotnet/UnicornManaged/Const/Arm64.fs
@@ -273,7 +273,12 @@ module Arm64 =
     // pseudo registers
     let UC_ARM64_REG_PC = 260
     let UC_ARM64_REG_CPACR_EL1 = 261
-    let UC_ARM64_REG_ENDING = 262
+
+    // thread registers
+    let UC_ARM64_REG_TPIDR_EL0 = 262
+    let UC_ARM64_REG_TPIDRRO_EL0 = 263
+    let UC_ARM64_REG_TPIDR_EL1 = 264
+    let UC_ARM64_REG_ENDING = 265
 
     // alias registers
     let UC_ARM64_REG_IP1 = 215
diff --git a/bindings/go/unicorn/arm64_const.go b/bindings/go/unicorn/arm64_const.go
index 47a90c8c..cfefc1b9 100644
--- a/bindings/go/unicorn/arm64_const.go
+++ b/bindings/go/unicorn/arm64_const.go
@@ -268,7 +268,12 @@ const (
 // pseudo registers
 	ARM64_REG_PC = 260
 	ARM64_REG_CPACR_EL1 = 261
-	ARM64_REG_ENDING = 262
+
+// thread registers
+	ARM64_REG_TPIDR_EL0 = 262
+	ARM64_REG_TPIDRRO_EL0 = 263
+	ARM64_REG_TPIDR_EL1 = 264
+	ARM64_REG_ENDING = 265
 
 // alias registers
 	ARM64_REG_IP1 = 215
diff --git a/bindings/java/unicorn/Arm64Const.java b/bindings/java/unicorn/Arm64Const.java
index 9b79fbfb..7a35434d 100644
--- a/bindings/java/unicorn/Arm64Const.java
+++ b/bindings/java/unicorn/Arm64Const.java
@@ -270,7 +270,12 @@ public interface Arm64Const {
 // pseudo registers
    public static final int UC_ARM64_REG_PC = 260;
    public static final int UC_ARM64_REG_CPACR_EL1 = 261;
-   public static final int UC_ARM64_REG_ENDING = 262;
+
+// thread registers
+   public static final int UC_ARM64_REG_TPIDR_EL0 = 262;
+   public static final int UC_ARM64_REG_TPIDRRO_EL0 = 263;
+   public static final int UC_ARM64_REG_TPIDR_EL1 = 264;
+   public static final int UC_ARM64_REG_ENDING = 265;
 
 // alias registers
    public static final int UC_ARM64_REG_IP1 = 215;
diff --git a/bindings/python/unicorn/arm64_const.py b/bindings/python/unicorn/arm64_const.py
index 30001560..9b731d02 100644
--- a/bindings/python/unicorn/arm64_const.py
+++ b/bindings/python/unicorn/arm64_const.py
@@ -266,7 +266,12 @@ UC_ARM64_REG_V31 = 259
 # pseudo registers
 UC_ARM64_REG_PC = 260
 UC_ARM64_REG_CPACR_EL1 = 261
-UC_ARM64_REG_ENDING = 262
+
+# thread registers
+UC_ARM64_REG_TPIDR_EL0 = 262
+UC_ARM64_REG_TPIDRRO_EL0 = 263
+UC_ARM64_REG_TPIDR_EL1 = 264
+UC_ARM64_REG_ENDING = 265
 
 # alias registers
 UC_ARM64_REG_IP1 = 215
diff --git a/bindings/ruby/unicorn_gem/lib/unicorn/arm64_const.rb b/bindings/ruby/unicorn_gem/lib/unicorn/arm64_const.rb
index e1abdf76..424de052 100644
--- a/bindings/ruby/unicorn_gem/lib/unicorn/arm64_const.rb
+++ b/bindings/ruby/unicorn_gem/lib/unicorn/arm64_const.rb
@@ -268,7 +268,12 @@ module Unicorn
 # pseudo registers
 	UC_ARM64_REG_PC = 260
 	UC_ARM64_REG_CPACR_EL1 = 261
-	UC_ARM64_REG_ENDING = 262
+
+# thread registers
+	UC_ARM64_REG_TPIDR_EL0 = 262
+	UC_ARM64_REG_TPIDRRO_EL0 = 263
+	UC_ARM64_REG_TPIDR_EL1 = 264
+	UC_ARM64_REG_ENDING = 265
 
 # alias registers
 	UC_ARM64_REG_IP1 = 215
diff --git a/include/unicorn/arm64.h b/include/unicorn/arm64.h
index 17eb7b78..586d12da 100644
--- a/include/unicorn/arm64.h
+++ b/include/unicorn/arm64.h
@@ -282,6 +282,11 @@ typedef enum uc_arm64_reg {
 
     UC_ARM64_REG_CPACR_EL1,
 
+    //> thread registers
+    UC_ARM64_REG_TPIDR_EL0,
+    UC_ARM64_REG_TPIDRRO_EL0,
+    UC_ARM64_REG_TPIDR_EL1,
+    
     UC_ARM64_REG_ENDING,		// <-- mark the end of the list of registers
 
     //> alias registers
diff --git a/qemu/target-arm/unicorn_aarch64.c b/qemu/target-arm/unicorn_aarch64.c
index 3de2dbab..76e580b5 100644
--- a/qemu/target-arm/unicorn_aarch64.c
+++ b/qemu/target-arm/unicorn_aarch64.c
@@ -79,21 +79,30 @@ int arm64_reg_read(struct uc_struct *uc, unsigned int *regs, void **vals, int co
                 case UC_ARM64_REG_CPACR_EL1:
                     *(uint32_t *)value = ARM_CPU(uc, mycpu)->env.cp15.c1_coproc;
                     break;
+                case UC_ARM64_REG_TPIDR_EL0:
+                    *(int64_t *)value = ARM_CPU(uc, mycpu)->env.cp15.tpidr_el0;
+                    break;
+                case UC_ARM64_REG_TPIDRRO_EL0:
+                    *(int64_t *)value = ARM_CPU(uc, mycpu)->env.cp15.tpidrro_el0;
+                    break;
+                case UC_ARM64_REG_TPIDR_EL1:
+                    *(int64_t *)value = ARM_CPU(uc, mycpu)->env.cp15.tpidr_el1;
+                    break;
                 case UC_ARM64_REG_X29:
-                         *(int64_t *)value = ARM_CPU(uc, mycpu)->env.xregs[29];
-                         break;
+                    *(int64_t *)value = ARM_CPU(uc, mycpu)->env.xregs[29];
+                    break;
                 case UC_ARM64_REG_X30:
-                         *(int64_t *)value = ARM_CPU(uc, mycpu)->env.xregs[30];
-                         break;
+                    *(int64_t *)value = ARM_CPU(uc, mycpu)->env.xregs[30];
+                    break;
                 case UC_ARM64_REG_PC:
-                         *(uint64_t *)value = ARM_CPU(uc, mycpu)->env.pc;
-                         break;
+                    *(uint64_t *)value = ARM_CPU(uc, mycpu)->env.pc;
+                    break;
                 case UC_ARM64_REG_SP:
-                         *(int64_t *)value = ARM_CPU(uc, mycpu)->env.xregs[31];
-                         break;
+                    *(int64_t *)value = ARM_CPU(uc, mycpu)->env.xregs[31];
+                    break;
                 case UC_ARM64_REG_NZCV:
-                         *(int32_t *)value = cpsr_read(&ARM_CPU(uc, mycpu)->env) & CPSR_NZCV;
-                         break;
+                    *(int32_t *)value = cpsr_read(&ARM_CPU(uc, mycpu)->env) & CPSR_NZCV;
+                    break;
             }
         }
     }
@@ -135,24 +144,33 @@ int arm64_reg_write(struct uc_struct *uc, unsigned int *regs, void* const* vals,
                 case UC_ARM64_REG_CPACR_EL1:
                     ARM_CPU(uc, mycpu)->env.cp15.c1_coproc = *(uint32_t *)value;
                     break;
+                case UC_ARM64_REG_TPIDR_EL0:
+                    ARM_CPU(uc, mycpu)->env.cp15.tpidr_el0 = *(uint64_t *)value;
+                    break;
+                case UC_ARM64_REG_TPIDRRO_EL0:
+                    ARM_CPU(uc, mycpu)->env.cp15.tpidrro_el0 = *(uint64_t *)value;
+                    break;
+                case UC_ARM64_REG_TPIDR_EL1:
+                    ARM_CPU(uc, mycpu)->env.cp15.tpidr_el1 = *(uint64_t *)value;
+                    break;
                 case UC_ARM64_REG_X29:
-                         ARM_CPU(uc, mycpu)->env.xregs[29] = *(uint64_t *)value;
-                         break;
+                    ARM_CPU(uc, mycpu)->env.xregs[29] = *(uint64_t *)value;
+                    break;
                 case UC_ARM64_REG_X30:
-                         ARM_CPU(uc, mycpu)->env.xregs[30] = *(uint64_t *)value;
-                         break;
+                    ARM_CPU(uc, mycpu)->env.xregs[30] = *(uint64_t *)value;
+                    break;
                 case UC_ARM64_REG_PC:
-                         ARM_CPU(uc, mycpu)->env.pc = *(uint64_t *)value;
-                         // force to quit execution and flush TB
-                         uc->quit_request = true;
-                         uc_emu_stop(uc);
-                         break;
+                    ARM_CPU(uc, mycpu)->env.pc = *(uint64_t *)value;
+                    // force to quit execution and flush TB
+                    uc->quit_request = true;
+                    uc_emu_stop(uc);
+                    break;
                 case UC_ARM64_REG_SP:
-                         ARM_CPU(uc, mycpu)->env.xregs[31] = *(uint64_t *)value;
-                         break;
+                    ARM_CPU(uc, mycpu)->env.xregs[31] = *(uint64_t *)value;
+                    break;
                 case UC_ARM64_REG_NZCV:
-                         cpsr_write(&ARM_CPU(uc, mycpu)->env, *(uint32_t *) value, CPSR_NZCV);
-                         break;
+                    cpsr_write(&ARM_CPU(uc, mycpu)->env, *(uint32_t *) value, CPSR_NZCV);
+                    break;
             }
         }
     }