From 025aa6fd3949b1995e0011c4670d297d901b8bf0 Mon Sep 17 00:00:00 2001 From: LIU Zhiwei Date: Fri, 5 Mar 2021 09:14:45 -0500 Subject: [PATCH] target/riscv: vector integer merge and move instructions Backports f020a7a14505d6996497693e63331ab609847d93 --- qemu/header_gen.py | 34 ++++++ qemu/riscv32.h | 34 ++++++ qemu/riscv64.h | 34 ++++++ qemu/target/riscv/helper.h | 17 +++ qemu/target/riscv/insn32.decode | 7 ++ qemu/target/riscv/insn_trans/trans_rvv.inc.c | 119 +++++++++++++++++++ qemu/target/riscv/vector_helper.c | 88 ++++++++++++++ 7 files changed, 333 insertions(+) diff --git a/qemu/header_gen.py b/qemu/header_gen.py index 95e061ef..6891ece3 100644 --- a/qemu/header_gen.py +++ b/qemu/header_gen.py @@ -6826,6 +6826,40 @@ riscv_symbols = ( 'helper_vwmaccus_vx_b', 'helper_vwmaccus_vx_h', 'helper_vwmaccus_vx_w', + 'helper_vmerge_vvm_b', + 'helper_vmerge_vvm_h', + 'helper_vmerge_vvm_w', + 'helper_vmerge_vvm_d', + 'helper_vmerge_vxm_b', + 'helper_vmerge_vxm_h', + 'helper_vmerge_vxm_w', + 'helper_vmerge_vxm_d', + 'helper_vmv_v_v_b', + 'helper_vmv_v_v_h', + 'helper_vmv_v_v_w', + 'helper_vmv_v_v_d', + 'helper_vmv_v_x_b', + 'helper_vmv_v_x_h', + 'helper_vmv_v_x_w', + 'helper_vmv_v_x_d', + 'helper_vwmul_vv_b', + 'helper_vwmul_vv_h', + 'helper_vwmul_vv_w', + 'helper_vwmulu_vv_b', + 'helper_vwmulu_vv_h', + 'helper_vwmulu_vv_w', + 'helper_vwmulsu_vv_b', + 'helper_vwmulsu_vv_h', + 'helper_vwmulsu_vv_w', + 'helper_vwmul_vx_b', + 'helper_vwmul_vx_h', + 'helper_vwmul_vx_w', + 'helper_vwmulu_vx_b', + 'helper_vwmulu_vx_h', + 'helper_vwmulu_vx_w', + 'helper_vwmulsu_vx_b', + 'helper_vwmulsu_vx_h', + 'helper_vwmulsu_vx_w', 'pmp_hart_has_privs', 'pmpaddr_csr_read', 'pmpaddr_csr_write', diff --git a/qemu/riscv32.h b/qemu/riscv32.h index f9879a9c..a7f1e912 100644 --- a/qemu/riscv32.h +++ b/qemu/riscv32.h @@ -4262,6 +4262,40 @@ #define helper_vwmaccus_vx_b helper_vwmaccus_vx_b_riscv32 #define helper_vwmaccus_vx_h helper_vwmaccus_vx_h_riscv32 #define helper_vwmaccus_vx_w helper_vwmaccus_vx_w_riscv32 +#define helper_vmerge_vvm_b helper_vmerge_vvm_b_riscv32 +#define helper_vmerge_vvm_h helper_vmerge_vvm_h_riscv32 +#define helper_vmerge_vvm_w helper_vmerge_vvm_w_riscv32 +#define helper_vmerge_vvm_d helper_vmerge_vvm_d_riscv32 +#define helper_vmerge_vxm_b helper_vmerge_vxm_b_riscv32 +#define helper_vmerge_vxm_h helper_vmerge_vxm_h_riscv32 +#define helper_vmerge_vxm_w helper_vmerge_vxm_w_riscv32 +#define helper_vmerge_vxm_d helper_vmerge_vxm_d_riscv32 +#define helper_vmv_v_v_b helper_vmv_v_v_b_riscv32 +#define helper_vmv_v_v_h helper_vmv_v_v_h_riscv32 +#define helper_vmv_v_v_w helper_vmv_v_v_w_riscv32 +#define helper_vmv_v_v_d helper_vmv_v_v_d_riscv32 +#define helper_vmv_v_x_b helper_vmv_v_x_b_riscv32 +#define helper_vmv_v_x_h helper_vmv_v_x_h_riscv32 +#define helper_vmv_v_x_w helper_vmv_v_x_w_riscv32 +#define helper_vmv_v_x_d helper_vmv_v_x_d_riscv32 +#define helper_vwmul_vv_b helper_vwmul_vv_b_riscv32 +#define helper_vwmul_vv_h helper_vwmul_vv_h_riscv32 +#define helper_vwmul_vv_w helper_vwmul_vv_w_riscv32 +#define helper_vwmulu_vv_b helper_vwmulu_vv_b_riscv32 +#define helper_vwmulu_vv_h helper_vwmulu_vv_h_riscv32 +#define helper_vwmulu_vv_w helper_vwmulu_vv_w_riscv32 +#define helper_vwmulsu_vv_b helper_vwmulsu_vv_b_riscv32 +#define helper_vwmulsu_vv_h helper_vwmulsu_vv_h_riscv32 +#define helper_vwmulsu_vv_w helper_vwmulsu_vv_w_riscv32 +#define helper_vwmul_vx_b helper_vwmul_vx_b_riscv32 +#define helper_vwmul_vx_h helper_vwmul_vx_h_riscv32 +#define helper_vwmul_vx_w helper_vwmul_vx_w_riscv32 +#define helper_vwmulu_vx_b helper_vwmulu_vx_b_riscv32 +#define helper_vwmulu_vx_h helper_vwmulu_vx_h_riscv32 +#define helper_vwmulu_vx_w helper_vwmulu_vx_w_riscv32 +#define helper_vwmulsu_vx_b helper_vwmulsu_vx_b_riscv32 +#define helper_vwmulsu_vx_h helper_vwmulsu_vx_h_riscv32 +#define helper_vwmulsu_vx_w helper_vwmulsu_vx_w_riscv32 #define pmp_hart_has_privs pmp_hart_has_privs_riscv32 #define pmpaddr_csr_read pmpaddr_csr_read_riscv32 #define pmpaddr_csr_write pmpaddr_csr_write_riscv32 diff --git a/qemu/riscv64.h b/qemu/riscv64.h index be92365e..360d6afb 100644 --- a/qemu/riscv64.h +++ b/qemu/riscv64.h @@ -4262,6 +4262,40 @@ #define helper_vwmaccus_vx_b helper_vwmaccus_vx_b_riscv64 #define helper_vwmaccus_vx_h helper_vwmaccus_vx_h_riscv64 #define helper_vwmaccus_vx_w helper_vwmaccus_vx_w_riscv64 +#define helper_vmerge_vvm_b helper_vmerge_vvm_b_riscv64 +#define helper_vmerge_vvm_h helper_vmerge_vvm_h_riscv64 +#define helper_vmerge_vvm_w helper_vmerge_vvm_w_riscv64 +#define helper_vmerge_vvm_d helper_vmerge_vvm_d_riscv64 +#define helper_vmerge_vxm_b helper_vmerge_vxm_b_riscv64 +#define helper_vmerge_vxm_h helper_vmerge_vxm_h_riscv64 +#define helper_vmerge_vxm_w helper_vmerge_vxm_w_riscv64 +#define helper_vmerge_vxm_d helper_vmerge_vxm_d_riscv64 +#define helper_vmv_v_v_b helper_vmv_v_v_b_riscv64 +#define helper_vmv_v_v_h helper_vmv_v_v_h_riscv64 +#define helper_vmv_v_v_w helper_vmv_v_v_w_riscv64 +#define helper_vmv_v_v_d helper_vmv_v_v_d_riscv64 +#define helper_vmv_v_x_b helper_vmv_v_x_b_riscv64 +#define helper_vmv_v_x_h helper_vmv_v_x_h_riscv64 +#define helper_vmv_v_x_w helper_vmv_v_x_w_riscv64 +#define helper_vmv_v_x_d helper_vmv_v_x_d_riscv64 +#define helper_vwmul_vv_b helper_vwmul_vv_b_riscv64 +#define helper_vwmul_vv_h helper_vwmul_vv_h_riscv64 +#define helper_vwmul_vv_w helper_vwmul_vv_w_riscv64 +#define helper_vwmulu_vv_b helper_vwmulu_vv_b_riscv64 +#define helper_vwmulu_vv_h helper_vwmulu_vv_h_riscv64 +#define helper_vwmulu_vv_w helper_vwmulu_vv_w_riscv64 +#define helper_vwmulsu_vv_b helper_vwmulsu_vv_b_riscv64 +#define helper_vwmulsu_vv_h helper_vwmulsu_vv_h_riscv64 +#define helper_vwmulsu_vv_w helper_vwmulsu_vv_w_riscv64 +#define helper_vwmul_vx_b helper_vwmul_vx_b_riscv64 +#define helper_vwmul_vx_h helper_vwmul_vx_h_riscv64 +#define helper_vwmul_vx_w helper_vwmul_vx_w_riscv64 +#define helper_vwmulu_vx_b helper_vwmulu_vx_b_riscv64 +#define helper_vwmulu_vx_h helper_vwmulu_vx_h_riscv64 +#define helper_vwmulu_vx_w helper_vwmulu_vx_w_riscv64 +#define helper_vwmulsu_vx_b helper_vwmulsu_vx_b_riscv64 +#define helper_vwmulsu_vx_h helper_vwmulsu_vx_h_riscv64 +#define helper_vwmulsu_vx_w helper_vwmulsu_vx_w_riscv64 #define pmp_hart_has_privs pmp_hart_has_privs_riscv64 #define pmpaddr_csr_read pmpaddr_csr_read_riscv64 #define pmpaddr_csr_write pmpaddr_csr_write_riscv64 diff --git a/qemu/target/riscv/helper.h b/qemu/target/riscv/helper.h index 64816bd2..7adb951c 100644 --- a/qemu/target/riscv/helper.h +++ b/qemu/target/riscv/helper.h @@ -665,3 +665,20 @@ DEF_HELPER_6(vwmaccsu_vx_w, void, ptr, ptr, tl, ptr, env, i32) DEF_HELPER_6(vwmaccus_vx_b, void, ptr, ptr, tl, ptr, env, i32) DEF_HELPER_6(vwmaccus_vx_h, void, ptr, ptr, tl, ptr, env, i32) DEF_HELPER_6(vwmaccus_vx_w, void, ptr, ptr, tl, ptr, env, i32) + +DEF_HELPER_6(vmerge_vvm_b, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vmerge_vvm_h, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vmerge_vvm_w, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vmerge_vvm_d, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vmerge_vxm_b, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vmerge_vxm_h, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vmerge_vxm_w, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vmerge_vxm_d, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_4(vmv_v_v_b, void, ptr, ptr, env, i32) +DEF_HELPER_4(vmv_v_v_h, void, ptr, ptr, env, i32) +DEF_HELPER_4(vmv_v_v_w, void, ptr, ptr, env, i32) +DEF_HELPER_4(vmv_v_v_d, void, ptr, ptr, env, i32) +DEF_HELPER_4(vmv_v_x_b, void, ptr, i64, env, i32) +DEF_HELPER_4(vmv_v_x_h, void, ptr, i64, env, i32) +DEF_HELPER_4(vmv_v_x_w, void, ptr, i64, env, i32) +DEF_HELPER_4(vmv_v_x_d, void, ptr, i64, env, i32) diff --git a/qemu/target/riscv/insn32.decode b/qemu/target/riscv/insn32.decode index acb5b0fc..b1bf6ef3 100644 --- a/qemu/target/riscv/insn32.decode +++ b/qemu/target/riscv/insn32.decode @@ -71,6 +71,7 @@ @r_nfvm ... ... vm:1 ..... ..... ... ..... ....... &rnfvm %nf %rs2 %rs1 %rd @r_vm ...... vm:1 ..... ..... ... ..... ....... &rmrr %rs2 %rs1 %rd @r_vm_1 ...... . ..... ..... ... ..... ....... &rmrr vm=1 %rs2 %rs1 %rd +@r_vm_0 ...... . ..... ..... ... ..... ....... &rmrr vm=0 %rs2 %rs1 %rd @r_wdvm ..... wd:1 vm:1 ..... ..... ... ..... ....... &rwdvm %rs2 %rs1 %rd @r2_zimm . zimm:11 ..... ... ..... ....... %rs1 %rd @@ -396,6 +397,12 @@ vwmacc_vx 111101 . ..... ..... 110 ..... 1010111 @r_vm vwmaccsu_vv 111110 . ..... ..... 010 ..... 1010111 @r_vm vwmaccsu_vx 111110 . ..... ..... 110 ..... 1010111 @r_vm vwmaccus_vx 111111 . ..... ..... 110 ..... 1010111 @r_vm +vmv_v_v 010111 1 00000 ..... 000 ..... 1010111 @r2 +vmv_v_x 010111 1 00000 ..... 100 ..... 1010111 @r2 +vmv_v_i 010111 1 00000 ..... 011 ..... 1010111 @r2 +vmerge_vvm 010111 0 ..... ..... 000 ..... 1010111 @r_vm_0 +vmerge_vxm 010111 0 ..... ..... 100 ..... 1010111 @r_vm_0 +vmerge_vim 010111 0 ..... ..... 011 ..... 1010111 @r_vm_0 vsetvli 0 ........... ..... 111 ..... 1010111 @r2_zimm vsetvl 1000000 ..... ..... 111 ..... 1010111 @r diff --git a/qemu/target/riscv/insn_trans/trans_rvv.inc.c b/qemu/target/riscv/insn_trans/trans_rvv.inc.c index 63a127ff..b725e054 100644 --- a/qemu/target/riscv/insn_trans/trans_rvv.inc.c +++ b/qemu/target/riscv/insn_trans/trans_rvv.inc.c @@ -1549,3 +1549,122 @@ GEN_OPIVX_WIDEN_TRANS(vwmaccu_vx) GEN_OPIVX_WIDEN_TRANS(vwmacc_vx) GEN_OPIVX_WIDEN_TRANS(vwmaccsu_vx) GEN_OPIVX_WIDEN_TRANS(vwmaccus_vx) + +/* Vector Integer Merge and Move Instructions */ +static bool trans_vmv_v_v(DisasContext *s, arg_vmv_v_v *a) +{ + TCGContext *tcg_ctx = s->uc->tcg_ctx; + + if (vext_check_isa_ill(s) && + vext_check_reg(s, a->rd, false) && + vext_check_reg(s, a->rs1, false)) { + + if (s->vl_eq_vlmax) { + tcg_gen_gvec_mov(tcg_ctx, s->sew, vreg_ofs(s, a->rd), + vreg_ofs(s, a->rs1), + MAXSZ(s), MAXSZ(s)); + } else { + uint32_t data = FIELD_DP32(0, VDATA, LMUL, s->lmul); + static gen_helper_gvec_2_ptr * const fns[4] = { + gen_helper_vmv_v_v_b, gen_helper_vmv_v_v_h, + gen_helper_vmv_v_v_w, gen_helper_vmv_v_v_d, + }; + TCGLabel *over = gen_new_label(tcg_ctx); + tcg_gen_brcondi_tl(tcg_ctx, TCG_COND_EQ, tcg_ctx->cpu_vl_risc, 0, over); + + tcg_gen_gvec_2_ptr(tcg_ctx, vreg_ofs(s, a->rd), vreg_ofs(s, a->rs1), + tcg_ctx->cpu_env, 0, s->vlen / 8, data, fns[s->sew]); + gen_set_label(tcg_ctx, over); + } + return true; + } + return false; +} + +typedef void gen_helper_vmv_vx(TCGContext *, TCGv_ptr, TCGv_i64, TCGv_env, TCGv_i32); +static bool trans_vmv_v_x(DisasContext *s, arg_vmv_v_x *a) +{ + TCGContext *tcg_ctx = s->uc->tcg_ctx; + + if (vext_check_isa_ill(s) && + vext_check_reg(s, a->rd, false)) { + + TCGv s1; + TCGLabel *over = gen_new_label(tcg_ctx); + tcg_gen_brcondi_tl(tcg_ctx, TCG_COND_EQ, tcg_ctx->cpu_vl_risc, 0, over); + + s1 = tcg_temp_new(tcg_ctx); + gen_get_gpr(s, s1, a->rs1); + + if (s->vl_eq_vlmax) { + tcg_gen_gvec_dup_tl(tcg_ctx, s->sew, vreg_ofs(s, a->rd), + MAXSZ(s), MAXSZ(s), s1); + } else { + TCGv_i32 desc ; + TCGv_i64 s1_i64 = tcg_temp_new_i64(tcg_ctx); + TCGv_ptr dest = tcg_temp_new_ptr(tcg_ctx); + uint32_t data = FIELD_DP32(0, VDATA, LMUL, s->lmul); + static gen_helper_vmv_vx * const fns[4] = { + gen_helper_vmv_v_x_b, gen_helper_vmv_v_x_h, + gen_helper_vmv_v_x_w, gen_helper_vmv_v_x_d, + }; + + tcg_gen_ext_tl_i64(tcg_ctx, s1_i64, s1); + desc = tcg_const_i32(tcg_ctx, simd_desc(0, s->vlen / 8, data)); + tcg_gen_addi_ptr(tcg_ctx, dest, tcg_ctx->cpu_env, vreg_ofs(s, a->rd)); + fns[s->sew](tcg_ctx, dest, s1_i64, tcg_ctx->cpu_env, desc); + + tcg_temp_free_ptr(tcg_ctx, dest); + tcg_temp_free_i32(tcg_ctx, desc); + tcg_temp_free_i64(tcg_ctx, s1_i64); + } + + tcg_temp_free(tcg_ctx, s1); + gen_set_label(tcg_ctx, over); + return true; + } + return false; +} + +static bool trans_vmv_v_i(DisasContext *s, arg_vmv_v_i *a) +{ + TCGContext *tcg_ctx = s->uc->tcg_ctx; + + if (vext_check_isa_ill(s) && + vext_check_reg(s, a->rd, false)) { + + int64_t simm = sextract64(a->rs1, 0, 5); + if (s->vl_eq_vlmax) { + tcg_gen_gvec_dup_imm(tcg_ctx, s->sew, vreg_ofs(s, a->rd), + MAXSZ(s), MAXSZ(s), simm); + } else { + TCGv_i32 desc; + TCGv_i64 s1; + TCGv_ptr dest; + uint32_t data = FIELD_DP32(0, VDATA, LMUL, s->lmul); + static gen_helper_vmv_vx * const fns[4] = { + gen_helper_vmv_v_x_b, gen_helper_vmv_v_x_h, + gen_helper_vmv_v_x_w, gen_helper_vmv_v_x_d, + }; + TCGLabel *over = gen_new_label(tcg_ctx); + tcg_gen_brcondi_tl(tcg_ctx, TCG_COND_EQ, tcg_ctx->cpu_vl_risc, 0, over); + + s1 = tcg_const_i64(tcg_ctx, simm); + dest = tcg_temp_new_ptr(tcg_ctx); + desc = tcg_const_i32(tcg_ctx, simd_desc(0, s->vlen / 8, data)); + tcg_gen_addi_ptr(tcg_ctx, dest, tcg_ctx->cpu_env, vreg_ofs(s, a->rd)); + fns[s->sew](tcg_ctx, dest, s1, tcg_ctx->cpu_env, desc); + + tcg_temp_free_ptr(tcg_ctx, dest); + tcg_temp_free_i32(tcg_ctx, desc); + tcg_temp_free_i64(tcg_ctx, s1); + gen_set_label(tcg_ctx, over); + } + return true; + } + return false; +} + +GEN_OPIVV_TRANS(vmerge_vvm, opivv_vadc_check) +GEN_OPIVX_TRANS(vmerge_vxm, opivx_vadc_check) +GEN_OPIVI_TRANS(vmerge_vim, 0, vmerge_vxm, opivx_vadc_check) diff --git a/qemu/target/riscv/vector_helper.c b/qemu/target/riscv/vector_helper.c index 6fad9f0e..72bed439 100644 --- a/qemu/target/riscv/vector_helper.c +++ b/qemu/target/riscv/vector_helper.c @@ -2011,3 +2011,91 @@ GEN_VEXT_VX(vwmaccsu_vx_w, 4, 8, clearq) GEN_VEXT_VX(vwmaccus_vx_b, 1, 2, clearh) GEN_VEXT_VX(vwmaccus_vx_h, 2, 4, clearl) GEN_VEXT_VX(vwmaccus_vx_w, 4, 8, clearq) + +/* Vector Integer Merge and Move Instructions */ +#define GEN_VEXT_VMV_VV(NAME, ETYPE, H, CLEAR_FN) \ +void HELPER(NAME)(void *vd, void *vs1, CPURISCVState *env, \ + uint32_t desc) \ +{ \ + uint32_t vl = env->vl; \ + uint32_t esz = sizeof(ETYPE); \ + uint32_t vlmax = vext_maxsz(desc) / esz; \ + uint32_t i; \ + \ + for (i = 0; i < vl; i++) { \ + ETYPE s1 = *((ETYPE *)vs1 + H(i)); \ + *((ETYPE *)vd + H(i)) = s1; \ + } \ + CLEAR_FN(vd, vl, vl * esz, vlmax * esz); \ +} + +GEN_VEXT_VMV_VV(vmv_v_v_b, int8_t, H1, clearb) +GEN_VEXT_VMV_VV(vmv_v_v_h, int16_t, H2, clearh) +GEN_VEXT_VMV_VV(vmv_v_v_w, int32_t, H4, clearl) +GEN_VEXT_VMV_VV(vmv_v_v_d, int64_t, H8, clearq) + +#define GEN_VEXT_VMV_VX(NAME, ETYPE, H, CLEAR_FN) \ +void HELPER(NAME)(void *vd, uint64_t s1, CPURISCVState *env, \ + uint32_t desc) \ +{ \ + uint32_t vl = env->vl; \ + uint32_t esz = sizeof(ETYPE); \ + uint32_t vlmax = vext_maxsz(desc) / esz; \ + uint32_t i; \ + \ + for (i = 0; i < vl; i++) { \ + *((ETYPE *)vd + H(i)) = (ETYPE)s1; \ + } \ + CLEAR_FN(vd, vl, vl * esz, vlmax * esz); \ +} + +GEN_VEXT_VMV_VX(vmv_v_x_b, int8_t, H1, clearb) +GEN_VEXT_VMV_VX(vmv_v_x_h, int16_t, H2, clearh) +GEN_VEXT_VMV_VX(vmv_v_x_w, int32_t, H4, clearl) +GEN_VEXT_VMV_VX(vmv_v_x_d, int64_t, H8, clearq) + +#define GEN_VEXT_VMERGE_VV(NAME, ETYPE, H, CLEAR_FN) \ +void HELPER(NAME)(void *vd, void *v0, void *vs1, void *vs2, \ + CPURISCVState *env, uint32_t desc) \ +{ \ + uint32_t mlen = vext_mlen(desc); \ + uint32_t vl = env->vl; \ + uint32_t esz = sizeof(ETYPE); \ + uint32_t vlmax = vext_maxsz(desc) / esz; \ + uint32_t i; \ + \ + for (i = 0; i < vl; i++) { \ + ETYPE *vt = (!vext_elem_mask(v0, mlen, i) ? vs2 : vs1); \ + *((ETYPE *)vd + H(i)) = *(vt + H(i)); \ + } \ + CLEAR_FN(vd, vl, vl * esz, vlmax * esz); \ +} + +GEN_VEXT_VMERGE_VV(vmerge_vvm_b, int8_t, H1, clearb) +GEN_VEXT_VMERGE_VV(vmerge_vvm_h, int16_t, H2, clearh) +GEN_VEXT_VMERGE_VV(vmerge_vvm_w, int32_t, H4, clearl) +GEN_VEXT_VMERGE_VV(vmerge_vvm_d, int64_t, H8, clearq) + +#define GEN_VEXT_VMERGE_VX(NAME, ETYPE, H, CLEAR_FN) \ +void HELPER(NAME)(void *vd, void *v0, target_ulong s1, \ + void *vs2, CPURISCVState *env, uint32_t desc) \ +{ \ + uint32_t mlen = vext_mlen(desc); \ + uint32_t vl = env->vl; \ + uint32_t esz = sizeof(ETYPE); \ + uint32_t vlmax = vext_maxsz(desc) / esz; \ + uint32_t i; \ + \ + for (i = 0; i < vl; i++) { \ + ETYPE s2 = *((ETYPE *)vs2 + H(i)); \ + ETYPE d = (!vext_elem_mask(v0, mlen, i) ? s2 : \ + (ETYPE)(target_long)s1); \ + *((ETYPE *)vd + H(i)) = d; \ + } \ + CLEAR_FN(vd, vl, vl * esz, vlmax * esz); \ +} + +GEN_VEXT_VMERGE_VX(vmerge_vxm_b, int8_t, H1, clearb) +GEN_VEXT_VMERGE_VX(vmerge_vxm_h, int16_t, H2, clearh) +GEN_VEXT_VMERGE_VX(vmerge_vxm_w, int32_t, H4, clearl) +GEN_VEXT_VMERGE_VX(vmerge_vxm_d, int64_t, H8, clearq)