From 04fead0dcb9bfb64ee14e2886c060e4adcd72db1 Mon Sep 17 00:00:00 2001 From: Peter Maydell Date: Tue, 25 Sep 2018 21:19:32 -0400 Subject: [PATCH] target/arm: Start AArch32 CPUs with EL2 but not EL3 in Hyp mode The ARMv8 architecture defines that an AArch32 CPU starts in SVC mode, unless EL2 is the highest available EL, in which case it starts in Hyp mode. (In ARMv7 a CPU with EL2 but not EL3 was not a valid configuration, but we don't specifically reject this if the user asks for one.) Backports commit 060a65df056a5d6ca3a6a91e7bf150ca1fbccddf from qemu --- qemu/target/arm/cpu.c | 14 ++++++++++++-- 1 file changed, 12 insertions(+), 2 deletions(-) diff --git a/qemu/target/arm/cpu.c b/qemu/target/arm/cpu.c index 5c16172e..0cc1b6b4 100644 --- a/qemu/target/arm/cpu.c +++ b/qemu/target/arm/cpu.c @@ -191,8 +191,18 @@ static void arm_cpu_reset(CPUState *s) env->cp15.c15_cpar = 1; } #else - /* SVC mode with interrupts disabled. */ - env->uncached_cpsr = ARM_CPU_MODE_SVC; + /* + * If the highest available EL is EL2, AArch32 will start in Hyp + * mode; otherwise it starts in SVC. Note that if we start in + * AArch64 then these values in the uncached_cpsr will be ignored. + */ + if (arm_feature(env, ARM_FEATURE_EL2) && + !arm_feature(env, ARM_FEATURE_EL3)) { + env->uncached_cpsr = ARM_CPU_MODE_HYP; + } else { + env->uncached_cpsr = ARM_CPU_MODE_SVC; + } + env->daif = PSTATE_D | PSTATE_A | PSTATE_I | PSTATE_F; if (arm_feature(env, ARM_FEATURE_M)) {