From 05e72483f409327eac9b9fa53898d73816920172 Mon Sep 17 00:00:00 2001 From: Peter Maydell Date: Fri, 15 May 2020 23:37:51 -0400 Subject: [PATCH] target/arm: Convert Neon 3-reg-same compare insns to decodetree Convert the Neon integer 3-reg-same compare insns VCGE, VCGT, VCEQ, VACGE and VACGT to decodetree. Backports commit 727ff1d63213e6666e511956903b9e97a339ec7e from qemu --- qemu/target/arm/neon-dp.decode | 5 ++++ qemu/target/arm/translate-neon.inc.c | 6 +++++ qemu/target/arm/translate.c | 39 ++-------------------------- 3 files changed, 13 insertions(+), 37 deletions(-) diff --git a/qemu/target/arm/neon-dp.decode b/qemu/target/arm/neon-dp.decode index 4c2f8c77..29cf54c2 100644 --- a/qemu/target/arm/neon-dp.decode +++ b/qemu/target/arm/neon-dp.decode @@ -183,5 +183,10 @@ VABD_fp_3s 1111 001 1 0 . 1 . .... .... 1101 ... 0 .... @3same_fp VMLA_fp_3s 1111 001 0 0 . 0 . .... .... 1101 ... 1 .... @3same_fp VMLS_fp_3s 1111 001 0 0 . 1 . .... .... 1101 ... 1 .... @3same_fp VMUL_fp_3s 1111 001 1 0 . 0 . .... .... 1101 ... 1 .... @3same_fp +VCEQ_fp_3s 1111 001 0 0 . 0 . .... .... 1110 ... 0 .... @3same_fp +VCGE_fp_3s 1111 001 1 0 . 0 . .... .... 1110 ... 0 .... @3same_fp +VACGE_fp_3s 1111 001 1 0 . 0 . .... .... 1110 ... 1 .... @3same_fp +VCGT_fp_3s 1111 001 1 0 . 1 . .... .... 1110 ... 0 .... @3same_fp +VACGT_fp_3s 1111 001 1 0 . 1 . .... .... 1110 ... 1 .... @3same_fp VPMAX_fp_3s 1111 001 1 0 . 0 . .... .... 1111 ... 0 .... @3same_fp_q0 VPMIN_fp_3s 1111 001 1 0 . 1 . .... .... 1111 ... 0 .... @3same_fp_q0 diff --git a/qemu/target/arm/translate-neon.inc.c b/qemu/target/arm/translate-neon.inc.c index 73c6fbd7..231bb6f1 100644 --- a/qemu/target/arm/translate-neon.inc.c +++ b/qemu/target/arm/translate-neon.inc.c @@ -1133,6 +1133,12 @@ DO_3S_FP_GVEC(VMUL, gen_helper_gvec_fmul_s) return do_3same_fp(s, a, FUNC, READS_VD); \ } +DO_3S_FP(VCEQ, gen_helper_neon_ceq_f32, false) +DO_3S_FP(VCGE, gen_helper_neon_cge_f32, false) +DO_3S_FP(VCGT, gen_helper_neon_cgt_f32, false) +DO_3S_FP(VACGE, gen_helper_neon_acge_f32, false) +DO_3S_FP(VACGT, gen_helper_neon_acgt_f32, false) + static void gen_VMLA_fp_3s(TCGContext *s, TCGv_i32 vd, TCGv_i32 vn, TCGv_i32 vm, TCGv_ptr fpstatus) { diff --git a/qemu/target/arm/translate.c b/qemu/target/arm/translate.c index b13c010c..8a56f2b9 100644 --- a/qemu/target/arm/translate.c +++ b/qemu/target/arm/translate.c @@ -5560,6 +5560,8 @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn) case NEON_3R_VQDMULH_VQRDMULH: case NEON_3R_FLOAT_ARITH: case NEON_3R_FLOAT_MULTIPLY: + case NEON_3R_FLOAT_CMP: + case NEON_3R_FLOAT_ACMP: /* Already handled by decodetree */ return 1; } @@ -5574,17 +5576,6 @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn) return 1; /* VPMIN/VPMAX handled by decodetree */ } break; - case NEON_3R_FLOAT_CMP: - if (!u && size) { - /* no encoding for U=0 C=1x */ - return 1; - } - break; - case NEON_3R_FLOAT_ACMP: - if (!u) { - return 1; - } - break; case NEON_3R_FLOAT_MISC: /* VMAXNM/VMINNM in ARMv8 */ if (u && !arm_dc_feature(s, ARM_FEATURE_V8)) { @@ -5606,32 +5597,6 @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn) tmp = neon_load_reg(s, rn, pass); tmp2 = neon_load_reg(s, rm, pass); switch (op) { - case NEON_3R_FLOAT_CMP: - { - TCGv_ptr fpstatus = get_fpstatus_ptr(tcg_ctx, 1); - if (!u) { - gen_helper_neon_ceq_f32(tcg_ctx, tmp, tmp, tmp2, fpstatus); - } else { - if (size == 0) { - gen_helper_neon_cge_f32(tcg_ctx, tmp, tmp, tmp2, fpstatus); - } else { - gen_helper_neon_cgt_f32(tcg_ctx, tmp, tmp, tmp2, fpstatus); - } - } - tcg_temp_free_ptr(tcg_ctx, fpstatus); - break; - } - case NEON_3R_FLOAT_ACMP: - { - TCGv_ptr fpstatus = get_fpstatus_ptr(tcg_ctx, 1); - if (size == 0) { - gen_helper_neon_acge_f32(tcg_ctx, tmp, tmp, tmp2, fpstatus); - } else { - gen_helper_neon_acgt_f32(tcg_ctx, tmp, tmp, tmp2, fpstatus); - } - tcg_temp_free_ptr(tcg_ctx, fpstatus); - break; - } case NEON_3R_FLOAT_MINMAX: { TCGv_ptr fpstatus = get_fpstatus_ptr(tcg_ctx, 1);