From 085a3c9aab0ec94456c351ee3c462ca1ceaa5446 Mon Sep 17 00:00:00 2001 From: Richard Henderson Date: Wed, 21 Feb 2018 21:18:47 -0500 Subject: [PATCH] target-i386: Fix SMSW for 64-bit mode In non-64-bit modes, the instruction always stores 16 bits. But in 64-bit mode, when the destination is a register, the instruction can write 32 or 64 bits. Backports commit a657f79e32422634415c09f3f15c73d610297af5 from qemu --- qemu/target-i386/translate.c | 14 ++++++++------ 1 file changed, 8 insertions(+), 6 deletions(-) diff --git a/qemu/target-i386/translate.c b/qemu/target-i386/translate.c index ec8adc8c..ce56279c 100644 --- a/qemu/target-i386/translate.c +++ b/qemu/target-i386/translate.c @@ -7959,12 +7959,14 @@ case 0x101: CASE_MODRM_OP(4): /* smsw */ gen_svm_check_intercept(s, pc_start, SVM_EXIT_READ_CR0); -#if defined TARGET_X86_64 && defined HOST_WORDS_BIGENDIAN - tcg_gen_ld32u_tl(tcg_ctx, cpu_T0, cpu_env, offsetof(CPUX86State, cr[0]) + 4); -#else - tcg_gen_ld32u_tl(tcg_ctx, cpu_T0, cpu_env, offsetof(CPUX86State, cr[0])); -#endif - gen_ldst_modrm(env, s, modrm, MO_16, OR_TMP0, 1); + tcg_gen_ld_tl(tcg_ctx, cpu_T0, cpu_env, offsetof(CPUX86State, cr[0])); + if (CODE64(s)) { + mod = (modrm >> 6) & 3; + ot = (mod != 3 ? MO_16 : s->dflag); + } else { + ot = MO_16; + } + gen_ldst_modrm(env, s, modrm, ot, OR_TMP0, 1); break; CASE_MODRM_OP(6): /* lmsw */