diff --git a/qemu/target/riscv/cpu.h b/qemu/target/riscv/cpu.h
index 6bdfb542..f610ff0b 100644
--- a/qemu/target/riscv/cpu.h
+++ b/qemu/target/riscv/cpu.h
@@ -64,6 +64,7 @@
 #define RVA RV('A')
 #define RVF RV('F')
 #define RVD RV('D')
+#define RVV RV('V')
 #define RVC RV('C')
 #define RVS RV('S')
 #define RVU RV('U')
@@ -93,9 +94,20 @@ typedef struct CPURISCVState CPURISCVState;
 
 #include "pmp.h"
 
+#define RV_VLEN_MAX 512
+
 struct CPURISCVState {
     target_ulong gpr[32];
     uint64_t fpr[32]; /* assume both F and D extensions */
+
+    /* vector coprocessor state. */
+    uint64_t QEMU_ALIGNED(16, vreg[32 * RV_VLEN_MAX / 64]);
+    target_ulong vxrm;
+    target_ulong vxsat;
+    target_ulong vl;
+    target_ulong vstart;
+    target_ulong vtype;
+
     target_ulong pc;
     target_ulong load_res;
     target_ulong load_val;
diff --git a/qemu/target/riscv/translate.c b/qemu/target/riscv/translate.c
index b7a20cb3..83d19582 100644
--- a/qemu/target/riscv/translate.c
+++ b/qemu/target/riscv/translate.c
@@ -926,6 +926,7 @@ void riscv_translate_init(struct uc_struct *uc)
     }
 
     tcg_ctx->cpu_pc_risc = tcg_global_mem_new(tcg_ctx, tcg_ctx->cpu_env, offsetof(CPURISCVState, pc), "pc");
+    tcg_ctx->cpu_vl_risc = tcg_global_mem_new(tcg_ctx, tcg_ctx->cpu_env, offsetof(CPURISCVState, vl), "vl");
     tcg_ctx->load_res_risc = tcg_global_mem_new(tcg_ctx, tcg_ctx->cpu_env, offsetof(CPURISCVState, load_res),
                              "load_res");
     tcg_ctx->load_val_risc = tcg_global_mem_new(tcg_ctx, tcg_ctx->cpu_env, offsetof(CPURISCVState, load_val),
diff --git a/qemu/tcg/tcg.h b/qemu/tcg/tcg.h
index f321465c..978f7c88 100644
--- a/qemu/tcg/tcg.h
+++ b/qemu/tcg/tcg.h
@@ -847,6 +847,7 @@ struct TCGContext {
     TCGv_i64 cpu_fpr_risc[32]; /* assume F and D extensions */
     TCGv load_res_risc;
     TCGv load_val_risc;
+    TCGv cpu_vl_risc;
 
     /* qemu/target-sparc/translate.c */
     /* global register indexes */