From 09cfe29d5bc8ce9b9e1823c7a56c58f3afc1e350 Mon Sep 17 00:00:00 2001 From: Peter Maydell Date: Thu, 8 Mar 2018 09:36:57 -0500 Subject: [PATCH] hw/intc/armv7m_nvic: Implement SCR We were previously making the system control register (SCR) just RAZ/WI. Although we don't implement the functionality this register controls, we should at least provide the state, including the banked state for v8M. Backports register related changes in commit 24ac0fb129f9ce9dd96901b2377fc6271dc55b2b from qemu --- qemu/target/arm/cpu.h | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/qemu/target/arm/cpu.h b/qemu/target/arm/cpu.h index ed9cd4c3..3855e785 100644 --- a/qemu/target/arm/cpu.h +++ b/qemu/target/arm/cpu.h @@ -501,6 +501,7 @@ typedef struct CPUARMState { uint32_t aircr; /* only holds r/w state if security extn implemented */ uint32_t secure; /* Is CPU in Secure state? (not guest visible) */ uint32_t csselr[M_REG_NUM_BANKS]; + uint32_t scr[M_REG_NUM_BANKS]; } v7m; /* Information associated with an exception about to be taken: @@ -1233,6 +1234,12 @@ FIELD(V7M_CCR, STKALIGN, 9, 1) FIELD(V7M_CCR, DC, 16, 1) FIELD(V7M_CCR, IC, 17, 1) +/* V7M SCR bits */ +FIELD(V7M_SCR, SLEEPONEXIT, 1, 1) +FIELD(V7M_SCR, SLEEPDEEP, 2, 1) +FIELD(V7M_SCR, SLEEPDEEPS, 3, 1) +FIELD(V7M_SCR, SEVONPEND, 4, 1) + /* V7M AIRCR bits */ FIELD(V7M_AIRCR, VECTRESET, 0, 1) FIELD(V7M_AIRCR, VECTCLRACTIVE, 1, 1)