From 0d7be1a91328f2a33ad0ab278094326d0a633390 Mon Sep 17 00:00:00 2001 From: Igor Mammedov Date: Wed, 7 Mar 2018 21:33:12 -0500 Subject: [PATCH] sparc: embed sparc_def_t into CPUSPARCState Make CPUSPARCState::def embedded so it would be allocated as part of cpu instance and we won't have to worry about cleaning def pointer up mannualy on cpu destruction. Backports commit 576e1c4c239621482474ba7b495a41bab2d16ae5 from qemu --- qemu/target/sparc/cpu.c | 40 ++++++++++++++------------------ qemu/target/sparc/cpu.h | 8 +++---- qemu/target/sparc/int32_helper.c | 2 +- qemu/target/sparc/int64_helper.c | 2 +- qemu/target/sparc/ldst_helper.c | 14 +++++------ qemu/target/sparc/mmu_helper.c | 2 +- qemu/target/sparc/translate.c | 2 +- qemu/target/sparc/win_helper.c | 4 ++-- 8 files changed, 34 insertions(+), 40 deletions(-) diff --git a/qemu/target/sparc/cpu.c b/qemu/target/sparc/cpu.c index 1d70be25..c70e79e5 100644 --- a/qemu/target/sparc/cpu.c +++ b/qemu/target/sparc/cpu.c @@ -66,7 +66,7 @@ static void sparc_cpu_reset(CPUState *s) env->lsu = 0; #else env->mmuregs[0] &= ~(MMU_E | MMU_NF); - env->mmuregs[0] |= env->def->mmu_bm; + env->mmuregs[0] |= env->def.mmu_bm; #endif env->pc = 0; env->npc = env->pc + 4; @@ -113,18 +113,18 @@ static int cpu_sparc_register(struct uc_struct *uc, SPARCCPU *cpu, const char *c return -1; } - env->version = env->def->iu_version; - env->fsr = env->def->fpu_version; - env->nwindows = env->def->nwindows; + env->version = env->def.iu_version; + env->fsr = env->def.fpu_version; + env->nwindows = env->def.nwindows; #if !defined(TARGET_SPARC64) - env->mmuregs[0] |= env->def->mmu_version; + env->mmuregs[0] |= env->def.mmu_version; cpu_sparc_set_id(env, 0); - env->mxccregs[7] |= env->def->mxcc_version; + env->mxccregs[7] |= env->def.mxcc_version; #else - env->mmu_version = env->def->mmu_version; - env->maxtl = env->def->maxtl; - env->version |= env->def->maxtl << 8; - env->version |= env->def->nwindows - 1; + env->mmu_version = env->def.mmu_version; + env->maxtl = env->def.maxtl; + env->version |= env->def.maxtl << 8; + env->version |= env->def.nwindows - 1; #endif return 0; } @@ -592,7 +592,7 @@ static void sparc_cpu_parse_features(CPUState *cs, char *features, Error **errp) { SPARCCPU *cpu = SPARC_CPU(cs->uc, cs); - sparc_def_t *cpu_def = cpu->env.def; + sparc_def_t *cpu_def = &cpu->env.def; char *featurestr; uint32_t plus_features = 0; uint32_t minus_features = 0; @@ -854,8 +854,8 @@ static int sparc_cpu_realizefn(struct uc_struct *uc, DeviceState *dev, Error **e SPARCCPUClass *scc = SPARC_CPU_GET_CLASS(uc, obj); CPUSPARCState *env = &cpu->env; - if ((env->def->features & CPU_FEATURE_FLOAT)) { - env->def->features |= CPU_FEATURE_FLOAT128; + if ((env->def.features & CPU_FEATURE_FLOAT)) { + env->def.features |= CPU_FEATURE_FLOAT128; } #endif @@ -876,15 +876,9 @@ static void sparc_cpu_initfn(struct uc_struct *uc, Object *obj, void *opaque) cs->env_ptr = env; cpu_exec_init(cs, opaque); - env->def = g_memdup(scc->cpu_def, sizeof(*scc->cpu_def)); -} - -static void sparc_cpu_uninitfn(struct uc_struct *uc, Object *obj, void *opaque) -{ - SPARCCPU *cpu = SPARC_CPU(uc, obj); - CPUSPARCState *env = &cpu->env; - - g_free(env->def); + if (scc->cpu_def) { + env->def = *scc->cpu_def; + } } static void sparc_cpu_class_init(struct uc_struct *uc, ObjectClass *oc, void *data) @@ -964,7 +958,7 @@ void sparc_cpu_register_types(void *opaque) sparc_cpu_initfn, NULL, - sparc_cpu_uninitfn, + NULL, NULL, diff --git a/qemu/target/sparc/cpu.h b/qemu/target/sparc/cpu.h index e2db386d..ef038b2c 100644 --- a/qemu/target/sparc/cpu.h +++ b/qemu/target/sparc/cpu.h @@ -523,7 +523,7 @@ struct CPUSPARCState { #define SOFTINT_INTRMASK (0xFFFE) #define SOFTINT_REG_MASK (SOFTINT_STIMER|SOFTINT_INTRMASK|SOFTINT_TIMER) #endif - sparc_def_t *def; + sparc_def_t def; //void *irq_manager; //void (*qemu_irq_ack)(CPUSPARCState *env, void *irq_manager, int intno); @@ -679,7 +679,7 @@ static inline CPUSPARCState *cpu_init(struct uc_struct *uc, const char *cpu_mode #if defined (TARGET_SPARC64) static inline int cpu_has_hypervisor(CPUSPARCState *env1) { - return env1->def->features & CPU_FEATURE_HYPV; + return env1->def.features & CPU_FEATURE_HYPV; } static inline int cpu_hypervisor_mode(CPUSPARCState *env1) @@ -788,14 +788,14 @@ static inline void cpu_get_tb_cpu_state(CPUSPARCState *env, target_ulong *pc, if (env->pstate & PS_AM) { flags |= TB_FLAG_AM_ENABLED; } - if ((env->def->features & CPU_FEATURE_FLOAT) + if ((env->def.features & CPU_FEATURE_FLOAT) && (env->pstate & PS_PEF) && (env->fprs & FPRS_FEF)) { flags |= TB_FLAG_FPU_ENABLED; } flags |= env->asi << TB_FLAG_ASI_SHIFT; #else - if ((env->def->features & CPU_FEATURE_FLOAT) && env->psref) { + if ((env->def.features & CPU_FEATURE_FLOAT) && env->psref) { flags |= TB_FLAG_FPU_ENABLED; } #endif diff --git a/qemu/target/sparc/int32_helper.c b/qemu/target/sparc/int32_helper.c index e59d7dd3..e110725b 100644 --- a/qemu/target/sparc/int32_helper.c +++ b/qemu/target/sparc/int32_helper.c @@ -35,7 +35,7 @@ void sparc_cpu_do_interrupt(CPUState *cs) #if !defined(CONFIG_USER_ONLY) if (env->psret == 0) { if (cs->exception_index == 0x80 && - env->def->features & CPU_FEATURE_TA0_SHUTDOWN) { + env->def.features & CPU_FEATURE_TA0_SHUTDOWN) { qemu_system_shutdown_request(); } else { cpu_abort(cs, "Trap 0x%02x while interrupts disabled, Error state", diff --git a/qemu/target/sparc/int64_helper.c b/qemu/target/sparc/int64_helper.c index 4f30dcb9..4f1df66c 100644 --- a/qemu/target/sparc/int64_helper.c +++ b/qemu/target/sparc/int64_helper.c @@ -66,7 +66,7 @@ void sparc_cpu_do_interrupt(CPUState *cs) } } - if (env->def->features & CPU_FEATURE_GL) { + if (env->def.features & CPU_FEATURE_GL) { tsptr->tstate |= (env->gl & 7ULL) << 40; cpu_gl_switch_gregs(env, env->gl + 1); env->gl++; diff --git a/qemu/target/sparc/ldst_helper.c b/qemu/target/sparc/ldst_helper.c index 6d9c0b87..9abfdd8c 100644 --- a/qemu/target/sparc/ldst_helper.c +++ b/qemu/target/sparc/ldst_helper.c @@ -473,7 +473,7 @@ uint64_t helper_ld_asi(CPUSPARCState *env, target_ulong addr, case 0x00: /* Leon3 Cache Control */ case 0x08: /* Leon3 Instruction Cache config */ case 0x0C: /* Leon3 Date Cache config */ - if (env->def->features & CPU_FEATURE_CACHE_CTRL) { + if (env->def.features & CPU_FEATURE_CACHE_CTRL) { ret = leon3_cache_control_ld(env, addr, size); } break; @@ -698,7 +698,7 @@ void helper_st_asi(CPUSPARCState *env, target_ulong addr, uint64_t val, case 0x00: /* Leon3 Cache Control */ case 0x08: /* Leon3 Instruction Cache config */ case 0x0C: /* Leon3 Date Cache config */ - if (env->def->features & CPU_FEATURE_CACHE_CTRL) { + if (env->def.features & CPU_FEATURE_CACHE_CTRL) { leon3_cache_control_st(env, addr, val, size); } break; @@ -866,15 +866,15 @@ void helper_st_asi(CPUSPARCState *env, target_ulong addr, uint64_t val, /* Mappings generated during no-fault mode are invalid in normal mode. */ if ((oldreg ^ env->mmuregs[reg]) - & (MMU_NF | env->def->mmu_bm)) { + & (MMU_NF | env->def.mmu_bm)) { tlb_flush(CPU(cpu)); } break; case 1: /* Context Table Pointer Register */ - env->mmuregs[reg] = val & env->def->mmu_ctpr_mask; + env->mmuregs[reg] = val & env->def.mmu_ctpr_mask; break; case 2: /* Context Register */ - env->mmuregs[reg] = val & env->def->mmu_cxr_mask; + env->mmuregs[reg] = val & env->def.mmu_cxr_mask; if (oldreg != env->mmuregs[reg]) { /* we flush when the MMU context changes because QEMU has no MMU context support */ @@ -885,11 +885,11 @@ void helper_st_asi(CPUSPARCState *env, target_ulong addr, uint64_t val, case 4: /* Synchronous Fault Address Register */ break; case 0x10: /* TLB Replacement Control Register */ - env->mmuregs[reg] = val & env->def->mmu_trcr_mask; + env->mmuregs[reg] = val & env->def.mmu_trcr_mask; break; case 0x13: /* Synchronous Fault Status Register with Read and Clear */ - env->mmuregs[3] = val & env->def->mmu_sfsr_mask; + env->mmuregs[3] = val & env->def.mmu_sfsr_mask; break; case 0x14: /* Synchronous Fault Address Register */ env->mmuregs[4] = val; diff --git a/qemu/target/sparc/mmu_helper.c b/qemu/target/sparc/mmu_helper.c index 1c283c9c..1ea63a8a 100644 --- a/qemu/target/sparc/mmu_helper.c +++ b/qemu/target/sparc/mmu_helper.c @@ -93,7 +93,7 @@ static int get_physical_address(CPUSPARCState *env, hwaddr *physical, if (mmu_idx == MMU_PHYS_IDX) { *page_size = TARGET_PAGE_SIZE; /* Boot mode: instruction fetches are taken from PROM */ - if (rw == 2 && (env->mmuregs[0] & env->def->mmu_bm)) { + if (rw == 2 && (env->mmuregs[0] & env->def.mmu_bm)) { *physical = env->prom_addr | (address & 0x7ffffULL); *prot = PAGE_READ | PAGE_EXEC; return 0; diff --git a/qemu/target/sparc/translate.c b/qemu/target/sparc/translate.c index f10553a2..e5b6fac0 100644 --- a/qemu/target/sparc/translate.c +++ b/qemu/target/sparc/translate.c @@ -5936,7 +5936,7 @@ void gen_intermediate_code(CPUState *cs, TranslationBlock * tb) dc->npc = (target_ulong) tb->cs_base; dc->cc_op = CC_OP_DYNAMIC; dc->mem_idx = tb->flags & TB_FLAG_MMU_MASK; - dc->def = env->def; + dc->def = &env->def; dc->fpu_enabled = tb_fpu_enabled(tb->flags); dc->address_mask_32bit = tb_am_enabled(tb->flags); dc->singlestep = (cs->singlestep_enabled); // || singlestep); diff --git a/qemu/target/sparc/win_helper.c b/qemu/target/sparc/win_helper.c index a8dd53fa..de7096c2 100644 --- a/qemu/target/sparc/win_helper.c +++ b/qemu/target/sparc/win_helper.c @@ -291,7 +291,7 @@ void helper_wrcwp(CPUSPARCState *env, target_ulong new_cwp) static inline uint64_t *get_gregset(CPUSPARCState *env, uint32_t pstate) { - if (env->def->features & CPU_FEATURE_GL) { + if (env->def.features & CPU_FEATURE_GL) { return env->glregs + (env->gl & 7) * 8; } @@ -339,7 +339,7 @@ void cpu_change_pstate(CPUSPARCState *env, uint32_t new_pstate) uint32_t pstate_regs, new_pstate_regs; uint64_t *src, *dst; - if (env->def->features & CPU_FEATURE_GL) { + if (env->def.features & CPU_FEATURE_GL) { /* PS_AG, IG and MG are not implemented in this case */ new_pstate &= ~(PS_AG | PS_IG | PS_MG); env->pstate = new_pstate;