From 0ed5787f89260b8ab5d5eb7dae42141e2f8ccccc Mon Sep 17 00:00:00 2001
From: Peter Maydell <peter.maydell@linaro.org>
Date: Sat, 17 Feb 2018 14:51:26 -0500
Subject: [PATCH] target-arm: Report S/NS status in the CPU debug logs

If this CPU supports EL3, enhance the printing of the current
CPU mode in debug logging to distinguish S from NS modes as
appropriate.

Backports commit 06e5cf7acd1f94ab7c1cd6945974a1f039672940 from qemu
---
 qemu/target-arm/translate-a64.c | 11 ++++++++++-
 qemu/target-arm/translate.c     | 12 ++++++++++--
 2 files changed, 20 insertions(+), 3 deletions(-)

diff --git a/qemu/target-arm/translate-a64.c b/qemu/target-arm/translate-a64.c
index 93a0a9dc..475723a6 100644
--- a/qemu/target-arm/translate-a64.c
+++ b/qemu/target-arm/translate-a64.c
@@ -140,6 +140,7 @@ void aarch64_cpu_dump_state(CPUState *cs, FILE *f,
     uint32_t psr = pstate_read(env);
     int i;
     int el = arm_current_el(env);
+    const char *ns_status;
 
     cpu_fprintf(f, "PC=%016"PRIx64"  SP=%016"PRIx64"\n",
             env->pc, env->xregs[31]);
@@ -151,12 +152,20 @@ void aarch64_cpu_dump_state(CPUState *cs, FILE *f,
             cpu_fprintf(f, " ");
         }
     }
-    cpu_fprintf(f, "\nPSTATE=%08x %c%c%c%c EL%d%c\n",
+
+    if (arm_feature(env, ARM_FEATURE_EL3) && el != 3) {
+        ns_status = env->cp15.scr_el3 & SCR_NS ? "NS " : "S ";
+    } else {
+        ns_status = "";
+    }
+
+    cpu_fprintf(f, "\nPSTATE=%08x %c%c%c%c %sEL%d%c\n",
                 psr,
                 psr & PSTATE_N ? 'N' : '-',
                 psr & PSTATE_Z ? 'Z' : '-',
                 psr & PSTATE_C ? 'C' : '-',
                 psr & PSTATE_V ? 'V' : '-',
+                ns_status,
                 el,
                 psr & PSTATE_SP ? 'h' : 't');
 
diff --git a/qemu/target-arm/translate.c b/qemu/target-arm/translate.c
index f8b00f3e..1608997b 100644
--- a/qemu/target-arm/translate.c
+++ b/qemu/target-arm/translate.c
@@ -11803,6 +11803,7 @@ void arm_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function cpu_fprintf,
     ARMCPU *cpu = ARM_CPU(cs);
     CPUARMState *env = &cpu->env;
     int i;
+    const char *ns_status;
 
     if (is_a64(env)) {
         aarch64_cpu_dump_state(cs, f, cpu_fprintf, flags);
@@ -11817,10 +11818,16 @@ void arm_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function cpu_fprintf,
             cpu_fprintf(f, " ");
     }
 
+    if (arm_feature(env, ARM_FEATURE_EL3) &&
+        (psr & CPSR_M) != ARM_CPU_MODE_MON) {
+        ns_status = env->cp15.scr_el3 & SCR_NS ? "NS " : "S ";
+    } else {
+        ns_status = "";
+    }
+
     if (arm_feature(env, ARM_FEATURE_M)) {
         uint32_t xpsr = xpsr_read(env);
         const char *mode;
-        const char *ns_status = "";
 
         if (arm_feature(env, ARM_FEATURE_M_SECURITY)) {
             ns_status = env->v7m.secure ? "S " : "NS ";
@@ -11854,13 +11861,14 @@ void arm_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function cpu_fprintf,
             ns_status = env->cp15.scr_el3 & SCR_NS ? "NS " : "S ";
         }
 
-        cpu_fprintf(f, "PSR=%08x %c%c%c%c %c %s%d\n",
+        cpu_fprintf(f, "PSR=%08x %c%c%c%c %c %s%s%d\n",
                     psr,
                     psr & (1 << 31) ? 'N' : '-',
                     psr & (1 << 30) ? 'Z' : '-',
                     psr & (1 << 29) ? 'C' : '-',
                     psr & (1 << 28) ? 'V' : '-',
                     psr & CPSR_T ? 'T' : 'A',
+                    ns_status,
                     cpu_mode_names[psr & 0xf], (psr & 0x10) ? 32 : 26);
     }