From 0f0b2e0bd851b137719beecca0408e84af690af9 Mon Sep 17 00:00:00 2001 From: Peter Maydell Date: Sat, 2 Jun 2018 10:02:37 -0400 Subject: [PATCH] target/arm: Honour FPCR.FZ in FRECPX The FRECPX instructions should (like most other floating point operations) honour the FPCR.FZ bit which specifies whether input denormals should be flushed to zero (or FZ16 for the half-precision version). We forgot to implement this, which doesn't affect the results (since the calculation doesn't actually care about the mantissa bits) but did mean we were failing to set the FPSR.IDC bit. Backports commit 2cfbf36ec07f7cac1aabb3b86f1c95c8a55424ba from qemu --- qemu/target/arm/helper-a64.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/qemu/target/arm/helper-a64.c b/qemu/target/arm/helper-a64.c index ead86122..4573ac58 100644 --- a/qemu/target/arm/helper-a64.c +++ b/qemu/target/arm/helper-a64.c @@ -382,6 +382,8 @@ float16 HELPER(frecpx_f16)(float16 a, void *fpstp) return nan; } + a = float16_squash_input_denormal(a, fpst); + val16 = float16_val(a); sbit = 0x8000 & val16; exp = extract32(val16, 10, 5); @@ -411,6 +413,8 @@ float32 HELPER(frecpx_f32)(float32 a, void *fpstp) return nan; } + a = float32_squash_input_denormal(a, fpst); + val32 = float32_val(a); sbit = 0x80000000ULL & val32; exp = extract32(val32, 23, 8); @@ -440,6 +444,8 @@ float64 HELPER(frecpx_f64)(float64 a, void *fpstp) return nan; } + a = float64_squash_input_denormal(a, fpst); + val64 = float64_val(a); sbit = 0x8000000000000000ULL & val64; exp = extract64(float64_val(a), 52, 11);