From 1081e5e7a4515415ec30472f1fe7ce806ee7a58a Mon Sep 17 00:00:00 2001 From: Richard Henderson Date: Mon, 8 Oct 2018 11:10:55 -0400 Subject: [PATCH] target/arm: Define ID_AA64ZFR0_EL1 Given that the only field defined for this new register may only be 0, we don't actually need to change anything except the name. Backports commit 9516d7725ec1deaa6ef5ccc5a26d005650d6c524 from qemu --- qemu/target/arm/helper.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/qemu/target/arm/helper.c b/qemu/target/arm/helper.c index ff874466..4a1a0423 100644 --- a/qemu/target/arm/helper.c +++ b/qemu/target/arm/helper.c @@ -4380,7 +4380,8 @@ void register_cp_regs_for_features(ARMCPU *cpu) PL1_R, 0, NULL, 0 }, { "ID_AA64PFR3_EL1_RESERVED", 0,0,4, 3,0,3, ARM_CP_STATE_AA64, ARM_CP_CONST, PL1_R, 0, NULL, 0,}, - { "ID_AA64PFR4_EL1_RESERVED", 0,0,4, 3,0,4, ARM_CP_STATE_AA64, ARM_CP_CONST, + { "ID_AA64ZFR0_EL1", 0,0,4, 3,0,4, ARM_CP_STATE_AA64, ARM_CP_CONST, + /* At present, only SVEver == 0 is defined anyway. */ PL1_R, 0, NULL, 0 }, { "ID_AA64PFR5_EL1_RESERVED", 0,0,4, 3,0,5, ARM_CP_STATE_AA64, ARM_CP_CONST, PL1_R, 0, NULL, 0 },