From 13bad2c2348bfd12ef4abf0f5e35bd6eaf1f647b Mon Sep 17 00:00:00 2001 From: Peter Maydell Date: Sun, 4 Mar 2018 20:50:58 -0500 Subject: [PATCH] target/arm: Register second AddressSpace for secure v8M CPUs If a v8M CPU supports the security extension then we need to give it two AddressSpaces, the same way we do already for an A profile core with EL3. Backports commit 1d2091bc75ab7f9e2c43082f361a528a63c79527 from qemu --- qemu/target/arm/cpu.c | 12 +++++------- 1 file changed, 5 insertions(+), 7 deletions(-) diff --git a/qemu/target/arm/cpu.c b/qemu/target/arm/cpu.c index 3b049ffb..52691ceb 100644 --- a/qemu/target/arm/cpu.c +++ b/qemu/target/arm/cpu.c @@ -631,15 +631,11 @@ static int arm_cpu_realizefn(struct uc_struct *uc, DeviceState *dev, Error **err arm_cpu_register_gdb_regs_for_features(cpu); #ifndef CONFIG_USER_ONLY - if (cpu->has_el3) { - cs->num_ases = 2; - } else { - cs->num_ases = 1; - } - - if (cpu->has_el3) { + if (cpu->has_el3 || arm_feature(env, ARM_FEATURE_M_SECURITY)) { AddressSpace *as; + cs->num_ases = 2; + if (!cpu->secure_memory) { cpu->secure_memory = cs->memory; } @@ -647,6 +643,8 @@ static int arm_cpu_realizefn(struct uc_struct *uc, DeviceState *dev, Error **err cpu->secure_memory, "cpu-secure-memory"); cpu_address_space_init(cs, as, ARMASIdx_S); + } else { + cs->num_ases = 1; } cpu_address_space_init(cs, address_space_init_shareable(uc,