From 14d48974a4ae57b221bca5cb7d139bb9c3c369f5 Mon Sep 17 00:00:00 2001 From: Richard Henderson Date: Thu, 16 May 2019 17:19:26 -0400 Subject: [PATCH] target/mips: Convert to CPUClass::tlb_fill Note that env->active_tc.PC is removed from the qemu_log as that value is garbage. The PC isn't recovered until cpu_restore_state, called from cpu_loop_exit_restore, called from do_raise_exception_err. Backports commit 931d019f5b2e7bbacb162869497123be402ddd86 from qemu --- qemu/header_gen.py | 2 +- qemu/mips.h | 2 +- qemu/mips64.h | 2 +- qemu/mips64el.h | 2 +- qemu/mipsel.h | 2 +- qemu/target/mips/cpu.c | 7 +++--- qemu/target/mips/helper.c | 44 ++++++++++++++++++++---------------- qemu/target/mips/internal.h | 5 ++-- qemu/target/mips/op_helper.c | 15 ------------ 9 files changed, 36 insertions(+), 45 deletions(-) diff --git a/qemu/header_gen.py b/qemu/header_gen.py index 25391b45..a2e48ebb 100644 --- a/qemu/header_gen.py +++ b/qemu/header_gen.py @@ -5432,9 +5432,9 @@ mips_symbols = ( 'mips_cpu_do_unaligned_access', 'mips_cpu_exec_interrupt', 'mips_cpu_get_phys_page_debug', - 'mips_cpu_handle_mmu_fault', 'mips_cpu_list', 'mips_cpu_register_types', + 'mips_cpu_tlb_fill', 'mips_cpu_unassigned_access', 'mips_defs', 'mips_defs_number', diff --git a/qemu/mips.h b/qemu/mips.h index bcb622c1..da0de825 100644 --- a/qemu/mips.h +++ b/qemu/mips.h @@ -4320,9 +4320,9 @@ #define mips_cpu_do_unaligned_access mips_cpu_do_unaligned_access_mips #define mips_cpu_exec_interrupt mips_cpu_exec_interrupt_mips #define mips_cpu_get_phys_page_debug mips_cpu_get_phys_page_debug_mips -#define mips_cpu_handle_mmu_fault mips_cpu_handle_mmu_fault_mips #define mips_cpu_list mips_cpu_list_mips #define mips_cpu_register_types mips_cpu_register_types_mips +#define mips_cpu_tlb_fill mips_cpu_tlb_fill_mips #define mips_cpu_unassigned_access mips_cpu_unassigned_access_mips #define mips_defs mips_defs_mips #define mips_defs_number mips_defs_number_mips diff --git a/qemu/mips64.h b/qemu/mips64.h index f2473f8c..b17b7267 100644 --- a/qemu/mips64.h +++ b/qemu/mips64.h @@ -4320,9 +4320,9 @@ #define mips_cpu_do_unaligned_access mips_cpu_do_unaligned_access_mips64 #define mips_cpu_exec_interrupt mips_cpu_exec_interrupt_mips64 #define mips_cpu_get_phys_page_debug mips_cpu_get_phys_page_debug_mips64 -#define mips_cpu_handle_mmu_fault mips_cpu_handle_mmu_fault_mips64 #define mips_cpu_list mips_cpu_list_mips64 #define mips_cpu_register_types mips_cpu_register_types_mips64 +#define mips_cpu_tlb_fill mips_cpu_tlb_fill_mips64 #define mips_cpu_unassigned_access mips_cpu_unassigned_access_mips64 #define mips_defs mips_defs_mips64 #define mips_defs_number mips_defs_number_mips64 diff --git a/qemu/mips64el.h b/qemu/mips64el.h index 46183d76..0a9583fa 100644 --- a/qemu/mips64el.h +++ b/qemu/mips64el.h @@ -4320,9 +4320,9 @@ #define mips_cpu_do_unaligned_access mips_cpu_do_unaligned_access_mips64el #define mips_cpu_exec_interrupt mips_cpu_exec_interrupt_mips64el #define mips_cpu_get_phys_page_debug mips_cpu_get_phys_page_debug_mips64el -#define mips_cpu_handle_mmu_fault mips_cpu_handle_mmu_fault_mips64el #define mips_cpu_list mips_cpu_list_mips64el #define mips_cpu_register_types mips_cpu_register_types_mips64el +#define mips_cpu_tlb_fill mips_cpu_tlb_fill_mips64el #define mips_cpu_unassigned_access mips_cpu_unassigned_access_mips64el #define mips_defs mips_defs_mips64el #define mips_defs_number mips_defs_number_mips64el diff --git a/qemu/mipsel.h b/qemu/mipsel.h index 79b89ae1..7c184995 100644 --- a/qemu/mipsel.h +++ b/qemu/mipsel.h @@ -4320,9 +4320,9 @@ #define mips_cpu_do_unaligned_access mips_cpu_do_unaligned_access_mipsel #define mips_cpu_exec_interrupt mips_cpu_exec_interrupt_mipsel #define mips_cpu_get_phys_page_debug mips_cpu_get_phys_page_debug_mipsel -#define mips_cpu_handle_mmu_fault mips_cpu_handle_mmu_fault_mipsel #define mips_cpu_list mips_cpu_list_mipsel #define mips_cpu_register_types mips_cpu_register_types_mipsel +#define mips_cpu_tlb_fill mips_cpu_tlb_fill_mipsel #define mips_cpu_unassigned_access mips_cpu_unassigned_access_mipsel #define mips_defs mips_defs_mipsel #define mips_defs_number mips_defs_number_mipsel diff --git a/qemu/target/mips/cpu.c b/qemu/target/mips/cpu.c index 8f7b2847..766b74ad 100644 --- a/qemu/target/mips/cpu.c +++ b/qemu/target/mips/cpu.c @@ -171,14 +171,15 @@ static void mips_cpu_class_init(struct uc_struct *uc, ObjectClass *c, void *data cc->cpu_exec_interrupt = mips_cpu_exec_interrupt; cc->set_pc = mips_cpu_set_pc; cc->synchronize_from_tb = mips_cpu_synchronize_from_tb; -#ifdef CONFIG_USER_ONLY - cc->handle_mmu_fault = mips_cpu_handle_mmu_fault; -#else +#ifndef CONFIG_USER_ONLY cc->do_unassigned_access = mips_cpu_unassigned_access; cc->do_unaligned_access = mips_cpu_do_unaligned_access; cc->get_phys_page_debug = mips_cpu_get_phys_page_debug; #endif +#ifdef CONFIG_TCG cc->tcg_initialize = mips_tcg_init; + cc->tlb_fill = mips_cpu_tlb_fill; +#endif } static void mips_cpu_cpudef_class_init(struct uc_struct *uc, ObjectClass *oc, void *data) diff --git a/qemu/target/mips/helper.c b/qemu/target/mips/helper.c index d2aa4329..20787f69 100644 --- a/qemu/target/mips/helper.c +++ b/qemu/target/mips/helper.c @@ -862,30 +862,25 @@ refill: #endif #endif -int mips_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int size, int rw, - int mmu_idx) +bool mips_cpu_tlb_fill(CPUState *cs, vaddr address, int size, + MMUAccessType access_type, int mmu_idx, + bool probe, uintptr_t retaddr) { MIPSCPU *cpu = MIPS_CPU(cs->uc, cs); CPUMIPSState *env = &cpu->env; #if !defined(CONFIG_USER_ONLY) hwaddr physical; int prot; - int access_type; + int mips_access_type; #endif int ret = TLBRET_BADADDR; -#if 0 - log_cpu_state(cs, 0); -#endif - qemu_log("%s pc " TARGET_FMT_lx " ad %" VADDR_PRIx " rw %d mmu_idx %d\n", - __func__, env->active_tc.PC, address, rw, mmu_idx); - /* data access */ #if !defined(CONFIG_USER_ONLY) /* XXX: put correct access by using cpu_restore_state() correctly */ - access_type = ACCESS_INT; - ret = get_physical_address(env, &physical, &prot, - address, rw, access_type, mmu_idx); + mips_access_type = ACCESS_INT; + ret = get_physical_address(env, &physical, &prot, address, + access_type, mips_access_type, mmu_idx); switch (ret) { case TLBRET_MATCH: qemu_log_mask(CPU_LOG_MMU, @@ -902,7 +897,7 @@ int mips_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int size, int rw, tlb_set_page(cs, address & TARGET_PAGE_MASK, physical & TARGET_PAGE_MASK, prot | PAGE_EXEC, mmu_idx, TARGET_PAGE_SIZE); - return 0; + return true; } #if !defined(TARGET_MIPS64) if ((ret == TLBRET_NOMATCH) && (env->tlb->nb_tlb > 1)) { @@ -913,26 +908,35 @@ int mips_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int size, int rw, int mode = (env->hflags & MIPS_HFLAG_KSU); bool ret_walker; env->hflags &= ~MIPS_HFLAG_KSU; - ret_walker = page_table_walk_refill(env, address, rw, mmu_idx); + ret_walker = page_table_walk_refill(env, address, access_type, mmu_idx); env->hflags |= mode; if (ret_walker) { - ret = get_physical_address(env, &physical, &prot, - address, rw, access_type, mmu_idx); + ret = get_physical_address(env, &physical, &prot, address, + access_type, mips_access_type, mmu_idx); if (ret == TLBRET_MATCH) { tlb_set_page(cs, address & TARGET_PAGE_MASK, physical & TARGET_PAGE_MASK, prot | PAGE_EXEC, mmu_idx, TARGET_PAGE_SIZE); - return 0; + return true; } } } #endif + if (probe) { + return false; + } #endif - raise_mmu_exception(env, address, rw, ret); - return 1; + raise_mmu_exception(env, address, access_type, ret); + do_raise_exception_err(env, cs->exception_index, env->error_code, retaddr); +} + +#ifndef CONFIG_USER_ONLY +void tlb_fill(CPUState *cs, target_ulong addr, int size, + MMUAccessType access_type, int mmu_idx, uintptr_t retaddr) +{ + mips_cpu_tlb_fill(cs, addr, size, access_type, mmu_idx, false, retaddr); } -#if !defined(CONFIG_USER_ONLY) hwaddr cpu_mips_translate_address(CPUMIPSState *env, target_ulong address, int rw) { hwaddr physical; diff --git a/qemu/target/mips/internal.h b/qemu/target/mips/internal.h index 92329b93..082f87ba 100644 --- a/qemu/target/mips/internal.h +++ b/qemu/target/mips/internal.h @@ -203,8 +203,9 @@ void cpu_mips_start_count(CPUMIPSState *env); void cpu_mips_stop_count(CPUMIPSState *env); /* helper.c */ -int mips_cpu_handle_mmu_fault(CPUState *cpu, vaddr address, int size, int rw, - int mmu_idx); +bool mips_cpu_tlb_fill(CPUState *cs, vaddr address, int size, + MMUAccessType access_type, int mmu_idx, + bool probe, uintptr_t retaddr); /* op_helper.c */ uint32_t float_class_s(uint32_t arg, float_status *fst); diff --git a/qemu/target/mips/op_helper.c b/qemu/target/mips/op_helper.c index 7d889254..7406a208 100644 --- a/qemu/target/mips/op_helper.c +++ b/qemu/target/mips/op_helper.c @@ -2657,21 +2657,6 @@ void mips_cpu_do_unaligned_access(CPUState *cs, vaddr addr, do_raise_exception_err(env, excp, error_code, retaddr); } -void tlb_fill(CPUState *cs, target_ulong addr, int size, - MMUAccessType access_type, int mmu_idx, uintptr_t retaddr) -{ - int ret; - - ret = mips_cpu_handle_mmu_fault(cs, addr, size, access_type, mmu_idx); - if (ret) { - MIPSCPU *cpu = MIPS_CPU(cs->uc, cs); - CPUMIPSState *env = &cpu->env; - - do_raise_exception_err(env, cs->exception_index, - env->error_code, retaddr); - } -} - void mips_cpu_unassigned_access(CPUState *cs, hwaddr addr, bool is_write, bool is_exec, int unused, unsigned size)