From 18e9c4805f2385b0f97c29f96e5771963affc0e8 Mon Sep 17 00:00:00 2001 From: Richard Henderson Date: Sat, 21 Mar 2020 17:55:09 -0400 Subject: [PATCH] target/arm: Flush high bits of sve register after AdvSIMD EXT Writes to AdvSIMD registers flush the bits above 128. Backports commit 78cedfabd53b6f64e7e64fc84878d848e5df1d08 from qemu --- qemu/target/arm/translate-a64.c | 1 + 1 file changed, 1 insertion(+) diff --git a/qemu/target/arm/translate-a64.c b/qemu/target/arm/translate-a64.c index b757e593..69cadeb1 100644 --- a/qemu/target/arm/translate-a64.c +++ b/qemu/target/arm/translate-a64.c @@ -7148,6 +7148,7 @@ static void disas_simd_ext(DisasContext *s, uint32_t insn) tcg_temp_free_i64(tcg_ctx, tcg_resl); write_vec_element(s, tcg_resh, rd, 1, MO_64); tcg_temp_free_i64(tcg_ctx, tcg_resh); + clear_vec_high(s, true, rd); } /* TBL/TBX