diff --git a/qemu/target/arm/cpu.h b/qemu/target/arm/cpu.h
index 0bad697d..533b8aa8 100644
--- a/qemu/target/arm/cpu.h
+++ b/qemu/target/arm/cpu.h
@@ -910,7 +910,14 @@ static inline void aarch64_sve_change_el(CPUARMState *env, int o,
 { }
 #endif
 
+#if !defined(CONFIG_TCG)
+static inline target_ulong do_arm_semihosting(CPUARMState *env)
+{
+    g_assert_not_reached();
+}
+#else
 target_ulong do_arm_semihosting(CPUARMState *env);
+#endif
 void aarch64_sync_32_to_64(CPUARMState *env);
 void aarch64_sync_64_to_32(CPUARMState *env);
 
diff --git a/qemu/target/arm/helper.c b/qemu/target/arm/helper.c
index c3b9652f..4d433cf1 100644
--- a/qemu/target/arm/helper.c
+++ b/qemu/target/arm/helper.c
@@ -18,8 +18,10 @@
 #include "qemu/crc32c.h"
 #include "exec/exec-all.h"
 #include "exec/cpu_ldst.h"
-#include "arm_ldst.h"
 #include "qemu/range.h"
+#ifdef CONFIG_TCG
+#include "arm_ldst.h"
+#endif
 
 #define ARM_CPU_FREQ 1000000000 /* FIXME: 1 GHz, should be configurable */
 
@@ -10214,6 +10216,7 @@ static inline bool check_for_semihosting(CPUState *cs)
 
 // Unicorn: ifdefd out
 #if 0
+#ifdef CONFIG_TCG
     /*
      * Check whether this exception is a semihosting call; if so
      * then handle it and return true; otherwise return false.
@@ -10293,6 +10296,9 @@ static inline bool check_for_semihosting(CPUState *cs)
         env->regs[0] = do_arm_semihosting(env);
         return true;
     }
+#else
+    return false;
+#endif
 #endif
 }