From 19c937f2cc30e1a0d613d46aa307bfbd57d928d5 Mon Sep 17 00:00:00 2001 From: Alistair Francis Date: Mon, 8 Mar 2021 15:17:56 -0500 Subject: [PATCH] target/riscv: Add a TYPE_RISCV_CPU_BASE CPU Backports c0a635f3973d974befb954463287786fd988bb64 --- qemu/target/riscv/cpu.h | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/qemu/target/riscv/cpu.h b/qemu/target/riscv/cpu.h index 29f5f383..8324ec56 100644 --- a/qemu/target/riscv/cpu.h +++ b/qemu/target/riscv/cpu.h @@ -48,6 +48,12 @@ #define TYPE_RISCV_CPU_SIFIVE_U34 RISCV_CPU_TYPE_NAME("sifive-u34") #define TYPE_RISCV_CPU_SIFIVE_U54 RISCV_CPU_TYPE_NAME("sifive-u54") +#if defined(TARGET_RISCV32) +# define TYPE_RISCV_CPU_BASE TYPE_RISCV_CPU_BASE32 +#elif defined(TARGET_RISCV64) +# define TYPE_RISCV_CPU_BASE TYPE_RISCV_CPU_BASE64 +#endif + #define RV32 ((target_ulong)1 << (TARGET_LONG_BITS - 2)) #define RV64 ((target_ulong)2 << (TARGET_LONG_BITS - 2))