diff --git a/bindings/java/unicorn_Unicorn.c b/bindings/java/unicorn_Unicorn.c index 18af09f8..c9cef604 100644 --- a/bindings/java/unicorn_Unicorn.c +++ b/bindings/java/unicorn_Unicorn.c @@ -20,7 +20,7 @@ Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. */ #include -#include +#include "platform.h" #include #include diff --git a/bindings/msvc/samples/main.c b/bindings/msvc/samples/main.c index 1539d68c..0b99d83c 100644 --- a/bindings/msvc/samples/main.c +++ b/bindings/msvc/samples/main.c @@ -22,8 +22,7 @@ // posix specific #else // _MSC_VER -#include -#include +#include "platform.h" #include #endif // _MSC_VER diff --git a/bindings/msvc_native/config-host.h b/bindings/msvc_native/config-host.h index b01191af..98913d6c 100644 --- a/bindings/msvc_native/config-host.h +++ b/bindings/msvc_native/config-host.h @@ -1,4 +1,9 @@ -/* This is a hand made version for MSVC support */ +/* +This is a hand made version for MSVC native support +It seems that most of these are not used by any source files. +The only one that I can see being used is: CONFIG_CPUID_H +*/ + #define CONFIG_QEMU_CONFDIR "c:/Program Files/QEMU" #define CONFIG_QEMU_DATADIR "" #define CONFIG_QEMU_DOCDIR "c:/Program Files/QEMU" diff --git a/bindings/msvc_native/msvc_native.sln b/bindings/msvc_native/msvc_native.sln index c26a4eb3..2571942c 100644 --- a/bindings/msvc_native/msvc_native.sln +++ b/bindings/msvc_native/msvc_native.sln @@ -1,7 +1,7 @@  Microsoft Visual Studio Solution File, Format Version 12.00 # Visual Studio 2012 -Project("{8BC9CEB8-8B4A-11D0-8D11-00A0C91BC942}") = "unicorn", "unicorn\unicorn.vcxproj", "{B6EFD6D7-C2D4-4FBB-B363-2E08CE09CC96}" +Project("{8BC9CEB8-8B4A-11D0-8D11-00A0C91BC942}") = "x86_64-softmmu", "x86_64-softmmu\x86_64-softmmu.vcxproj", "{17077E86-AE7C-41AF-86ED-2BAC03B019BC}" EndProject Global GlobalSection(SolutionConfigurationPlatforms) = preSolution @@ -9,10 +9,10 @@ Global Release|Win32 = Release|Win32 EndGlobalSection GlobalSection(ProjectConfigurationPlatforms) = postSolution - {B6EFD6D7-C2D4-4FBB-B363-2E08CE09CC96}.Debug|Win32.ActiveCfg = Debug|Win32 - {B6EFD6D7-C2D4-4FBB-B363-2E08CE09CC96}.Debug|Win32.Build.0 = Debug|Win32 - {B6EFD6D7-C2D4-4FBB-B363-2E08CE09CC96}.Release|Win32.ActiveCfg = Release|Win32 - {B6EFD6D7-C2D4-4FBB-B363-2E08CE09CC96}.Release|Win32.Build.0 = Release|Win32 + {17077E86-AE7C-41AF-86ED-2BAC03B019BC}.Debug|Win32.ActiveCfg = Debug|Win32 + {17077E86-AE7C-41AF-86ED-2BAC03B019BC}.Debug|Win32.Build.0 = Debug|Win32 + {17077E86-AE7C-41AF-86ED-2BAC03B019BC}.Release|Win32.ActiveCfg = Release|Win32 + {17077E86-AE7C-41AF-86ED-2BAC03B019BC}.Release|Win32.Build.0 = Release|Win32 EndGlobalSection GlobalSection(SolutionProperties) = preSolution HideSolutionNode = FALSE diff --git a/bindings/msvc_native/unicorn/unicorn.vcxproj b/bindings/msvc_native/unicorn/unicorn.vcxproj index d8a259de..452809fd 100644 --- a/bindings/msvc_native/unicorn/unicorn.vcxproj +++ b/bindings/msvc_native/unicorn/unicorn.vcxproj @@ -365,7 +365,7 @@ Level3 Disabled - WIN32;_DEBUG;_LIB;%(PreprocessorDefinitions);_CRT_SECURE_NO_WARNINGS;inline=__inline;__func__=__FUNCTION__ + WIN32;_DEBUG;_LIB;%(PreprocessorDefinitions);_CRT_SECURE_NO_WARNINGS;inline=__inline;__func__=__FUNCTION__;UNICORN_HAS_X86;UNICORN_HAS_ARM;UNICORN_HAS_M68K;UNICORN_HAS_ARM64;UNICORN_HAS_MIPS;UNICORN_HAS_MIPSEL;UNICORN_HAS_MIPS64;UNICORN_HAS_MIPS64EL;UNICORN_HAS_SPARC MultiThreadedDebug ../../..;../../../include;../../../qemu;../../../qemu/include;../../../qemu/tcg; @@ -382,8 +382,9 @@ MaxSpeed true true - WIN32;NDEBUG;_LIB;%(PreprocessorDefinitions);_CRT_SECURE_NO_WARNINGS;;inline=__inline;__func__=__FUNCTION__ + WIN32;NDEBUG;_LIB;%(PreprocessorDefinitions);_CRT_SECURE_NO_WARNINGS;;inline=__inline;__func__=__FUNCTION__;UNICORN_HAS_X86;UNICORN_HAS_ARM;UNICORN_HAS_M68K;UNICORN_HAS_ARM64;UNICORN_HAS_MIPS;UNICORN_HAS_MIPSEL;UNICORN_HAS_MIPS64;UNICORN_HAS_MIPS64EL;UNICORN_HAS_SPARC MultiThreadedDebug + ../../..;../../../include;../../../qemu;../../../qemu/include;../../../qemu/tcg; Windows diff --git a/include/list.h b/include/list.h index 75ec13e2..9731ca3a 100644 --- a/include/list.h +++ b/include/list.h @@ -1,7 +1,7 @@ #ifndef UC_LLIST_H #define UC_LLIST_H -#include +#include "platform.h" struct list_item { struct list_item *next; diff --git a/include/platform.h b/include/platform.h index 36a0dcfe..2ba818c7 100644 --- a/include/platform.h +++ b/include/platform.h @@ -238,6 +238,7 @@ static void usleep(const int64_t &t) { // misc support #if defined(_MSC_VER) +#define va_copy(d,s) ((d) = (s)) #define snprintf _snprintf #define strcasecmp _stricmp #if (_MSC_VER <= MSC_VER_VS2013) @@ -247,4 +248,5 @@ static void usleep(const int64_t &t) { + #endif // UNICORN_PLATFORM_H diff --git a/include/uc_priv.h b/include/uc_priv.h index dd4a211b..93eb3eda 100644 --- a/include/uc_priv.h +++ b/include/uc_priv.h @@ -4,7 +4,7 @@ #ifndef UC_PRIV_H #define UC_PRIV_H -#include +#include "platform.h" #include #include "qemu.h" @@ -110,9 +110,11 @@ enum uc_hook_idx { UC_HOOK_MAX, }; +#define HOOK_FOREACH_VAR_DECLARE \ + struct list_item *cur + // for loop macro to loop over hook lists #define HOOK_FOREACH(uc, hh, idx) \ - struct list_item *cur; \ for ( \ cur = (uc)->hook[idx##_IDX].head; \ cur != NULL && ((hh) = (struct hook *)cur->data) \ diff --git a/include/unicorn/m68k.h b/include/unicorn/m68k.h index 201a4e78..a2a02fab 100644 --- a/include/unicorn/m68k.h +++ b/include/unicorn/m68k.h @@ -8,7 +8,7 @@ extern "C" { #endif -#include +#include "platform.h" #ifdef _MSC_VER #pragma warning(disable:4201) diff --git a/include/unicorn/sparc.h b/include/unicorn/sparc.h index 57a483b7..7be29ab5 100644 --- a/include/unicorn/sparc.h +++ b/include/unicorn/sparc.h @@ -8,7 +8,7 @@ extern "C" { #endif -#include +#include "platform.h" // GCC SPARC toolchain has a default macro called "sparc" which breaks // compilation diff --git a/include/unicorn/unicorn.h b/include/unicorn/unicorn.h index 61d16568..885716d0 100644 --- a/include/unicorn/unicorn.h +++ b/include/unicorn/unicorn.h @@ -8,16 +8,7 @@ extern "C" { #endif -#include -#ifdef _MSC_VER -#ifndef __cplusplus -typedef unsigned char bool; -#define false 0 -#define true 1 -#endif -#else -#include -#endif +#include "platform.h" #include #if defined(UNICORN_HAS_OSXKERNEL) #include @@ -38,6 +29,12 @@ typedef size_t uc_hook; #include "mips.h" #include "sparc.h" +#ifdef __GNUC__ +#define DEFAULT_VISIBILITY __attribute__((visibility("default"))) +#else +#define DEFAULT_VISIBILITY +#endif + #ifdef _MSC_VER #pragma warning(disable:4201) #pragma warning(disable:4100) diff --git a/include/unicorn/x86.h b/include/unicorn/x86.h index b0e02d8d..e4c6fd43 100644 --- a/include/unicorn/x86.h +++ b/include/unicorn/x86.h @@ -8,7 +8,7 @@ extern "C" { #endif -#include +#include "platform.h" // Memory-Management Register for instructions IDTR, GDTR, LDTR, TR. // Borrow from SegmentCache in qemu/target-i386/cpu.h diff --git a/list.c b/list.c index b1627f59..c58cf163 100644 --- a/list.c +++ b/list.c @@ -1,5 +1,5 @@ #include -#include +#include "platform.h" #include "list.h" // simple linked list implementation diff --git a/qemu/accel.c b/qemu/accel.c index 3de5416c..a2172657 100644 --- a/qemu/accel.c +++ b/qemu/accel.c @@ -48,18 +48,25 @@ static int tcg_init(MachineState *ms) } static const TypeInfo accel_type = { - .name = TYPE_ACCEL, - .parent = TYPE_OBJECT, - .class_size = sizeof(AccelClass), - .instance_size = sizeof(AccelState), + TYPE_ACCEL, + TYPE_OBJECT, + sizeof(AccelClass), + sizeof(AccelState), }; #define TYPE_TCG_ACCEL ACCEL_CLASS_NAME("tcg") static const TypeInfo tcg_accel_type = { - .name = TYPE_TCG_ACCEL, - .parent = TYPE_ACCEL, - .class_init = tcg_accel_class_init, + TYPE_TCG_ACCEL, + TYPE_ACCEL, + 0, + 0, + NULL, + NULL, + NULL, + NULL, + NULL, + tcg_accel_class_init, }; diff --git a/qemu/cpu-exec.c b/qemu/cpu-exec.c index 61b11f30..ba07c350 100644 --- a/qemu/cpu-exec.c +++ b/qemu/cpu-exec.c @@ -132,6 +132,7 @@ int cpu_exec(struct uc_struct *uc, CPUArchState *env) // qq #else bool catched = false; // Unicorn: call registered interrupt callbacks + HOOK_FOREACH_VAR_DECLARE; HOOK_FOREACH(uc, hook, UC_HOOK_INTR) { ((uc_cb_hookintr_t)hook->callback)(uc, cpu->exception_index, hook->user_data); catched = true; @@ -376,7 +377,7 @@ static TranslationBlock *tb_find_slow(CPUArchState *env, target_ulong pc, } not_found: /* if no translated code available, then translate it now */ - tb = tb_gen_code(cpu, pc, cs_base, flags, 0); // qq + tb = tb_gen_code(cpu, pc, cs_base, (int)flags, 0); // qq found: /* Move the last found TB to the head of the list */ diff --git a/qemu/cputlb.c b/qemu/cputlb.c index eb0b2c53..87f14f75 100644 --- a/qemu/cputlb.c +++ b/qemu/cputlb.c @@ -235,7 +235,7 @@ void tlb_set_page(CPUState *cpu, target_ulong vaddr, addend = 0; } else { /* TLB_MMIO for rom/romd handled below */ - addend = (uintptr_t)memory_region_get_ram_ptr(section->mr) + xlat; + addend = (uintptr_t)((char*)memory_region_get_ram_ptr(section->mr) + xlat); } code_address = address; @@ -251,7 +251,7 @@ void tlb_set_page(CPUState *cpu, target_ulong vaddr, /* refill the tlb */ env->iotlb[mmu_idx][index] = iotlb - vaddr; - te->addend = addend - vaddr; + te->addend = (uintptr_t)(addend - vaddr); if (prot & PAGE_READ) { te->addr_read = address; } else { @@ -269,8 +269,8 @@ void tlb_set_page(CPUState *cpu, target_ulong vaddr, /* Write access calls the I/O callback. */ te->addr_write = address | TLB_MMIO; } else if (memory_region_is_ram(section->mr) - && cpu_physical_memory_is_clean(cpu->uc, section->mr->ram_addr - + xlat)) { + && cpu_physical_memory_is_clean(cpu->uc, (ram_addr_t)(section->mr->ram_addr + + xlat))) { te->addr_write = address | TLB_NOTDIRTY; } else { te->addr_write = address; diff --git a/qemu/exec.c b/qemu/exec.c index 92f26641..bb4b3ba0 100644 --- a/qemu/exec.c +++ b/qemu/exec.c @@ -247,9 +247,11 @@ static void phys_page_compact(PhysPageEntry *lp, Node *nodes, unsigned long *com } } -static void phys_page_compact_all(AddressSpaceDispatch *d, int nodes_nb) +static void phys_page_compact_all(AddressSpaceDispatch *d, const int nodes_nb) { - DECLARE_BITMAP(compacted, nodes_nb); + //DECLARE_BITMAP(compacted, nodes_nb); + // this isnt actually used + unsigned int* compacted = NULL; if (d->phys_map.skip) { phys_page_compact(&d->phys_map, d->map.nodes, compacted); @@ -634,10 +636,11 @@ void cpu_single_step(CPUState *cpu, int enabled) { #if defined(TARGET_HAS_ICE) if (cpu->singlestep_enabled != enabled) { + CPUArchState *env; cpu->singlestep_enabled = enabled; /* must flush all the translated code to avoid inconsistencies */ /* XXX: only flush what is necessary */ - CPUArchState *env = cpu->env_ptr; + env = cpu->env_ptr; tb_flush(env); } #endif @@ -836,11 +839,8 @@ static void register_subpage(struct uc_struct* uc, & TARGET_PAGE_MASK; MemoryRegionSection *existing = phys_page_find(d->phys_map, base, d->map.nodes, d->map.sections); - MemoryRegionSection subsection = { - .offset_within_address_space = base, - .size = int128_make64(TARGET_PAGE_SIZE), - }; hwaddr start, end; + MemoryRegionSection subsection = MemoryRegionSection_make(NULL, NULL, 0, int128_make64(TARGET_PAGE_SIZE), base, false); assert(existing->mr->subpage || existing->mr == &uc->io_mem_unassigned); @@ -1227,10 +1227,10 @@ void *qemu_get_ram_ptr(struct uc_struct *uc, ram_addr_t addr) * but takes a size argument */ static void *qemu_ram_ptr_length(struct uc_struct *uc, ram_addr_t addr, hwaddr *size) { + RAMBlock *block; if (*size == 0) { return NULL; } - RAMBlock *block; QTAILQ_FOREACH(block, &uc->ram_list.blocks, next) { if (addr - block->offset < block->length) { @@ -1337,10 +1337,12 @@ static bool subpage_accepts(void *opaque, hwaddr addr, } static const MemoryRegionOps subpage_ops = { - .read = subpage_read, - .write = subpage_write, - .valid.accepts = subpage_accepts, - .endianness = DEVICE_NATIVE_ENDIAN, + subpage_read, + subpage_write, + DEVICE_NATIVE_ENDIAN, + { + 0, 0, false, subpage_accepts, + }, }; static int subpage_register (subpage_t *mmio, uint32_t start, uint32_t end, @@ -1398,9 +1400,12 @@ static bool notdirty_mem_accepts(void *opaque, hwaddr addr, } static const MemoryRegionOps notdirty_mem_ops = { - .write = notdirty_mem_write, - .valid.accepts = notdirty_mem_accepts, - .endianness = DEVICE_NATIVE_ENDIAN, + NULL, + notdirty_mem_write, + DEVICE_NATIVE_ENDIAN, + { + 0, 0, false, notdirty_mem_accepts, + }, }; static void io_mem_init(struct uc_struct* uc) @@ -1437,14 +1442,14 @@ static subpage_t *subpage_init(AddressSpace *as, hwaddr base) static uint16_t dummy_section(PhysPageMap *map, AddressSpace *as, MemoryRegion *mr) { - assert(as); - MemoryRegionSection section = { - .address_space = as, - .mr = mr, - .offset_within_address_space = 0, - .offset_within_region = 0, - .size = int128_2_64(), - }; + MemoryRegionSection section = MemoryRegionSection_make( + mr, as, 0, + int128_2_64(), + false, + 0 + ); + + assert(as); return phys_section_add(map, §ion); } @@ -1465,7 +1470,7 @@ static void mem_begin(MemoryListener *listener) AddressSpace *as = container_of(listener, AddressSpace, dispatch_listener); AddressSpaceDispatch *d = g_new0(AddressSpaceDispatch, 1); uint16_t n; - + PhysPageEntry ppe = { 1, PHYS_MAP_NODE_NIL }; struct uc_struct *uc = as->uc; n = dummy_section(&d->map, as, &uc->io_mem_unassigned); @@ -1477,7 +1482,7 @@ static void mem_begin(MemoryListener *listener) // n = dummy_section(&d->map, as, &uc->io_mem_watch); // assert(n == PHYS_SECTION_WATCH); - d->phys_map = (PhysPageEntry) { .ptr = PHYS_MAP_NODE_NIL, .skip = 1 }; + d->phys_map = ppe; d->as = as; as->next_dispatch = d; } @@ -1510,14 +1515,17 @@ static void tcg_commit(MemoryListener *listener) void address_space_init_dispatch(AddressSpace *as) { - as->dispatch = NULL; - as->dispatch_listener = (MemoryListener) { - .begin = mem_begin, - .commit = mem_commit, - .region_add = mem_add, - .region_nop = mem_add, - .priority = 0, + MemoryListener ml = { + mem_begin, + mem_commit, + mem_add, + NULL, + mem_add, + NULL,NULL,NULL,NULL,NULL,NULL,NULL,NULL,NULL, + 0, }; + as->dispatch = NULL; + as->dispatch_listener = ml; memory_listener_register(as->uc, &as->dispatch_listener, as); } @@ -1632,7 +1640,7 @@ static int memory_access_size(MemoryRegion *mr, unsigned l, hwaddr addr) /* Bound the maximum access by the alignment of the address. */ if (!mr->ops->impl.unaligned) { - unsigned align_size_max = addr & -addr; + unsigned align_size_max = addr & (0-addr); if (align_size_max != 0 && align_size_max < access_size_max) { access_size_max = align_size_max; } @@ -1804,7 +1812,7 @@ static inline void cpu_physical_memory_write_rom_internal(AddressSpace *as, } /* used for ROM loading : can write in RAM and ROM */ -__attribute__ ((visibility ("default"))) +DEFAULT_VISIBILITY void cpu_physical_memory_write_rom(AddressSpace *as, hwaddr addr, const uint8_t *buf, int len) { @@ -1953,7 +1961,7 @@ void *cpu_physical_memory_map(AddressSpace *as, hwaddr addr, void cpu_physical_memory_unmap(AddressSpace *as, void *buffer, hwaddr len, int is_write, hwaddr access_len) { - return address_space_unmap(as, buffer, len, is_write, access_len); + address_space_unmap(as, buffer, len, is_write, access_len); } /* warning: addr must be aligned */ diff --git a/qemu/fpu/softfloat-macros.h b/qemu/fpu/softfloat-macros.h index 0dcda93f..2e3c967d 100644 --- a/qemu/fpu/softfloat-macros.h +++ b/qemu/fpu/softfloat-macros.h @@ -467,9 +467,9 @@ static inline void mul64To128( uint64_t a, uint64_t b, uint64_t *z0Ptr, uint64_t uint32_t aHigh, aLow, bHigh, bLow; uint64_t z0, zMiddleA, zMiddleB, z1; - aLow = a; + aLow = (uint32_t)a; aHigh = a>>32; - bLow = b; + bLow = (uint32_t)b; bHigh = b>>32; z1 = ( (uint64_t) aLow ) * bLow; zMiddleA = ( (uint64_t) aLow ) * bHigh; @@ -691,7 +691,7 @@ static int8 countLeadingZeros64( uint64_t a ) else { a >>= 32; } - shiftCount += countLeadingZeros32( a ); + shiftCount += countLeadingZeros32( (uint32_t)a ); return shiftCount; #endif } diff --git a/qemu/fpu/softfloat.c b/qemu/fpu/softfloat.c index 81c8f3d6..f12ec3e9 100644 --- a/qemu/fpu/softfloat.c +++ b/qemu/fpu/softfloat.c @@ -129,7 +129,7 @@ static int32 roundAndPackInt32( flag zSign, uint64_t absZ STATUS_PARAM) roundBits = absZ & 0x7F; absZ = ( absZ + roundIncrement )>>7; absZ &= ~ ( ( ( roundBits ^ 0x40 ) == 0 ) & roundNearestEven ); - z = absZ; + z = (int32_t)absZ; if ( zSign ) z = - z; if ( ( absZ>>32 ) || ( z && ( ( z < 0 ) ^ zSign ) ) ) { float_raise( float_flag_invalid STATUS_VAR); @@ -786,7 +786,7 @@ static floatx80 } if ( roundBits ) STATUS(float_exception_flags) |= float_flag_inexact; zSig0 += roundIncrement; - if ( zSig0 < roundIncrement ) { + if ( zSig0 < (uint64_t)roundIncrement ) { ++zExp; zSig0 = LIT64( 0x8000000000000000 ); } @@ -1289,7 +1289,7 @@ float32 int64_to_float32(int64_t a STATUS_PARAM) absA = zSign ? - a : a; shiftCount = countLeadingZeros64( absA ) - 40; if ( 0 <= shiftCount ) { - return packFloat32( zSign, 0x95 - shiftCount, absA<>( 64 - expDiff ); + q = (uint32_t)(q64>>( 64 - expDiff )); bSig <<= 6; aSig = ( ( aSig64>>33 )<<( expDiff - 1 ) ) - bSig * q; } @@ -2285,7 +2287,7 @@ float32 float32_rem( float32 a, float32 b STATUS_PARAM ) aSig = alternateASig; } zSign = ( (int32_t) aSig < 0 ); - if ( zSign ) aSig = - aSig; + if ( zSign ) aSig = 0- aSig; return normalizeRoundAndPackFloat32( aSign ^ zSign, bExp, aSig STATUS_VAR ); } @@ -2438,7 +2440,7 @@ float32 float32_muladd(float32 a, float32 b, float32 c, int flags STATUS_PARAM) if (!cSig) { /* Throw out the special case of c being an exact zero now */ shift64RightJamming(pSig64, 32, &pSig64); - pSig = pSig64; + pSig = (uint32_t)pSig64; if (flags & float_muladd_halve_result) { pExp--; } @@ -2511,7 +2513,7 @@ float32 float32_muladd(float32 a, float32 b, float32 c, int flags STATUS_PARAM) } shift64RightJamming(zSig64, 32, &zSig64); - return roundAndPackFloat32(zSign, zExp, zSig64 STATUS_VAR); + return roundAndPackFloat32(zSign, zExp, (uint32_t)zSig64 STATUS_VAR); } @@ -2693,7 +2695,7 @@ float32 float32_log2( float32 a STATUS_PARAM ) } if ( zSign ) - zSig = -zSig; + zSig = 0-zSig; return normalizeRoundAndPackFloat32( zSign, 0x85, zSig STATUS_VAR ); } @@ -2971,7 +2973,7 @@ int32 float64_to_int32_round_to_zero( float64 a STATUS_PARAM ) shiftCount = 0x433 - aExp; savedASig = aSig; aSig >>= shiftCount; - z = aSig; + z = (int32_t)aSig; if ( aSign ) z = - z; if ( ( z < 0 ) ^ aSign ) { invalid: @@ -3021,7 +3023,7 @@ int_fast16_t float64_to_int16_round_to_zero(float64 a STATUS_PARAM) shiftCount = 0x433 - aExp; savedASig = aSig; aSig >>= shiftCount; - z = aSig; + z = (int32)aSig; if ( aSign ) { z = - z; } @@ -3155,7 +3157,7 @@ float32 float64_to_float32( float64 a STATUS_PARAM ) return packFloat32( aSign, 0xFF, 0 ); } shift64RightJamming( aSig, 22, &aSig ); - zSig = aSig; + zSig = (uint32_t)aSig; if ( aExp || zSig ) { zSig |= 0x40000000; aExp -= 0x381; @@ -3435,7 +3437,7 @@ float16 float64_to_float16(float64 a, flag ieee STATUS_PARAM) return packFloat16(aSign, 0x1f, 0); } shift64RightJamming(aSig, 29, &aSig); - zSig = aSig; + zSig = (uint32_t)aSig; if (aExp == 0 && zSig == 0) { return packFloat16(aSign, 0, 0); } @@ -3995,7 +3997,7 @@ float64 float64_rem( float64 a, float64 b STATUS_PARAM ) while ( 0 < expDiff ) { q = estimateDiv128To64( aSig, 0, bSig ); q = ( 2 < q ) ? q - 2 : 0; - aSig = - ( ( bSig>>2 ) * q ); + aSig = 0- ( ( bSig>>2 ) * q ); expDiff -= 62; } expDiff += 64; @@ -4020,7 +4022,7 @@ float64 float64_rem( float64 a, float64 b STATUS_PARAM ) aSig = alternateASig; } zSign = ( (int64_t) aSig < 0 ); - if ( zSign ) aSig = - aSig; + if ( zSign ) aSig = 0- aSig; return normalizeRoundAndPackFloat64( aSign ^ zSign, bExp, aSig STATUS_VAR ); } @@ -4305,7 +4307,7 @@ float64 float64_sqrt( float64 a STATUS_PARAM ) } zExp = ( ( aExp - 0x3FF )>>1 ) + 0x3FE; aSig |= LIT64( 0x0010000000000000 ); - zSig = estimateSqrt32( aExp, aSig>>21 ); + zSig = estimateSqrt32( aExp, (uint32_t)(aSig>>21) ); aSig <<= 9 - ( aExp & 1 ); zSig = estimateDiv128To64( aSig, 0, zSig<<32 ) + ( zSig<<30 ); if ( ( zSig & 0x1FF ) <= 5 ) { @@ -4366,7 +4368,7 @@ float64 float64_log2( float64 a STATUS_PARAM ) } if ( zSign ) - zSig = -zSig; + zSig = 0-zSig; return normalizeRoundAndPackFloat64( zSign, 0x408, zSig STATUS_VAR ); } @@ -4652,7 +4654,7 @@ int32 floatx80_to_int32_round_to_zero( floatx80 a STATUS_PARAM ) shiftCount = 0x403E - aExp; savedASig = aSig; aSig >>= shiftCount; - z = aSig; + z = (int32_t)aSig; if ( aSign ) z = - z; if ( ( z < 0 ) ^ aSign ) { invalid: @@ -4786,7 +4788,7 @@ float32 floatx80_to_float32( floatx80 a STATUS_PARAM ) } shift64RightJamming( aSig, 33, &aSig ); if ( aExp || aSig ) aExp -= 0x3F81; - return roundAndPackFloat32( aSign, aExp, aSig STATUS_VAR ); + return roundAndPackFloat32( aSign, aExp, (uint32_t)aSig STATUS_VAR ); } @@ -5771,7 +5773,7 @@ int32 float128_to_int32_round_to_zero( float128 a STATUS_PARAM ) shiftCount = 0x402F - aExp; savedASig = aSig0; aSig0 >>= shiftCount; - z = aSig0; + z = (int32_t)aSig0; if ( aSign ) z = - z; if ( ( z < 0 ) ^ aSign ) { invalid: @@ -5915,7 +5917,7 @@ float32 float128_to_float32( float128 a STATUS_PARAM ) } aSig0 |= ( aSig1 != 0 ); shift64RightJamming( aSig0, 18, &aSig0 ); - zSig = aSig0; + zSig = (uint32_t)aSig0; if ( aExp || zSig ) { zSig |= 0x40000000; aExp -= 0x3F81; @@ -6636,7 +6638,7 @@ float128 float128_sqrt( float128 a STATUS_PARAM ) } zExp = ( ( aExp - 0x3FFF )>>1 ) + 0x3FFE; aSig0 |= LIT64( 0x0001000000000000 ); - zSig0 = estimateSqrt32( aExp, aSig0>>17 ); + zSig0 = estimateSqrt32( aExp, (uint32_t)(aSig0>>17) ); shortShift128Left( aSig0, aSig1, 13 - ( aExp & 1 ), &aSig0, &aSig1 ); zSig0 = estimateDiv128To64( aSig0, aSig1, zSig0<<32 ) + ( zSig0<<30 ); doubleZSig0 = zSig0<<1; @@ -6929,7 +6931,7 @@ uint32 float32_to_uint32( float32 a STATUS_PARAM ) } else if (v > 0xffffffff) { res = 0xffffffff; } else { - return v; + return (uint32)v; } set_float_exception_flags(old_exc_flags STATUS_VAR); float_raise(float_flag_invalid STATUS_VAR); @@ -6948,7 +6950,7 @@ uint32 float32_to_uint32_round_to_zero( float32 a STATUS_PARAM ) } else if (v > 0xffffffff) { res = 0xffffffff; } else { - return v; + return (uint32)v; } set_float_exception_flags(old_exc_flags, status); float_raise(float_flag_invalid STATUS_VAR); @@ -7007,7 +7009,7 @@ uint_fast16_t float32_to_uint16_round_to_zero(float32 a STATUS_PARAM) } else if (v > 0xffff) { res = 0xffff; } else { - return v; + return (uint_fast16_t)v; } set_float_exception_flags(old_exc_flags, status); float_raise(float_flag_invalid STATUS_VAR); @@ -7024,7 +7026,7 @@ uint32 float64_to_uint32( float64 a STATUS_PARAM ) if (v > 0xffffffff) { res = 0xffffffff; } else { - return v; + return (uint32)v; } set_float_exception_flags(old_exc_flags, status); float_raise(float_flag_invalid STATUS_VAR); @@ -7041,7 +7043,7 @@ uint32 float64_to_uint32_round_to_zero( float64 a STATUS_PARAM ) if (v > 0xffffffff) { res = 0xffffffff; } else { - return v; + return (uint32)v; } set_float_exception_flags(old_exc_flags, status); float_raise(float_flag_invalid STATUS_VAR); @@ -7060,7 +7062,7 @@ int_fast16_t float64_to_int16(float64 a STATUS_PARAM) } else if (v > 0x7fff) { res = 0x7fff; } else { - return v; + return (int_fast16_t)v; } set_float_exception_flags(old_exc_flags, status); @@ -7080,7 +7082,7 @@ uint_fast16_t float64_to_uint16(float64 a STATUS_PARAM) } else if (v > 0xffff) { res = 0xffff; } else { - return v; + return (uint_fast16_t)v; } set_float_exception_flags(old_exc_flags, status); @@ -7100,7 +7102,7 @@ uint_fast16_t float64_to_uint16_round_to_zero(float64 a STATUS_PARAM) } else if (v > 0xffff) { res = 0xffff; } else { - return v; + return (uint_fast16_t)v; } set_float_exception_flags(old_exc_flags, status); float_raise(float_flag_invalid STATUS_VAR); @@ -7156,9 +7158,10 @@ uint64_t float64_to_uint64(float64 a STATUS_PARAM) uint64_t float64_to_uint64_round_to_zero (float64 a STATUS_PARAM) { - signed char current_rounding_mode = STATUS(float_rounding_mode); + int64_t v; + signed char current_rounding_mode = STATUS(float_rounding_mode); set_float_rounding_mode(float_round_to_zero STATUS_VAR); - int64_t v = float64_to_uint64(a STATUS_VAR); + v = float64_to_uint64(a STATUS_VAR); set_float_rounding_mode(current_rounding_mode STATUS_VAR); return v; } diff --git a/qemu/glib_compat.c b/qemu/glib_compat.c index d800ea25..4da0765b 100644 --- a/qemu/glib_compat.c +++ b/qemu/glib_compat.c @@ -1217,16 +1217,18 @@ void g_free(gpointer ptr) gpointer g_malloc(size_t size) { - if (size == 0) return NULL; - void *res = malloc(size); + void *res; + if (size == 0) return NULL; + res = malloc(size); if (res == NULL) exit(1); return res; } gpointer g_malloc0(size_t size) { + void *res; if (size == 0) return NULL; - void *res = calloc(size, 1); + res = calloc(size, 1); if (res == NULL) exit(1); return res; } @@ -1239,18 +1241,23 @@ gpointer g_try_malloc0(size_t size) gpointer g_realloc(gpointer ptr, size_t size) { + void *res; if (size == 0) { free(ptr); return NULL; } - void *res = realloc(ptr, size); + res = realloc(ptr, size); if (res == NULL) exit(1); return res; } char *g_strdup(const char *str) { - return str ? strdup(str) : NULL; +#ifdef _MSC_VER + return str ? _strdup(str) : NULL; +#else + return str ? strdup(str) : NULL; +#endif } char *g_strdup_printf(const char *format, ...) @@ -1266,7 +1273,17 @@ char *g_strdup_printf(const char *format, ...) char *g_strdup_vprintf(const char *format, va_list ap) { char *str_res = NULL; +#ifdef _MSC_VER + int len = _vscprintf(format, ap); + if( len < 0 ) + return NULL; + str_res = (char *)malloc(len+1); + if(str_res==NULL) + return NULL; + vsnprintf(str_res, len+1, format, ap); +#else vasprintf(&str_res, format, ap); +#endif return str_res; } diff --git a/qemu/hw/i386/pc.c b/qemu/hw/i386/pc.c index d3aded6d..e245703b 100644 --- a/qemu/hw/i386/pc.c +++ b/qemu/hw/i386/pc.c @@ -149,16 +149,30 @@ static void pc_machine_class_init(struct uc_struct *uc, ObjectClass *oc, void *d } static const TypeInfo pc_machine_info = { - .name = TYPE_PC_MACHINE, - .parent = TYPE_MACHINE, - .abstract = true, - .instance_size = sizeof(PCMachineState), - .instance_init = pc_machine_initfn, - .class_size = sizeof(PCMachineClass), - .class_init = pc_machine_class_init, - .interfaces = (InterfaceInfo[]) { - { } - }, + TYPE_PC_MACHINE, + TYPE_MACHINE, + + sizeof(PCMachineClass), + sizeof(PCMachineState), + NULL, + + pc_machine_initfn, + NULL, + NULL, + + NULL, + + pc_machine_class_init, + NULL, + NULL, + + true, + + NULL, + NULL, + + // should this be added somehow? + //.interfaces = (InterfaceInfo[]) { { } }, }; void pc_machine_register_types(struct uc_struct *uc) diff --git a/qemu/hw/i386/pc_piix.c b/qemu/hw/i386/pc_piix.c index b9759621..43ec6962 100644 --- a/qemu/hw/i386/pc_piix.c +++ b/qemu/hw/i386/pc_piix.c @@ -46,19 +46,14 @@ static int pc_init_pci(struct uc_struct *uc, MachineState *machine) return pc_init1(uc, machine); } -#define PC_I440FX_MACHINE_OPTIONS \ - PC_DEFAULT_MACHINE_OPTIONS, \ - .family = "pc_piix" - -#define PC_I440FX_2_2_MACHINE_OPTIONS \ - PC_I440FX_MACHINE_OPTIONS - static QEMUMachine pc_i440fx_machine_v2_2 = { - PC_I440FX_2_2_MACHINE_OPTIONS, - .name = "pc-i440fx-2.2", - .init = pc_init_pci, - .is_default = 1, - .arch = UC_ARCH_X86, // X86 + "pc_piix", + "pc-i440fx-2.2", + pc_init_pci, + NULL, + 255, + 1, + UC_ARCH_X86, // X86 }; static void pc_generic_machine_class_init(struct uc_struct *uc, ObjectClass *oc, void *data) diff --git a/qemu/hw/intc/apic.c b/qemu/hw/intc/apic.c index 1f89770e..ed5d035f 100644 --- a/qemu/hw/intc/apic.c +++ b/qemu/hw/intc/apic.c @@ -205,10 +205,20 @@ static void apic_class_init(struct uc_struct *uc, ObjectClass *klass, void *data } static const TypeInfo apic_info = { - .name = "apic", - .instance_size = sizeof(APICCommonState), - .parent = TYPE_APIC_COMMON, - .class_init = apic_class_init, + "apic", + TYPE_APIC_COMMON, + + 0, + sizeof(APICCommonState), + NULL, + + NULL, + NULL, + NULL, + + NULL, + + apic_class_init, }; void apic_register_types(struct uc_struct *uc) diff --git a/qemu/hw/intc/apic_common.c b/qemu/hw/intc/apic_common.c index c5d32e39..7055fe53 100644 --- a/qemu/hw/intc/apic_common.c +++ b/qemu/hw/intc/apic_common.c @@ -163,11 +163,13 @@ void apic_init_reset(struct uc_struct *uc, DeviceState *dev) void apic_designate_bsp(struct uc_struct *uc, DeviceState *dev) { - if (dev == NULL) { + APICCommonState *s; + + if (dev == NULL) { return; } - APICCommonState *s = APIC_COMMON(uc, dev); + s = APIC_COMMON(uc, dev); s->apicbase |= MSR_IA32_APICBASE_BSP; } @@ -245,12 +247,24 @@ static void apic_common_class_init(struct uc_struct *uc, ObjectClass *klass, voi } static const TypeInfo apic_common_type = { - .name = TYPE_APIC_COMMON, - .parent = TYPE_DEVICE, - .instance_size = sizeof(APICCommonState), - .class_size = sizeof(APICCommonClass), - .class_init = apic_common_class_init, - .abstract = true, + TYPE_APIC_COMMON, + TYPE_DEVICE, + + sizeof(APICCommonClass), + sizeof(APICCommonState), + NULL, + + NULL, + NULL, + NULL, + + NULL, + + apic_common_class_init, + NULL, + NULL, + + true, }; void apic_common_register_types(struct uc_struct *uc) diff --git a/qemu/include/elf.h b/qemu/include/elf.h index a5165844..d9d6ebe6 100644 --- a/qemu/include/elf.h +++ b/qemu/include/elf.h @@ -1,7 +1,7 @@ #ifndef _QEMU_ELF_H #define _QEMU_ELF_H -#include +#include "platform.h" /* 32-bit ELF base types. */ typedef uint32_t Elf32_Addr; diff --git a/qemu/include/exec/cpu-defs.h b/qemu/include/exec/cpu-defs.h index 914246fe..5b456add 100644 --- a/qemu/include/exec/cpu-defs.h +++ b/qemu/include/exec/cpu-defs.h @@ -24,7 +24,7 @@ #endif #include "config.h" -#include +#include "platform.h" #include "qemu/osdep.h" #include "qemu/queue.h" #ifndef CONFIG_USER_ONLY @@ -96,7 +96,7 @@ typedef struct CPUTLBEntry { /* padding to get a power of two size */ uint8_t dummy[(1 << CPU_TLB_ENTRY_BITS) - (sizeof(target_ulong) * 3 + - ((-sizeof(target_ulong) * 3) & (sizeof(uintptr_t) - 1)) + + (((-(int)sizeof(target_ulong)) * 3) & (sizeof(uintptr_t) - 1)) + sizeof(uintptr_t))]; } CPUTLBEntry; diff --git a/qemu/include/exec/cpu_ldst.h b/qemu/include/exec/cpu_ldst.h index e5550e71..715cee51 100644 --- a/qemu/include/exec/cpu_ldst.h +++ b/qemu/include/exec/cpu_ldst.h @@ -391,7 +391,7 @@ static inline void *tlb_vaddr_to_host(CPUArchState *env, target_ulong addr, return NULL; } - haddr = addr + env->tlb_table[mmu_idx][index].addend; + haddr = (uintptr_t)(addr + env->tlb_table[mmu_idx][index].addend); return (void *)haddr; } diff --git a/qemu/include/exec/cpu_ldst_template.h b/qemu/include/exec/cpu_ldst_template.h index 006093ac..fc68ee31 100644 --- a/qemu/include/exec/cpu_ldst_template.h +++ b/qemu/include/exec/cpu_ldst_template.h @@ -78,7 +78,7 @@ glue(glue(cpu_ld, USUFFIX), MEMSUFFIX)(CPUArchState *env, target_ulong ptr) (addr & (TARGET_PAGE_MASK | (DATA_SIZE - 1))))) { res = glue(glue(helper_ld, SUFFIX), MMUSUFFIX)(env, addr, mmu_idx); } else { - uintptr_t hostaddr = addr + env->tlb_table[mmu_idx][page_index].addend; + uintptr_t hostaddr = (uintptr_t)(addr + env->tlb_table[mmu_idx][page_index].addend); res = glue(glue(ld, USUFFIX), _raw)(hostaddr); } return res; @@ -100,7 +100,7 @@ glue(glue(cpu_lds, SUFFIX), MEMSUFFIX)(CPUArchState *env, target_ulong ptr) res = (DATA_STYPE)glue(glue(helper_ld, SUFFIX), MMUSUFFIX)(env, addr, mmu_idx); } else { - uintptr_t hostaddr = addr + env->tlb_table[mmu_idx][page_index].addend; + uintptr_t hostaddr = (uintptr_t)(addr + env->tlb_table[mmu_idx][page_index].addend); res = glue(glue(lds, SUFFIX), _raw)(hostaddr); } return res; @@ -126,7 +126,7 @@ glue(glue(cpu_st, SUFFIX), MEMSUFFIX)(CPUArchState *env, target_ulong ptr, (addr & (TARGET_PAGE_MASK | (DATA_SIZE - 1))))) { glue(glue(helper_st, SUFFIX), MMUSUFFIX)(env, addr, v, mmu_idx); } else { - uintptr_t hostaddr = addr + env->tlb_table[mmu_idx][page_index].addend; + uintptr_t hostaddr = (uintptr_t)(addr + env->tlb_table[mmu_idx][page_index].addend); glue(glue(st, SUFFIX), _raw)(hostaddr, v); } } diff --git a/qemu/include/exec/exec-all.h b/qemu/include/exec/exec-all.h index cdf888f4..79f8df34 100644 --- a/qemu/include/exec/exec-all.h +++ b/qemu/include/exec/exec-all.h @@ -277,7 +277,7 @@ static inline void tb_set_jmp_target(TranslationBlock *tb, int n, uintptr_t addr) { uint16_t offset = tb->tb_jmp_offset[n]; - tb_set_jmp_target1((uintptr_t)(tb->tc_ptr + offset), addr); + tb_set_jmp_target1((uintptr_t)((char*)tb->tc_ptr + offset), addr); } #else @@ -310,6 +310,9 @@ static inline void tb_add_jump(TranslationBlock *tb, int n, #if defined(CONFIG_TCG_INTERPRETER) extern uintptr_t tci_tb_ptr; # define GETRA() tci_tb_ptr +#elif defined(_MSC_VER) +#include +# define GETRA() (uintptr_t)_ReturnAddress() #else # define GETRA() \ ((uintptr_t)__builtin_extract_return_addr(__builtin_return_address(0))) diff --git a/qemu/include/exec/helper-tcg.h b/qemu/include/exec/helper-tcg.h index d704c811..5b12f316 100644 --- a/qemu/include/exec/helper-tcg.h +++ b/qemu/include/exec/helper-tcg.h @@ -7,31 +7,31 @@ #include #define DEF_HELPER_FLAGS_0(NAME, FLAGS, ret) \ - { .func = HELPER(NAME), .name = #NAME, .flags = FLAGS, \ - .sizemask = dh_sizemask(ret, 0) }, + { HELPER(NAME), #NAME, FLAGS, \ + dh_sizemask(ret, 0) }, #define DEF_HELPER_FLAGS_1(NAME, FLAGS, ret, t1) \ - { .func = HELPER(NAME), .name = #NAME, .flags = FLAGS, \ - .sizemask = dh_sizemask(ret, 0) | dh_sizemask(t1, 1) }, + { HELPER(NAME), #NAME, FLAGS, \ + dh_sizemask(ret, 0) | dh_sizemask(t1, 1) }, #define DEF_HELPER_FLAGS_2(NAME, FLAGS, ret, t1, t2) \ - { .func = HELPER(NAME), .name = #NAME, .flags = FLAGS, \ - .sizemask = dh_sizemask(ret, 0) | dh_sizemask(t1, 1) \ + { HELPER(NAME), #NAME, FLAGS, \ + dh_sizemask(ret, 0) | dh_sizemask(t1, 1) \ | dh_sizemask(t2, 2) }, #define DEF_HELPER_FLAGS_3(NAME, FLAGS, ret, t1, t2, t3) \ - { .func = HELPER(NAME), .name = #NAME, .flags = FLAGS, \ - .sizemask = dh_sizemask(ret, 0) | dh_sizemask(t1, 1) \ + { HELPER(NAME), #NAME, FLAGS, \ + dh_sizemask(ret, 0) | dh_sizemask(t1, 1) \ | dh_sizemask(t2, 2) | dh_sizemask(t3, 3) }, #define DEF_HELPER_FLAGS_4(NAME, FLAGS, ret, t1, t2, t3, t4) \ - { .func = HELPER(NAME), .name = #NAME, .flags = FLAGS, \ - .sizemask = dh_sizemask(ret, 0) | dh_sizemask(t1, 1) \ + { HELPER(NAME), #NAME, FLAGS, \ + dh_sizemask(ret, 0) | dh_sizemask(t1, 1) \ | dh_sizemask(t2, 2) | dh_sizemask(t3, 3) | dh_sizemask(t4, 4) }, #define DEF_HELPER_FLAGS_5(NAME, FLAGS, ret, t1, t2, t3, t4, t5) \ - { .func = HELPER(NAME), .name = #NAME, .flags = FLAGS, \ - .sizemask = dh_sizemask(ret, 0) | dh_sizemask(t1, 1) \ + { HELPER(NAME), #NAME, FLAGS, \ + dh_sizemask(ret, 0) | dh_sizemask(t1, 1) \ | dh_sizemask(t2, 2) | dh_sizemask(t3, 3) | dh_sizemask(t4, 4) \ | dh_sizemask(t5, 5) }, diff --git a/qemu/include/exec/hwaddr.h b/qemu/include/exec/hwaddr.h index fb5306fc..0cfb0d24 100644 --- a/qemu/include/exec/hwaddr.h +++ b/qemu/include/exec/hwaddr.h @@ -7,7 +7,7 @@ /* hwaddr is the type of a physical address (its size can be different from 'target_ulong'). */ -#include +#include "platform.h" typedef uint64_t hwaddr; #define HWADDR_MAX UINT64_MAX diff --git a/qemu/include/exec/memory.h b/qemu/include/exec/memory.h index 9dc25cf1..3b2452f9 100644 --- a/qemu/include/exec/memory.h +++ b/qemu/include/exec/memory.h @@ -21,8 +21,7 @@ #define DIRTY_MEMORY_MIGRATION 2 #define DIRTY_MEMORY_NUM 3 /* num of dirty bits */ -#include -#include +#include "platform.h" #include "qemu-common.h" #include "exec/cpu-common.h" #ifndef CONFIG_USER_ONLY @@ -243,6 +242,19 @@ struct MemoryRegionSection { bool readonly; }; +static inline MemoryRegionSection MemoryRegionSection_make(MemoryRegion *mr, AddressSpace *address_space, + hwaddr offset_within_region, Int128 size, hwaddr offset_within_address_space, bool readonly) +{ + MemoryRegionSection section; + section.mr = mr; + section.address_space = address_space; + section.offset_within_region = offset_within_region; + section.size = size; + section.offset_within_address_space = offset_within_address_space; + section.readonly = readonly; + return section; +} + /** * memory_region_init: Initialize a memory region * diff --git a/qemu/include/fpu/softfloat.h b/qemu/include/fpu/softfloat.h index 8dc81c2f..982c4e06 100644 --- a/qemu/include/fpu/softfloat.h +++ b/qemu/include/fpu/softfloat.h @@ -42,7 +42,7 @@ these four paragraphs for those parts of this code that are retained. #include #endif -#include +#include "platform.h" #include "config-host.h" #include "qemu/osdep.h" @@ -125,7 +125,7 @@ typedef struct { uint16_t high; } floatx80; #define make_floatx80(exp, mant) ((floatx80) { mant, exp }) -#define make_floatx80_init(exp, mant) { .low = mant, .high = exp } +#define make_floatx80_init(exp, mant) { mant, exp } typedef struct { #ifdef HOST_WORDS_BIGENDIAN uint64_t high, low; @@ -133,8 +133,13 @@ typedef struct { uint64_t low, high; #endif } float128; -#define make_float128(high_, low_) ((float128) { .high = high_, .low = low_ }) -#define make_float128_init(high_, low_) { .high = high_, .low = low_ } +#ifdef HOST_WORDS_BIGENDIAN +#define make_float128(high_, low_) ((float128) { high_, low_ }) +#define make_float128_init(high_, low_) { high_, low_ } +#else +#define make_float128(high_, low_) ((float128) { low_, high_ }) +#define make_float128_init(high_, low_) { low_, high_ } +#endif /*---------------------------------------------------------------------------- | Software IEC/IEEE floating-point underflow tininess-detection mode. diff --git a/qemu/include/glib_compat.h b/qemu/include/glib_compat.h index b227d310..191fb864 100644 --- a/qemu/include/glib_compat.h +++ b/qemu/include/glib_compat.h @@ -20,7 +20,7 @@ Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. #ifndef __GLIB_COMPAT_H #define __GLIB_COMPAT_H -#include +#include "platform.h" #include #include #include diff --git a/qemu/include/hw/i386/apic_internal.h b/qemu/include/hw/i386/apic_internal.h index f587cbd8..b833d147 100644 --- a/qemu/include/hw/i386/apic_internal.h +++ b/qemu/include/hw/i386/apic_internal.h @@ -128,13 +128,13 @@ struct APICCommonState { hwaddr vapic_paddr; /* note: persistence via kvmvapic */ }; -typedef struct VAPICState { +QEMU_PACK( typedef struct VAPICState { uint8_t tpr; uint8_t isr; uint8_t zero; uint8_t irr; uint8_t enabled; -} QEMU_PACKED VAPICState; +}) VAPICState; extern bool apic_report_tpr_access; diff --git a/qemu/include/qapi/error.h b/qemu/include/qapi/error.h index f73dd58b..3b014053 100644 --- a/qemu/include/qapi/error.h +++ b/qemu/include/qapi/error.h @@ -14,7 +14,7 @@ #include "qemu/compiler.h" #include "qapi-types.h" -#include +#include "platform.h" /** * A class representing internal errors within QEMU. An error has a ErrorClass diff --git a/qemu/include/qapi/qmp/qbool.h b/qemu/include/qapi/qmp/qbool.h index c4eaab9b..9a9823c2 100644 --- a/qemu/include/qapi/qmp/qbool.h +++ b/qemu/include/qapi/qmp/qbool.h @@ -14,7 +14,7 @@ #ifndef QBOOL_H #define QBOOL_H -#include +#include "platform.h" #include "qapi/qmp/qobject.h" typedef struct QBool { diff --git a/qemu/include/qapi/qmp/qdict.h b/qemu/include/qapi/qmp/qdict.h index d68f4eb4..392ce3d8 100644 --- a/qemu/include/qapi/qmp/qdict.h +++ b/qemu/include/qapi/qmp/qdict.h @@ -16,8 +16,7 @@ #include "qapi/qmp/qobject.h" #include "qapi/qmp/qlist.h" #include "qemu/queue.h" -#include -#include +#include "platform.h" #define QDICT_BUCKET_MAX 512 diff --git a/qemu/include/qapi/qmp/qfloat.h b/qemu/include/qapi/qmp/qfloat.h index a8658443..775b86ec 100644 --- a/qemu/include/qapi/qmp/qfloat.h +++ b/qemu/include/qapi/qmp/qfloat.h @@ -14,7 +14,7 @@ #ifndef QFLOAT_H #define QFLOAT_H -#include +#include "platform.h" #include "qapi/qmp/qobject.h" typedef struct QFloat { diff --git a/qemu/include/qapi/qmp/qint.h b/qemu/include/qapi/qmp/qint.h index 48a41b0f..723fd55c 100644 --- a/qemu/include/qapi/qmp/qint.h +++ b/qemu/include/qapi/qmp/qint.h @@ -13,7 +13,7 @@ #ifndef QINT_H #define QINT_H -#include +#include "platform.h" #include "qapi/qmp/qobject.h" typedef struct QInt { diff --git a/qemu/include/qapi/qmp/qstring.h b/qemu/include/qapi/qmp/qstring.h index 1bc36661..e24325e9 100644 --- a/qemu/include/qapi/qmp/qstring.h +++ b/qemu/include/qapi/qmp/qstring.h @@ -13,7 +13,7 @@ #ifndef QSTRING_H #define QSTRING_H -#include +#include "platform.h" #include "qapi/qmp/qobject.h" typedef struct QString { diff --git a/qemu/include/qemu-common.h b/qemu/include/qemu-common.h index 8ddddb40..66126029 100644 --- a/qemu/include/qemu-common.h +++ b/qemu/include/qemu-common.h @@ -27,18 +27,14 @@ #include #include #include -#include +#include "platform.h" #include -#include -#include #include #include #include #include -#include #include #include -#include #include #include #include "glib_compat.h" @@ -195,7 +191,7 @@ static inline uint64_t muldiv64(uint64_t a, uint32_t b, uint32_t c) rl = (uint64_t)u.l.low * (uint64_t)b; rh = (uint64_t)u.l.high * (uint64_t)b; rh += (rl >> 32); - res.l.high = rh / c; + res.l.high = (uint32_t)(rh / c); res.l.low = (((rh % c) << 32) + (rl & 0xffffffff)) / c; return res.ll; } @@ -235,4 +231,23 @@ static inline uint64_t muldiv64(uint64_t a, uint32_t b, uint32_t c) #define ALL_EQ(v1, v2) ((v1) == (v2)) #endif +// support for calling functions before main code is executed. +#if defined(_MSC_VER) + #pragma section(".CRT$XCU",read) + #define INITIALIZER2_(f,p) \ + static void f(void); \ + __declspec(allocate(".CRT$XCU")) void (*f##_)(void) = f; \ + __pragma(comment(linker,"/include:" p #f "_")) \ + static void f(void) + #ifdef _WIN64 + #define INITIALIZER(f) INITIALIZER2_(f,"") + #else + #define INITIALIZER(f) INITIALIZER2_(f,"_") + #endif +#else + #define INITIALIZER(f) \ + static void f(void) __attribute__((constructor)); \ + static void f(void) +#endif + #endif diff --git a/qemu/include/qemu/atomic.h b/qemu/include/qemu/atomic.h index 492bce1c..b4d5d6b0 100644 --- a/qemu/include/qemu/atomic.h +++ b/qemu/include/qemu/atomic.h @@ -18,7 +18,12 @@ /* For C11 atomic ops */ /* Compiler barrier */ +#ifdef _MSC_VER +// TODO: fix me!!! +#define barrier() //{ __asm volatile("" ::: "memory"); (void)0; } +#else #define barrier() ({ asm volatile("" ::: "memory"); (void)0; }) +#endif #ifndef __ATOMIC_RELAXED @@ -31,9 +36,19 @@ #if defined(__i386__) || defined(__x86_64__) #if !QEMU_GNUC_PREREQ(4, 4) #if defined __x86_64__ -#define smp_mb() ({ asm volatile("mfence" ::: "memory"); (void)0; }) +# ifdef _MSC_VER +// TODO: fix me!!! +# define smp_mb() //{ __asm volatile("mfence" ::: "memory"); (void)0; } +# else +# define smp_mb() ({ asm volatile("mfence" ::: "memory"); (void)0; }) +# endif #else -#define smp_mb() ({ asm volatile("lock; addl $0,0(%%esp) " ::: "memory"); (void)0; }) +# ifdef _MSC_VER +// TODO: fix me!!! +# define smp_mb() //{ __asm volatile("lock; addl $0,0(%esp) " ::: "memory"); (void)0; } +# else +# define smp_mb() ({ asm volatile("lock; addl $0,0(%%esp) " ::: "memory"); (void)0; }) +# endif #endif #endif #endif @@ -183,6 +198,19 @@ #endif /* Provide shorter names for GCC atomic builtins. */ +#ifdef _MSC_VER +#ifdef _WIN64 +#define atomic_fetch_inc(ptr) InterlockedIncrement64(ptr) +#define atomic_fetch_dec(ptr) InterlockedDecrement64(ptr) +#define atomic_fetch_add(ptr, n) InterlockedAdd64(ptr, n) +#define atomic_fetch_sub(ptr, n) InterlockedAdd64(ptr, -n) +#else +#define atomic_fetch_inc(ptr) InterlockedIncrement(ptr) +#define atomic_fetch_dec(ptr) InterlockedDecrement(ptr) +#define atomic_fetch_add(ptr, n) InterlockedAdd(ptr, n) +#define atomic_fetch_sub(ptr, n) InterlockedAdd(ptr, -n) +#endif +#else #define atomic_fetch_inc(ptr) __sync_fetch_and_add(ptr, 1) #define atomic_fetch_dec(ptr) __sync_fetch_and_add(ptr, -1) #define atomic_fetch_add __sync_fetch_and_add @@ -190,13 +218,28 @@ #define atomic_fetch_and __sync_fetch_and_and #define atomic_fetch_or __sync_fetch_and_or #define atomic_cmpxchg __sync_val_compare_and_swap +#endif /* And even shorter names that return void. */ +#ifdef _MSC_VER +#ifdef _WIN64 +#define atomic_inc(ptr) ((void) InterlockedIncrement64(ptr)) +#define atomic_dec(ptr) ((void) InterlockedDecrement64(ptr)) +#define atomic_add(ptr, n) ((void) InterlockedAdd64(ptr, n)) +#define atomic_sub(ptr, n) ((void) InterlockedAdd64(ptr, -n)) +#else +#define atomic_inc(ptr) ((void) InterlockedIncrement(ptr)) +#define atomic_dec(ptr) ((void) InterlockedDecrement(ptr)) +#define atomic_add(ptr, n) ((void) InterlockedAdd(ptr, n)) +#define atomic_sub(ptr, n) ((void) InterlockedAdd(ptr, -n)) +#endif +#else #define atomic_inc(ptr) ((void) __sync_fetch_and_add(ptr, 1)) #define atomic_dec(ptr) ((void) __sync_fetch_and_add(ptr, -1)) #define atomic_add(ptr, n) ((void) __sync_fetch_and_add(ptr, n)) #define atomic_sub(ptr, n) ((void) __sync_fetch_and_sub(ptr, n)) #define atomic_and(ptr, n) ((void) __sync_fetch_and_and(ptr, n)) #define atomic_or(ptr, n) ((void) __sync_fetch_and_or(ptr, n)) +#endif #endif diff --git a/qemu/include/qemu/bitops.h b/qemu/include/qemu/bitops.h index 913bdb7b..792d03ad 100644 --- a/qemu/include/qemu/bitops.h +++ b/qemu/include/qemu/bitops.h @@ -12,7 +12,7 @@ #ifndef BITOPS_H #define BITOPS_H -#include +#include "platform.h" #include #include "host-utils.h" diff --git a/qemu/include/qemu/bswap.h b/qemu/include/qemu/bswap.h index 78c1ced4..64a3e170 100644 --- a/qemu/include/qemu/bswap.h +++ b/qemu/include/qemu/bswap.h @@ -2,7 +2,7 @@ #define BSWAP_H #include "config-host.h" -#include +#include "platform.h" #include #include #include "fpu/softfloat.h" diff --git a/qemu/include/qemu/compiler.h b/qemu/include/qemu/compiler.h index ac7c4c44..fe50eccd 100644 --- a/qemu/include/qemu/compiler.h +++ b/qemu/include/qemu/compiler.h @@ -5,6 +5,58 @@ #include "config-host.h" +#ifdef _MSC_VER +// MSVC support + +#define inline __inline +#define __func__ __FUNCTION__ + +#include +#include +#define isinf(x) (!_finite(x)) + +static double rint( double x ) +{ + return floor(x < 0 ? x - 0.5 : x + 0.5); +} + +union MSVC_FLOAT_HACK +{ + unsigned char Bytes[4]; + float Value; +}; + +#ifndef NAN +static union MSVC_FLOAT_HACK __NAN = {{0x00, 0x00, 0xC0, 0x7F}}; +#define NAN (__NAN.Value) +#endif + +#define QEMU_DIV0 __pragma(warning(suppress:2124)) // divide by zero error + +#define QEMU_GNUC_PREREQ(maj, min) 0 + +#define QEMU_NORETURN __declspec(noreturn) +#define QEMU_UNUSED_VAR __pragma(warning(suppress:4100)) // unused variables only +#define QEMU_UNUSED_FUNC +#define QEMU_WARN_UNUSED_RESULT +#define QEMU_ARTIFICIAL +#define QEMU_PACK( __Declaration__ ) __pragma( pack(push, 1) ) __Declaration__ __pragma( pack(pop) ) + +#define QEMU_ALIGN(A, B) __declspec(align(A)) B + +#define cat(x,y) x ## y +#define cat2(x,y) cat(x,y) +#define QEMU_BUILD_BUG_ON(x) \ + typedef char cat2(qemu_build_bug_on__,__LINE__)[(x)?-1:1] QEMU_UNUSED_VAR; + +#define GCC_FMT_ATTR(n, m) + +#else + +#ifndef NAN +#define NAN (0.0 / 0.0) +#endif + /*---------------------------------------------------------------------------- | The macro QEMU_GNUC_PREREQ tests for minimum version of the GNU C compiler. | The code is a copy of SOFTFLOAT_GNUC_PREREQ, see softfloat-macros.h. @@ -18,6 +70,9 @@ #define QEMU_NORETURN __attribute__ ((__noreturn__)) +#define QEMU_UNUSED_VAR __attribute__((unused)) +#define QEMU_UNUSED_FUNC __attribute__((unused)) + #if QEMU_GNUC_PREREQ(3, 4) #define QEMU_WARN_UNUSED_RESULT __attribute__((warn_unused_result)) #else @@ -31,11 +86,13 @@ #endif #if defined(_WIN32) -# define QEMU_PACKED __attribute__((gcc_struct, packed)) +# define QEMU_PACK( __Declaration__ ) __Declaration__ __attribute__((gcc_struct, packed)) #else -# define QEMU_PACKED __attribute__((packed)) +# define QEMU_PACK( __Declaration__ ) __Declaration__ __attribute__((packed)) #endif +#define QEMU_ALIGN(A, B) B __attribute__((aligned(A))) + #define cat(x,y) x ## y #define cat2(x,y) cat(x,y) #define QEMU_BUILD_BUG_ON(x) \ @@ -58,4 +115,6 @@ #define GCC_FMT_ATTR(n, m) #endif +#endif // _MSC_VER + #endif /* COMPILER_H */ diff --git a/qemu/include/qemu/host-utils.h b/qemu/include/qemu/host-utils.h index d4f21c94..d8707451 100644 --- a/qemu/include/qemu/host-utils.h +++ b/qemu/include/qemu/host-utils.h @@ -150,7 +150,7 @@ static inline int clz64(uint64_t val) val >>= 32; } - return cnt + clz32(val); + return cnt + clz32((uint32_t)val); #endif } @@ -240,7 +240,7 @@ static inline int ctz64(uint64_t val) val >>= 32; } - return cnt + ctz32(val); + return cnt + ctz32((uint32_t)val); #endif } @@ -357,7 +357,7 @@ static inline int ctpop64(uint64_t val) val = (val & 0x0000ffff0000ffffULL) + ((val >> 16) & 0x0000ffff0000ffffULL); val = (val & 0x00000000ffffffffULL) + ((val >> 32) & 0x00000000ffffffffULL); - return val; + return (int)val; #endif } @@ -379,4 +379,13 @@ static inline int ctpop64(uint64_t val) # error Unknown sizeof long #endif +#ifdef _MSC_VER +#include +#if defined(_WIN64) +#define isnan _isnanf +#else +#define isnan _isnan +#endif +#endif + #endif diff --git a/qemu/include/qemu/int128.h b/qemu/include/qemu/int128.h index fd0fe71d..cf4e6fb0 100644 --- a/qemu/include/qemu/int128.h +++ b/qemu/include/qemu/int128.h @@ -2,8 +2,7 @@ #define INT128_H //#include -#include -#include +#include "platform.h" typedef struct Int128 Int128; @@ -14,7 +13,8 @@ struct Int128 { static inline Int128 int128_make64(uint64_t a) { - return (Int128) { a, 0 }; + Int128 i128 = { a, 0 }; + return i128; } static inline uint64_t int128_get64(Int128 a) @@ -35,17 +35,20 @@ static inline Int128 int128_one(void) static inline Int128 int128_2_64(void) { - return (Int128) { 0, 1 }; + Int128 i128 = { 0, 1 }; + return i128; } static inline Int128 int128_exts64(int64_t a) { - return (Int128) { .lo = a, .hi = (a < 0) ? -1 : 0 }; + Int128 i128 = { a, (a < 0) ? -1 : 0 }; + return i128; } static inline Int128 int128_and(Int128 a, Int128 b) { - return (Int128) { a.lo & b.lo, a.hi & b.hi }; + Int128 i128 = { a.lo & b.lo, a.hi & b.hi }; + return i128; } static inline Int128 int128_rshift(Int128 a, int n) @@ -56,9 +59,11 @@ static inline Int128 int128_rshift(Int128 a, int n) } h = a.hi >> (n & 63); if (n >= 64) { - return (Int128) { h, h >> 63 }; + Int128 i128 = { h, h >> 63 }; + return i128; } else { - return (Int128) { (a.lo >> n) | ((uint64_t)a.hi << (64 - n)), h }; + Int128 i128 = { (a.lo >> n) | ((uint64_t)a.hi << (64 - n)), h }; + return i128; } } @@ -72,18 +77,21 @@ static inline Int128 int128_add(Int128 a, Int128 b) * * So the carry is lo < a.lo. */ - return (Int128) { lo, (uint64_t)a.hi + b.hi + (lo < a.lo) }; + Int128 i128 = { lo, (uint64_t)a.hi + b.hi + (lo < a.lo) }; + return i128; } static inline Int128 int128_neg(Int128 a) { - uint64_t lo = -a.lo; - return (Int128) { lo, ~(uint64_t)a.hi + !lo }; + uint64_t lo = 0-a.lo; + Int128 i128 = { lo, ~(uint64_t)a.hi + !lo }; + return i128; } static inline Int128 int128_sub(Int128 a, Int128 b) { - return (Int128){ a.lo - b.lo, (uint64_t)a.hi - b.hi - (a.lo < b.lo) }; + Int128 i128 = { a.lo - b.lo, (uint64_t)a.hi - b.hi - (a.lo < b.lo) }; + return i128; } static inline bool int128_nonneg(Int128 a) diff --git a/qemu/include/qemu/log.h b/qemu/include/qemu/log.h index d8824137..e9d34f5e 100644 --- a/qemu/include/qemu/log.h +++ b/qemu/include/qemu/log.h @@ -2,8 +2,7 @@ #define QEMU_LOG_H #include -#include -#include +#include "platform.h" #include "qemu/compiler.h" #include "qom/cpu.h" diff --git a/qemu/include/qemu/module.h b/qemu/include/qemu/module.h index 4161e23c..db2ebdea 100644 --- a/qemu/include/qemu/module.h +++ b/qemu/include/qemu/module.h @@ -26,15 +26,17 @@ void DSO_STAMP_FUN(void); * check fails during module loading */ void qemu_module_dummy(void); +//static void __attribute__((constructor)) do_qemu_init_ ## function(void) +//static void __attribute__((constructor)) do_qemu_init_ ## function(void) #define module_init(function, type) \ -static void __attribute__((constructor)) do_qemu_init_ ## function(void) \ + INITIALIZER(do_qemu_init_ ## function) \ { \ register_dso_module_init(function, type); \ } #else /* This should not be used directly. Use block_init etc. instead. */ #define module_init(function, type) \ -static void __attribute__((constructor)) do_qemu_init_ ## function(void) \ + INITIALIZER(do_qemu_init_ ## function) \ { \ register_module_init(function, type); \ } diff --git a/qemu/include/qemu/osdep.h b/qemu/include/qemu/osdep.h index dbd795a0..4536341a 100644 --- a/qemu/include/qemu/osdep.h +++ b/qemu/include/qemu/osdep.h @@ -4,8 +4,7 @@ #include "config-host.h" #include #include -#include -#include +#include "platform.h" #include #ifdef __OpenBSD__ #include @@ -18,7 +17,7 @@ #define WEXITSTATUS(x) (x) #endif -#include +#include "platform.h" #if defined(CONFIG_SOLARIS) && CONFIG_SOLARIS_VERSION < 10 /* [u]int_fast*_t not in */ @@ -44,15 +43,19 @@ typedef signed int int_fast16_t; #endif #ifndef container_of +#ifndef _MSC_VER #define container_of(ptr, type, member) ({ \ const typeof(((type *) 0)->member) *__mptr = (ptr); \ (type *) ((char *) __mptr - offsetof(type, member));}) +#else +#define container_of(ptr, type, member) ((type *)((char *)(ptr) -offsetof(type,member))) +#endif #endif /* Convert from a base type to a parent type, with compile time checking. */ #ifdef __GNUC__ #define DO_UPCAST(type, field, dev) ( __extension__ ( { \ - char __attribute__((unused)) offset_must_be_zero[ \ + char QEMU_UNUSED_VAR offset_must_be_zero[ \ -offsetof(type, field)]; \ container_of(dev, type, field);})) #else diff --git a/qemu/include/qemu/range.h b/qemu/include/qemu/range.h index cfa021fd..7d6c9f2b 100644 --- a/qemu/include/qemu/range.h +++ b/qemu/include/qemu/range.h @@ -1,7 +1,7 @@ #ifndef QEMU_RANGE_H #define QEMU_RANGE_H -#include +#include "platform.h" #include #include "qemu/queue.h" diff --git a/qemu/include/qemu/thread.h b/qemu/include/qemu/thread.h index 39336f79..b2f1145b 100644 --- a/qemu/include/qemu/thread.h +++ b/qemu/include/qemu/thread.h @@ -1,8 +1,7 @@ #ifndef __QEMU_THREAD_H #define __QEMU_THREAD_H 1 -#include -#include +#include "platform.h" typedef struct QemuMutex QemuMutex; typedef struct QemuThread QemuThread; diff --git a/qemu/include/qemu/timer.h b/qemu/include/qemu/timer.h index f3612863..5cc5c8aa 100644 --- a/qemu/include/qemu/timer.h +++ b/qemu/include/qemu/timer.h @@ -493,7 +493,7 @@ static inline int64_t get_clock(void) { LARGE_INTEGER ti; QueryPerformanceCounter(&ti); - return muldiv64(ti.QuadPart, get_ticks_per_sec(), clock_freq); + return muldiv64(ti.QuadPart, (uint32_t)get_ticks_per_sec(), (uint32_t)clock_freq); } #else @@ -545,9 +545,13 @@ static inline int64_t cpu_get_real_ticks(void) static inline int64_t cpu_get_real_ticks(void) { +#ifdef _MSC_VER + return __rdtsc(); +#else int64_t val; asm volatile ("rdtsc" : "=A" (val)); return val; +#endif } #elif defined(__x86_64__) diff --git a/qemu/include/qom/cpu.h b/qemu/include/qom/cpu.h index 94f38d17..016aa053 100644 --- a/qemu/include/qom/cpu.h +++ b/qemu/include/qom/cpu.h @@ -532,7 +532,7 @@ static inline void cpu_unaligned_access(CPUState *cpu, vaddr addr, { CPUClass *cc = CPU_GET_CLASS(cpu->uc, cpu); - return cc->do_unaligned_access(cpu, addr, is_write, is_user, retaddr); + cc->do_unaligned_access(cpu, addr, is_write, is_user, retaddr); } #endif diff --git a/qemu/include/qom/object.h b/qemu/include/qom/object.h index 93298b53..b18a2b7f 100644 --- a/qemu/include/qom/object.h +++ b/qemu/include/qom/object.h @@ -15,8 +15,7 @@ #define QEMU_OBJECT_H #include "glib_compat.h" -#include -#include +#include "platform.h" #include "qemu/queue.h" #include "qapi/error.h" diff --git a/qemu/include/sysemu/os-win32.h b/qemu/include/sysemu/os-win32.h index 4b391305..b0494872 100644 --- a/qemu/include/sysemu/os-win32.h +++ b/qemu/include/sysemu/os-win32.h @@ -26,6 +26,7 @@ #ifndef QEMU_OS_WIN32_H #define QEMU_OS_WIN32_H +#include #include #include diff --git a/qemu/ioport.c b/qemu/ioport.c index c7ac6b85..bed2c13d 100644 --- a/qemu/ioport.c +++ b/qemu/ioport.c @@ -49,7 +49,7 @@ typedef struct MemoryRegionPortioList { static uint64_t unassigned_io_read(struct uc_struct* uc, void *opaque, hwaddr addr, unsigned size) { - return -1ULL; + return 0-1ULL; } static void unassigned_io_write(struct uc_struct* uc, void *opaque, hwaddr addr, uint64_t val, @@ -58,9 +58,9 @@ static void unassigned_io_write(struct uc_struct* uc, void *opaque, hwaddr addr, } const MemoryRegionOps unassigned_io_ops = { - .read = unassigned_io_read, - .write = unassigned_io_write, - .endianness = DEVICE_NATIVE_ENDIAN, + unassigned_io_read, + unassigned_io_write, + DEVICE_NATIVE_ENDIAN, }; void cpu_outb(struct uc_struct *uc, pio_addr_t addr, uint8_t val) @@ -68,6 +68,7 @@ void cpu_outb(struct uc_struct *uc, pio_addr_t addr, uint8_t val) //LOG_IOPORT("outb: %04"FMT_pioaddr" %02"PRIx8"\n", addr, val); // Unicorn: call registered OUT callbacks struct hook *hook; + HOOK_FOREACH_VAR_DECLARE; HOOK_FOREACH(uc, hook, UC_HOOK_INSN) { if (hook->insn == UC_X86_INS_OUT) ((uc_cb_insn_out_t)hook->callback)(uc, addr, 1, val, hook->user_data); @@ -79,6 +80,7 @@ void cpu_outw(struct uc_struct *uc, pio_addr_t addr, uint16_t val) //LOG_IOPORT("outw: %04"FMT_pioaddr" %04"PRIx16"\n", addr, val); // Unicorn: call registered OUT callbacks struct hook *hook; + HOOK_FOREACH_VAR_DECLARE; HOOK_FOREACH(uc, hook, UC_HOOK_INSN) { if (hook->insn == UC_X86_INS_OUT) ((uc_cb_insn_out_t)hook->callback)(uc, addr, 2, val, hook->user_data); @@ -90,6 +92,7 @@ void cpu_outl(struct uc_struct *uc, pio_addr_t addr, uint32_t val) //LOG_IOPORT("outl: %04"FMT_pioaddr" %08"PRIx32"\n", addr, val); // Unicorn: call registered OUT callbacks struct hook *hook; + HOOK_FOREACH_VAR_DECLARE; HOOK_FOREACH(uc, hook, UC_HOOK_INSN) { if (hook->insn == UC_X86_INS_OUT) ((uc_cb_insn_out_t)hook->callback)(uc, addr, 4, val, hook->user_data); @@ -101,6 +104,7 @@ uint8_t cpu_inb(struct uc_struct *uc, pio_addr_t addr) //LOG_IOPORT("inb : %04"FMT_pioaddr" %02"PRIx8"\n", addr, val); // Unicorn: call registered IN callbacks struct hook *hook; + HOOK_FOREACH_VAR_DECLARE; HOOK_FOREACH(uc, hook, UC_HOOK_INSN) { if (hook->insn == UC_X86_INS_IN) return ((uc_cb_insn_in_t)hook->callback)(uc, addr, 1, hook->user_data); @@ -114,6 +118,7 @@ uint16_t cpu_inw(struct uc_struct *uc, pio_addr_t addr) //LOG_IOPORT("inw : %04"FMT_pioaddr" %04"PRIx16"\n", addr, val); // Unicorn: call registered IN callbacks struct hook *hook; + HOOK_FOREACH_VAR_DECLARE; HOOK_FOREACH(uc, hook, UC_HOOK_INSN) { if (hook->insn == UC_X86_INS_IN) return ((uc_cb_insn_in_t)hook->callback)(uc, addr, 2, hook->user_data); @@ -127,6 +132,7 @@ uint32_t cpu_inl(struct uc_struct *uc, pio_addr_t addr) //LOG_IOPORT("inl : %04"FMT_pioaddr" %08"PRIx32"\n", addr, val); // Unicorn: call registered IN callbacks struct hook *hook; + HOOK_FOREACH_VAR_DECLARE; HOOK_FOREACH(uc, hook, UC_HOOK_INSN) { if (hook->insn == UC_X86_INS_IN) return ((uc_cb_insn_in_t)hook->callback)(uc, addr, 4, hook->user_data); diff --git a/qemu/memory.c b/qemu/memory.c index 453ddce1..0aa1df68 100644 --- a/qemu/memory.c +++ b/qemu/memory.c @@ -147,7 +147,10 @@ struct AddrRange { static AddrRange addrrange_make(Int128 start, Int128 size) { - return (AddrRange) { start, size }; + AddrRange ar; + ar.start = start; + ar.size = size; + return ar; } static bool addrrange_equal(AddrRange r1, AddrRange r2) @@ -194,7 +197,7 @@ static bool memory_listener_match(MemoryListener *listener, || listener->address_space_filter == section->address_space; } -#define MEMORY_LISTENER_CALL_GLOBAL(_callback, _direction, _args...) \ +#define MEMORY_LISTENER_CALL_GLOBAL(_callback, _direction, ...) \ do { \ MemoryListener *_listener; \ \ @@ -202,7 +205,7 @@ static bool memory_listener_match(MemoryListener *listener, case Forward: \ QTAILQ_FOREACH(_listener, &uc->memory_listeners, link) { \ if (_listener->_callback) { \ - _listener->_callback(_listener, ##_args); \ + _listener->_callback(_listener, ##__VA_ARGS__); \ } \ } \ break; \ @@ -210,7 +213,7 @@ static bool memory_listener_match(MemoryListener *listener, QTAILQ_FOREACH_REVERSE(_listener, &uc->memory_listeners, \ memory_listeners, link) { \ if (_listener->_callback) { \ - _listener->_callback(_listener, ##_args); \ + _listener->_callback(_listener, ##__VA_ARGS__); \ } \ } \ break; \ @@ -219,7 +222,7 @@ static bool memory_listener_match(MemoryListener *listener, } \ } while (0) -#define MEMORY_LISTENER_CALL(_callback, _direction, _section, _args...) \ +#define MEMORY_LISTENER_CALL(_callback, _direction, _section, ...) \ do { \ MemoryListener *_listener; \ \ @@ -228,7 +231,7 @@ static bool memory_listener_match(MemoryListener *listener, QTAILQ_FOREACH(_listener, &uc->memory_listeners, link) { \ if (_listener->_callback \ && memory_listener_match(_listener, _section)) { \ - _listener->_callback(_listener, _section, ##_args); \ + _listener->_callback(_listener, _section, ##__VA_ARGS__); \ } \ } \ break; \ @@ -237,7 +240,7 @@ static bool memory_listener_match(MemoryListener *listener, memory_listeners, link) { \ if (_listener->_callback \ && memory_listener_match(_listener, _section)) { \ - _listener->_callback(_listener, _section, ##_args); \ + _listener->_callback(_listener, _section, ##__VA_ARGS__); \ } \ } \ break; \ @@ -248,6 +251,11 @@ static bool memory_listener_match(MemoryListener *listener, /* No need to ref/unref .mr, the FlatRange keeps it alive. */ #define MEMORY_LISTENER_UPDATE_REGION(fr, as, dir, callback) \ + do { MemoryRegionSection _mrs = MemoryRegionSection_make((fr)->mr, as, (fr)->offset_in_region, \ + (fr)->addr.size, int128_get64((fr)->addr.start), (fr)->readonly); \ + MEMORY_LISTENER_CALL(callback, dir, &_mrs); } while(0); + +/* MEMORY_LISTENER_CALL(callback, dir, (&(MemoryRegionSection) { \ .mr = (fr)->mr, \ .address_space = (as), \ @@ -256,6 +264,7 @@ static bool memory_listener_match(MemoryListener *listener, .offset_within_address_space = int128_get64((fr)->addr.start), \ .readonly = (fr)->readonly, \ })) +*/ struct CoalescedMemoryRange { AddrRange addr; @@ -269,6 +278,16 @@ struct MemoryRegionIoeventfd { EventNotifier *e; }; +static MemoryRegionIoeventfd MemoryRegionIoeventfd_make(AddrRange addr, bool match_data, uint64_t data, EventNotifier *e) +{ + MemoryRegionIoeventfd mrfd; + mrfd.addr = addr; + mrfd.match_data = match_data; + mrfd.data = data; + mrfd.e = e; + return mrfd; +} + static bool memory_region_ioeventfd_before(MemoryRegionIoeventfd a, MemoryRegionIoeventfd b) { @@ -546,7 +565,7 @@ static void access_with_adjusted_size(hwaddr addr, /* FIXME: support unaligned access? */ access_size = MAX(MIN(size, access_size_max), access_size_min); - access_mask = -1ULL >> (64 - access_size * 8); + access_mask = (0-1ULL) >> (64 - access_size * 8); if (memory_region_big_endian(mr)) { for (i = 0; i < size; i += access_size) { access(mr, addr + i, value, access_size, @@ -700,11 +719,7 @@ static void address_space_add_del_ioeventfds(AddressSpace *as, || memory_region_ioeventfd_before(fds_old[iold], fds_new[inew]))) { fd = &fds_old[iold]; - section = (MemoryRegionSection) { - .address_space = as, - .offset_within_address_space = int128_get64(fd->addr.start), - .size = fd->addr.size, - }; + section = MemoryRegionSection_make(NULL, as, 0, fd->addr.size, int128_get64(fd->addr.start), false); MEMORY_LISTENER_CALL(eventfd_del, Forward, §ion, fd->match_data, fd->data, fd->e); ++iold; @@ -713,11 +728,7 @@ static void address_space_add_del_ioeventfds(AddressSpace *as, || memory_region_ioeventfd_before(fds_new[inew], fds_old[iold]))) { fd = &fds_new[inew]; - section = (MemoryRegionSection) { - .address_space = as, - .offset_within_address_space = int128_get64(fd->addr.start), - .size = fd->addr.size, - }; + section = MemoryRegionSection_make(NULL, as, 0, fd->addr.size, int128_get64(fd->addr.start), false); MEMORY_LISTENER_CALL(eventfd_add, Reverse, §ion, fd->match_data, fd->data, fd->e); ++inew; @@ -1101,8 +1112,12 @@ static bool unassigned_mem_accepts(void *opaque, hwaddr addr, } const MemoryRegionOps unassigned_mem_ops = { - .valid.accepts = unassigned_mem_accepts, - .endianness = DEVICE_NATIVE_ENDIAN, + NULL, + NULL, + + DEVICE_NATIVE_ENDIAN, + + {0,0,false,unassigned_mem_accepts}, }; bool memory_region_access_valid(MemoryRegion *mr, @@ -1356,7 +1371,7 @@ bool memory_region_is_rom(MemoryRegion *mr) bool memory_region_is_iommu(MemoryRegion *mr) { - return mr->iommu_ops; + return mr->iommu_ops != 0; } void memory_region_register_iommu_notifier(MemoryRegion *mr, Notifier *n) @@ -1416,7 +1431,7 @@ int memory_region_get_fd(MemoryRegion *mr) void *memory_region_get_ram_ptr(MemoryRegion *mr) { if (mr->alias) { - return memory_region_get_ram_ptr(mr->alias) + mr->alias_offset; + return (char*)memory_region_get_ram_ptr(mr->alias) + mr->alias_offset; } assert(mr->terminates); @@ -1436,11 +1451,7 @@ static void memory_region_update_coalesced_range_as(MemoryRegion *mr, AddressSpa view = address_space_get_flatview(as); FOR_EACH_FLAT_RANGE(fr, view) { if (fr->mr == mr) { - section = (MemoryRegionSection) { - .address_space = as, - .offset_within_address_space = int128_get64(fr->addr.start), - .size = fr->addr.size, - }; + section = MemoryRegionSection_make(NULL, as, 0, fr->addr.size, int128_get64(fr->addr.start), false); MEMORY_LISTENER_CALL(coalesced_mmio_del, Reverse, §ion, int128_get64(fr->addr.start), @@ -1498,13 +1509,9 @@ void memory_region_add_eventfd(MemoryRegion *mr, uint64_t data, EventNotifier *e) { - MemoryRegionIoeventfd mrfd = { - .addr.start = int128_make64(addr), - .addr.size = int128_make64(size), - .match_data = match_data, - .data = data, - .e = e, - }; + MemoryRegionIoeventfd mrfd = MemoryRegionIoeventfd_make( + addrrange_make(int128_make64(addr), int128_make64(size)), + match_data, data, e); unsigned i; adjust_endianness(mr, &mrfd.data, size); @@ -1531,13 +1538,9 @@ void memory_region_del_eventfd(MemoryRegion *mr, uint64_t data, EventNotifier *e) { - MemoryRegionIoeventfd mrfd = { - .addr.start = int128_make64(addr), - .addr.size = int128_make64(size), - .match_data = match_data, - .data = data, - .e = e, - }; + MemoryRegionIoeventfd mrfd = MemoryRegionIoeventfd_make( + addrrange_make(int128_make64(addr), int128_make64(size)), + match_data, data, e); unsigned i; adjust_endianness(mr, &mrfd.data, size); @@ -1736,7 +1739,7 @@ bool memory_region_is_mapped(MemoryRegion *mr) MemoryRegionSection memory_region_find(MemoryRegion *mr, hwaddr addr, uint64_t size) { - MemoryRegionSection ret = { .mr = NULL }; + MemoryRegionSection ret = { NULL }; MemoryRegion *root; AddressSpace *as; AddrRange range; @@ -1800,14 +1803,13 @@ static void listener_add_address_space(MemoryListener *listener, view = address_space_get_flatview(as); FOR_EACH_FLAT_RANGE(fr, view) { - MemoryRegionSection section = { - .mr = fr->mr, - .address_space = as, - .offset_within_region = fr->offset_in_region, - .size = fr->addr.size, - .offset_within_address_space = int128_get64(fr->addr.start), - .readonly = fr->readonly, - }; + MemoryRegionSection section = MemoryRegionSection_make( + fr->mr, + as, + fr->offset_in_region, + fr->addr.size, + int128_get64(fr->addr.start), + fr->readonly); if (listener->region_add) { listener->region_add(listener, §ion); } @@ -1908,11 +1910,16 @@ struct MemoryRegionList { typedef QTAILQ_HEAD(queue, MemoryRegionList) MemoryRegionListHead; static const TypeInfo memory_region_info = { - .parent = TYPE_OBJECT, - .name = TYPE_MEMORY_REGION, - .instance_size = sizeof(MemoryRegion), - .instance_init = memory_region_initfn, - .instance_finalize = memory_region_finalize, + TYPE_MEMORY_REGION, + TYPE_OBJECT, + + 0, + sizeof(MemoryRegion), + NULL, + + memory_region_initfn, + NULL, + memory_region_finalize, }; void memory_register_types(struct uc_struct *uc) diff --git a/qemu/qapi/qapi-visit-core.c b/qemu/qapi/qapi-visit-core.c index b66b93ae..5f918403 100644 --- a/qemu/qapi/qapi-visit-core.c +++ b/qemu/qapi/qapi-visit-core.c @@ -114,7 +114,7 @@ void visit_type_uint8(Visitor *v, uint8_t *obj, const char *name, Error **errp) "uint8_t"); return; } - *obj = value; + *obj = (uint8_t)value; } } @@ -132,7 +132,7 @@ void visit_type_uint16(Visitor *v, uint16_t *obj, const char *name, Error **errp "uint16_t"); return; } - *obj = value; + *obj = (uint16_t)value; } } @@ -150,7 +150,7 @@ void visit_type_uint32(Visitor *v, uint32_t *obj, const char *name, Error **errp "uint32_t"); return; } - *obj = value; + *obj = (uint32_t)value; } } @@ -181,7 +181,7 @@ void visit_type_int8(Visitor *v, int8_t *obj, const char *name, Error **errp) "int8_t"); return; } - *obj = value; + *obj = (int8_t)value; } } @@ -199,7 +199,7 @@ void visit_type_int16(Visitor *v, int16_t *obj, const char *name, Error **errp) "int16_t"); return; } - *obj = value; + *obj = (int16_t)value; } } @@ -217,7 +217,7 @@ void visit_type_int32(Visitor *v, int32_t *obj, const char *name, Error **errp) "int32_t"); return; } - *obj = value; + *obj = (int32_t)value; } } @@ -309,5 +309,5 @@ void input_type_enum(Visitor *v, int *obj, const char *strings[], } g_free(enum_str); - *obj = value; + *obj = (int)value; } diff --git a/qemu/qapi/qmp-input-visitor.c b/qemu/qapi/qmp-input-visitor.c index d8612062..33dd754b 100644 --- a/qemu/qapi/qmp-input-visitor.c +++ b/qemu/qapi/qmp-input-visitor.c @@ -104,7 +104,7 @@ static void qmp_input_pop(QmpInputVisitor *qiv, Error **errp) if (top_ht) { if (g_hash_table_size(top_ht)) { const char *key; - g_hash_table_find(top_ht, always_true, &key); + g_hash_table_find(top_ht, always_true, (gpointer)&key); error_set(errp, QERR_QMP_EXTRA_MEMBER, key); } g_hash_table_unref(top_ht); @@ -280,7 +280,7 @@ static void qmp_input_type_number(Visitor *v, double *obj, const char *name, } if (qobject_type(qobj) == QTYPE_QINT) { - *obj = qint_get_int(qobject_to_qint(qobj)); + *obj = (double)qint_get_int(qobject_to_qint(qobj)); } else { *obj = qfloat_get_double(qobject_to_qfloat(qobj)); } diff --git a/qemu/qapi/string-input-visitor.c b/qemu/qapi/string-input-visitor.c index a9a0f588..cc5826e4 100644 --- a/qemu/qapi/string-input-visitor.c +++ b/qemu/qapi/string-input-visitor.c @@ -16,6 +16,7 @@ #include "qapi/qmp/qerror.h" #include "qemu/queue.h" #include "qemu/range.h" +#include // strtoll struct StringInputVisitor @@ -148,7 +149,7 @@ next_list(Visitor *v, GenericList **list, Error **errp) return NULL; } - if (siv->cur < r->begin || siv->cur >= r->end) { + if ((uint64_t)siv->cur < r->begin || (uint64_t)siv->cur >= r->end) { siv->cur_range = g_list_next(siv->cur_range); if (!siv->cur_range) { return NULL; diff --git a/qemu/qobject/qbool.c b/qemu/qobject/qbool.c index a3d2afa8..df4a23b7 100644 --- a/qemu/qobject/qbool.c +++ b/qemu/qobject/qbool.c @@ -18,8 +18,8 @@ static void qbool_destroy_obj(QObject *obj); static const QType qbool_type = { - .code = QTYPE_QBOOL, - .destroy = qbool_destroy_obj, + QTYPE_QBOOL, + qbool_destroy_obj, }; /** diff --git a/qemu/qobject/qdict.c b/qemu/qobject/qdict.c index ea239f08..e1a96a42 100644 --- a/qemu/qobject/qdict.c +++ b/qemu/qobject/qdict.c @@ -22,8 +22,8 @@ static void qdict_destroy_obj(QObject *obj); static const QType qdict_type = { - .code = QTYPE_QDICT, - .destroy = qdict_destroy_obj, + QTYPE_QDICT, + qdict_destroy_obj, }; /** @@ -213,7 +213,7 @@ double qdict_get_double(const QDict *qdict, const char *key) case QTYPE_QFLOAT: return qfloat_get_double(qobject_to_qfloat(obj)); case QTYPE_QINT: - return qint_get_int(qobject_to_qint(obj)); + return (double)qint_get_int(qobject_to_qint(obj)); default: abort(); } @@ -662,7 +662,7 @@ void qdict_array_split(QDict *src, QList **dst) qdict_del(src, indexstr); } - qlist_append_obj(*dst, subqobj ?: QOBJECT(subqdict)); + qlist_append_obj(*dst, (subqobj!=NULL) ? subqobj : QOBJECT(subqdict)); } } diff --git a/qemu/qobject/qfloat.c b/qemu/qobject/qfloat.c index 7de0992d..d6d4d3a2 100644 --- a/qemu/qobject/qfloat.c +++ b/qemu/qobject/qfloat.c @@ -18,8 +18,8 @@ static void qfloat_destroy_obj(QObject *obj); static const QType qfloat_type = { - .code = QTYPE_QFLOAT, - .destroy = qfloat_destroy_obj, + QTYPE_QFLOAT, + qfloat_destroy_obj, }; /** diff --git a/qemu/qobject/qint.c b/qemu/qobject/qint.c index 86b9b04f..e285d134 100644 --- a/qemu/qobject/qint.c +++ b/qemu/qobject/qint.c @@ -17,8 +17,8 @@ static void qint_destroy_obj(QObject *obj); static const QType qint_type = { - .code = QTYPE_QINT, - .destroy = qint_destroy_obj, + QTYPE_QINT, + qint_destroy_obj, }; /** diff --git a/qemu/qobject/qlist.c b/qemu/qobject/qlist.c index 1ced0de5..60ce805d 100644 --- a/qemu/qobject/qlist.c +++ b/qemu/qobject/qlist.c @@ -18,8 +18,8 @@ static void qlist_destroy_obj(QObject *obj); static const QType qlist_type = { - .code = QTYPE_QLIST, - .destroy = qlist_destroy_obj, + QTYPE_QLIST, + qlist_destroy_obj, }; /** diff --git a/qemu/qobject/qstring.c b/qemu/qobject/qstring.c index 607b7a14..542810a3 100644 --- a/qemu/qobject/qstring.c +++ b/qemu/qobject/qstring.c @@ -17,8 +17,8 @@ static void qstring_destroy_obj(QObject *obj); static const QType qstring_type = { - .code = QTYPE_QSTRING, - .destroy = qstring_destroy_obj, + QTYPE_QSTRING, + qstring_destroy_obj, }; /** diff --git a/qemu/qom/container.c b/qemu/qom/container.c index f311f995..131fa38f 100644 --- a/qemu/qom/container.c +++ b/qemu/qom/container.c @@ -15,9 +15,10 @@ #include static const TypeInfo container_info = { - .name = "container", - .instance_size = sizeof(Object), - .parent = TYPE_OBJECT, + "container", + TYPE_OBJECT, + 0, + sizeof(Object), }; void container_register_types(struct uc_struct *uc) diff --git a/qemu/qom/cpu.c b/qemu/qom/cpu.c index 57922b5f..a7cc20b7 100644 --- a/qemu/qom/cpu.c +++ b/qemu/qom/cpu.c @@ -89,7 +89,7 @@ void cpu_get_memory_mapping(CPUState *cpu, MemoryMappingList *list, { CPUClass *cc = CPU_GET_CLASS(cpu->uc, cpu); - return cc->get_memory_mapping(cpu, list, errp); + cc->get_memory_mapping(cpu, list, errp); } static void cpu_common_get_memory_mapping(CPUState *cpu, @@ -258,13 +258,24 @@ static void cpu_class_init(struct uc_struct *uc, ObjectClass *klass, void *data) } static const TypeInfo cpu_type_info = { - .name = TYPE_CPU, - .parent = TYPE_DEVICE, - .instance_size = sizeof(CPUState), - .instance_init = cpu_common_initfn, - .abstract = true, - .class_size = sizeof(CPUClass), - .class_init = cpu_class_init, + TYPE_CPU, + TYPE_DEVICE, + + sizeof(CPUClass), + sizeof(CPUState), + NULL, + + cpu_common_initfn, + NULL, + NULL, + + NULL, + + cpu_class_init, + NULL, + NULL, + + true, }; void cpu_register_types(struct uc_struct *uc) diff --git a/qemu/qom/object.c b/qemu/qom/object.c index 7731bd5f..1ab41da9 100644 --- a/qemu/qom/object.c +++ b/qemu/qom/object.c @@ -217,7 +217,7 @@ static void type_initialize_interface(struct uc_struct *uc, TypeImpl *ti, TypeIm TypeImpl *parent_type) { InterfaceClass *new_iface; - TypeInfo info = { }; + TypeInfo info = { 0 }; TypeImpl *iface_impl; info.parent = parent_type->name; @@ -252,9 +252,9 @@ static void type_initialize(struct uc_struct *uc, TypeImpl *ti) parent = type_get_parent(uc, ti); if (parent) { - type_initialize(uc, parent); GSList *e; int i; + type_initialize(uc, parent); g_assert(parent->class_size <= ti->class_size); memcpy(ti->class, parent->class, parent->class_size); @@ -1645,16 +1645,45 @@ static void object_instance_init(struct uc_struct *uc, Object *obj, void *opaque void register_types_object(struct uc_struct *uc) { static TypeInfo interface_info = { - .name = TYPE_INTERFACE, - .class_size = sizeof(InterfaceClass), - .abstract = true, + TYPE_INTERFACE, // name + NULL, + + sizeof(InterfaceClass), // class_size + 0, + NULL, + + NULL, + NULL, + NULL, + + NULL, + + NULL, + NULL, + NULL, + + true, // abstract }; static TypeInfo object_info = { - .name = TYPE_OBJECT, - .instance_size = sizeof(Object), - .instance_init = object_instance_init, - .abstract = true, + TYPE_OBJECT, + NULL, + + 0, + sizeof(Object), + NULL, + + object_instance_init, + NULL, + NULL, + + NULL, + + NULL, + NULL, + NULL, + + true, }; uc->type_interface = type_register_internal(uc, &interface_info); diff --git a/qemu/softmmu_template.h b/qemu/softmmu_template.h index 1f0adefb..a7373d57 100644 --- a/qemu/softmmu_template.h +++ b/qemu/softmmu_template.h @@ -1,26 +1,14 @@ -/* - * Software MMU support - * - * Generate helpers used by TCG for qemu_ld/st ops and code load - * functions. - * - * Included from target op helpers and exec.c. - * - * Copyright (c) 2003 Fabrice Bellard - * - * This library is free software; you can redistribute it and/or - * modify it under the terms of the GNU Lesser General Public - * License as published by the Free Software Foundation; either - * version 2 of the License, or (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU - * Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public - * License along with this library; if not, see . - */ +/* * Software MMU support * * Generate helpers used by TCG for qemu_ld/st ops +and code load * functions. * * Included from target op helpers and exec.c. * * +Copyright (c) 2003 Fabrice Bellard * * This library is free software; you can +redistribute it and/or * modify it under the terms of the GNU Lesser General +Public * License as published by the Free Software Foundation; either * version +2 of the License, or (at your option) any later version. * * This library is +distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; +without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A +PARTICULAR PURPOSE. See the GNU * Lesser General Public License for more +details. * * You should have received a copy of the GNU Lesser General Public * +License along with this library; if not, see . */ /* Modified for Unicorn Engine by Nguyen Anh Quynh, 2015 */ #include "qemu/timer.h" @@ -120,8 +108,7 @@ #endif /* macro to check the victim tlb */ -#define VICTIM_TLB_HIT(ty) \ -({ \ +#define VICTIM_TLB_HIT(ty) \ /* we are about to do a page table walk. our last hope is the \ * victim tlb. try to refill from the victim tlb before walking the \ * page table. */ \ @@ -141,8 +128,20 @@ } \ } \ /* return true when there is a vtlb hit, i.e. vidx >=0 */ \ - vidx >= 0; \ -}) + return (vidx >= 0) + +#ifndef victim_tlb_hit_funcs +#define victim_tlb_hit_funcs +static inline bool victim_tlb_hit_read(CPUArchState *env, target_ulong addr, int mmu_idx, int index) +{ + VICTIM_TLB_HIT(ADDR_READ); +} + +static inline bool victim_tlb_hit_write(CPUArchState *env, target_ulong addr, int mmu_idx, int index) +{ + VICTIM_TLB_HIT(addr_write); +} +#endif // victim_tlb_hit_funcs #ifndef SOFTMMU_CODE_ACCESS static inline DATA_TYPE glue(io_read, SUFFIX)(CPUArchState *env, @@ -163,12 +162,12 @@ static inline DATA_TYPE glue(io_read, SUFFIX)(CPUArchState *env, cpu->mem_io_vaddr = addr; io_mem_read(mr, physaddr, &val, 1 << SHIFT); - return val; + return (DATA_TYPE)val; } #endif #ifdef SOFTMMU_CODE_ACCESS -static __attribute__((unused)) +static QEMU_UNUSED_FUNC #endif WORD_TYPE helper_le_ld_name(CPUArchState *env, target_ulong addr, int mmu_idx, uintptr_t retaddr) @@ -180,6 +179,7 @@ WORD_TYPE helper_le_ld_name(CPUArchState *env, target_ulong addr, int mmu_idx, int error_code; struct hook *hook; bool handled; + HOOK_FOREACH_VAR_DECLARE; struct uc_struct *uc = env->uc; MemoryRegion *mr = memory_mapping(uc, addr); @@ -293,7 +293,7 @@ WORD_TYPE helper_le_ld_name(CPUArchState *env, target_ulong addr, int mmu_idx, return 0; } #endif - if (!VICTIM_TLB_HIT(ADDR_READ)) { + if (!victim_tlb_hit_read(env, addr, mmu_idx, index)) { tlb_fill(ENV_GET_CPU(env), addr, READ_ACCESS_TYPE, mmu_idx, retaddr); } @@ -373,7 +373,7 @@ WORD_TYPE helper_le_ld_name(CPUArchState *env, target_ulong addr, int mmu_idx, } #endif - haddr = addr + env->tlb_table[mmu_idx][index].addend; + haddr = (uintptr_t)(addr + env->tlb_table[mmu_idx][index].addend); #if DATA_SIZE == 1 res = glue(glue(ld, LSUFFIX), _p)((uint8_t *)haddr); #else @@ -395,7 +395,7 @@ _out: #if DATA_SIZE > 1 #ifdef SOFTMMU_CODE_ACCESS -static __attribute__((unused)) +static QEMU_UNUSED_FUNC #endif WORD_TYPE helper_be_ld_name(CPUArchState *env, target_ulong addr, int mmu_idx, uintptr_t retaddr) @@ -407,6 +407,7 @@ WORD_TYPE helper_be_ld_name(CPUArchState *env, target_ulong addr, int mmu_idx, int error_code; struct hook *hook; bool handled; + HOOK_FOREACH_VAR_DECLARE; struct uc_struct *uc = env->uc; MemoryRegion *mr = memory_mapping(uc, addr); @@ -520,7 +521,7 @@ WORD_TYPE helper_be_ld_name(CPUArchState *env, target_ulong addr, int mmu_idx, return 0; } #endif - if (!VICTIM_TLB_HIT(ADDR_READ)) { + if (!victim_tlb_hit_read(env, addr, mmu_idx, index)) { tlb_fill(ENV_GET_CPU(env), addr, READ_ACCESS_TYPE, mmu_idx, retaddr); } @@ -599,7 +600,7 @@ WORD_TYPE helper_be_ld_name(CPUArchState *env, target_ulong addr, int mmu_idx, } #endif - haddr = addr + env->tlb_table[mmu_idx][index].addend; + haddr = (uintptr_t)(addr + env->tlb_table[mmu_idx][index].addend); res = glue(glue(ld, LSUFFIX), _be_p)((uint8_t *)haddr); _out: @@ -671,6 +672,7 @@ void helper_le_st_name(CPUArchState *env, target_ulong addr, DATA_TYPE val, uintptr_t haddr; struct hook *hook; bool handled; + HOOK_FOREACH_VAR_DECLARE; struct uc_struct *uc = env->uc; MemoryRegion *mr = memory_mapping(uc, addr); @@ -742,7 +744,7 @@ void helper_le_st_name(CPUArchState *env, target_ulong addr, DATA_TYPE val, return; } #endif - if (!VICTIM_TLB_HIT(addr_write)) { + if (!victim_tlb_hit_write(env, addr, mmu_idx, index)) { tlb_fill(ENV_GET_CPU(env), addr, MMU_DATA_STORE, mmu_idx, retaddr); } tlb_addr = env->tlb_table[mmu_idx][index].addr_write; @@ -789,7 +791,7 @@ void helper_le_st_name(CPUArchState *env, target_ulong addr, DATA_TYPE val, * previous page from the TLB cache. */ for (i = DATA_SIZE - 1; i >= 0; i--) { /* Little-endian extract. */ - uint8_t val8 = val >> (i * 8); + uint8_t val8 = (uint8_t)(val >> (i * 8)); /* Note the adjustment at the beginning of the function. Undo that for the recursion. */ glue(helper_ret_stb, MMUSUFFIX)(env, addr + i, val8, @@ -812,7 +814,7 @@ void helper_le_st_name(CPUArchState *env, target_ulong addr, DATA_TYPE val, } #endif - haddr = addr + env->tlb_table[mmu_idx][index].addend; + haddr = (uintptr_t)(addr + env->tlb_table[mmu_idx][index].addend); #if DATA_SIZE == 1 glue(glue(st, SUFFIX), _p)((uint8_t *)haddr, val); #else @@ -829,6 +831,7 @@ void helper_be_st_name(CPUArchState *env, target_ulong addr, DATA_TYPE val, uintptr_t haddr; struct hook *hook; bool handled; + HOOK_FOREACH_VAR_DECLARE; struct uc_struct *uc = env->uc; MemoryRegion *mr = memory_mapping(uc, addr); @@ -900,7 +903,7 @@ void helper_be_st_name(CPUArchState *env, target_ulong addr, DATA_TYPE val, return; } #endif - if (!VICTIM_TLB_HIT(addr_write)) { + if (!victim_tlb_hit_write(env, addr, mmu_idx, index)) { tlb_fill(ENV_GET_CPU(env), addr, MMU_DATA_STORE, mmu_idx, retaddr); } tlb_addr = env->tlb_table[mmu_idx][index].addr_write; @@ -947,7 +950,7 @@ void helper_be_st_name(CPUArchState *env, target_ulong addr, DATA_TYPE val, * previous page from the TLB cache. */ for (i = DATA_SIZE - 1; i >= 0; i--) { /* Big-endian extract. */ - uint8_t val8 = val >> (((DATA_SIZE - 1) * 8) - (i * 8)); + uint8_t val8 = (uint8_t)(val >> (((DATA_SIZE - 1) * 8) - (i * 8))); /* Note the adjustment at the beginning of the function. Undo that for the recursion. */ glue(helper_ret_stb, MMUSUFFIX)(env, addr + i, val8, @@ -970,7 +973,7 @@ void helper_be_st_name(CPUArchState *env, target_ulong addr, DATA_TYPE val, } #endif - haddr = addr + env->tlb_table[mmu_idx][index].addend; + haddr = (uintptr_t)(addr + env->tlb_table[mmu_idx][index].addend); glue(glue(st, SUFFIX), _be_p)((uint8_t *)haddr, val); } #endif /* DATA_SIZE > 1 */ diff --git a/qemu/target-arm/arm-semi.c b/qemu/target-arm/arm-semi.c index f51cb69a..d8f3816f 100644 --- a/qemu/target-arm/arm-semi.c +++ b/qemu/target-arm/arm-semi.c @@ -21,7 +21,7 @@ #include #include #include -#include +#include "platform.h" #include #include #include diff --git a/qemu/target-arm/translate-a64.c b/qemu/target-arm/translate-a64.c index 11790a32..334b47a1 100644 --- a/qemu/target-arm/translate-a64.c +++ b/qemu/target-arm/translate-a64.c @@ -20,7 +20,7 @@ #include #include #include -#include +#include "platform.h" #include "cpu.h" #include "tcg-op.h" diff --git a/qemu/target-arm/translate.c b/qemu/target-arm/translate.c index 2ac5f47d..020bc717 100644 --- a/qemu/target-arm/translate.c +++ b/qemu/target-arm/translate.c @@ -23,7 +23,7 @@ #include #include #include -#include +#include "platform.h" #include "cpu.h" #include "internals.h" diff --git a/qemu/target-arm/unicorn.h b/qemu/target-arm/unicorn.h index d8a02505..cb32d4a5 100644 --- a/qemu/target-arm/unicorn.h +++ b/qemu/target-arm/unicorn.h @@ -13,10 +13,10 @@ int arm64_reg_write(struct uc_struct *uc, unsigned int *regs, void *const *vals, void arm_reg_reset(struct uc_struct *uc); void arm64_reg_reset(struct uc_struct *uc); -__attribute__ ((visibility ("default"))) +DEFAULT_VISIBILITY void arm_uc_init(struct uc_struct* uc); -__attribute__ ((visibility ("default"))) +DEFAULT_VISIBILITY void arm64_uc_init(struct uc_struct* uc); extern const int ARM_REGS_STORAGE_SIZE; diff --git a/qemu/target-arm/unicorn_aarch64.c b/qemu/target-arm/unicorn_aarch64.c index 9955b42e..3a5915a5 100644 --- a/qemu/target-arm/unicorn_aarch64.c +++ b/qemu/target-arm/unicorn_aarch64.c @@ -113,7 +113,7 @@ int arm64_reg_write(struct uc_struct *uc, unsigned int *regs, void* const* vals, return 0; } -__attribute__ ((visibility ("default"))) +DEFAULT_VISIBILITY void arm64_uc_init(struct uc_struct* uc) { register_accel_types(uc); diff --git a/qemu/target-i386/cc_helper.c b/qemu/target-i386/cc_helper.c index 2de54053..29e3c425 100644 --- a/qemu/target-i386/cc_helper.c +++ b/qemu/target-i386/cc_helper.c @@ -218,7 +218,7 @@ target_ulong helper_cc_compute_all(target_ulong dst, target_ulong src1, uint32_t cpu_cc_compute_all(CPUX86State *env, int op) { - return helper_cc_compute_all(CC_DST, CC_SRC, CC_SRC2, op); + return (uint32_t)helper_cc_compute_all(CC_DST, CC_SRC, CC_SRC2, op); } target_ulong helper_cc_compute_c(target_ulong dst, target_ulong src1, @@ -323,7 +323,7 @@ target_ulong helper_cc_compute_c(target_ulong dst, target_ulong src1, void helper_write_eflags(CPUX86State *env, target_ulong t0, uint32_t update_mask) { - cpu_load_eflags(env, t0, update_mask); + cpu_load_eflags(env, (int)t0, update_mask); } target_ulong helper_read_eflags(CPUX86State *env) diff --git a/qemu/target-i386/cc_helper_template.h b/qemu/target-i386/cc_helper_template.h index 607311f1..dc34d0d4 100644 --- a/qemu/target-i386/cc_helper_template.h +++ b/qemu/target-i386/cc_helper_template.h @@ -141,7 +141,7 @@ static int glue(compute_all_inc, SUFFIX)(DATA_TYPE dst, DATA_TYPE src1) int cf, pf, af, zf, sf, of; DATA_TYPE src2; - cf = src1; + cf = (int)src1; src1 = dst - 1; src2 = 1; pf = parity_table[(uint8_t)dst]; @@ -157,7 +157,7 @@ static int glue(compute_all_dec, SUFFIX)(DATA_TYPE dst, DATA_TYPE src1) int cf, pf, af, zf, sf, of; DATA_TYPE src2; - cf = src1; + cf = (int)src1; src1 = dst + 1; src2 = 1; pf = parity_table[(uint8_t)dst]; diff --git a/qemu/target-i386/cpu.c b/qemu/target-i386/cpu.c index 41e6ca7a..bb966d62 100644 --- a/qemu/target-i386/cpu.c +++ b/qemu/target-i386/cpu.c @@ -19,7 +19,7 @@ #include #include #include -#include +#include "platform.h" #include "cpu.h" #include "sysemu/cpus.h" @@ -309,7 +309,70 @@ typedef struct FeatureWordInfo { } FeatureWordInfo; static FeatureWordInfo feature_word_info[FEATURE_WORDS] = { - [FEAT_1_EDX] = { +#ifdef _MSC_VER + // FEAT_1_EDX + { + feature_name, + 1, + false,0, + R_EDX, + TCG_FEATURES, + }, + // FEAT_1_ECX + { + ext_feature_name, + 1, + false,0, + R_ECX, + TCG_EXT_FEATURES, + }, + // FEAT_7_0_EBX + { + cpuid_7_0_ebx_feature_name, + 7, + true, 0, + R_EBX, + TCG_7_0_EBX_FEATURES, + }, + // FEAT_8000_0001_EDX + { + ext2_feature_name, + 0x80000001, + false,0, + R_EDX, + TCG_EXT2_FEATURES, + }, + // FEAT_8000_0001_ECX + { + ext3_feature_name, + 0x80000001, + false,0, + R_ECX, + TCG_EXT3_FEATURES, + }, + // FEAT_8000_0007_EDX + { + cpuid_apm_edx_feature_name, + 0x80000007, + false,0, + R_EDX, + TCG_APM_FEATURES, + CPUID_APM_INVTSC, + }, + // FEAT_C000_0001_EDX + { + ext4_feature_name, + 0xC0000001, + false,0, + R_EDX, + TCG_EXT4_FEATURES, + }, + // FEAT_KVM + {0}, + // FEAT_SVM + {0}, +#else + [FEAT_1_EDX] = { .feat_names = feature_name, .cpuid_eax = 1, .cpuid_reg = R_EDX, .tcg_features = TCG_FEATURES, @@ -348,6 +411,7 @@ static FeatureWordInfo feature_word_info[FEATURE_WORDS] = { .tcg_features = TCG_APM_FEATURES, .unmigratable_flags = CPUID_APM_INVTSC, }, +#endif }; typedef struct X86RegisterInfo32 { @@ -358,7 +422,7 @@ typedef struct X86RegisterInfo32 { } X86RegisterInfo32; #define REGISTER(reg) \ - [R_##reg] = { .name = #reg, .qapi_enum = X86_CPU_REGISTER32_##reg } + { #reg, X86_CPU_REGISTER32_##reg } static const X86RegisterInfo32 x86_reg_info_32[CPU_NB_REGS32] = { REGISTER(EAX), REGISTER(ECX), @@ -384,11 +448,18 @@ const char *get_register_name_32(unsigned int reg) return x86_reg_info_32[reg].name; } +#ifdef _MSC_VER +#include +#endif + void host_cpuid(uint32_t function, uint32_t count, uint32_t *eax, uint32_t *ebx, uint32_t *ecx, uint32_t *edx) { uint32_t vec[4]; +#ifdef _MSC_VER + __cpuidex((int*)vec, function, count); +#else #ifdef __x86_64__ asm volatile("cpuid" : "=a"(vec[0]), "=b"(vec[1]), @@ -407,6 +478,7 @@ void host_cpuid(uint32_t function, uint32_t count, #else abort(); #endif +#endif // _MSC_VER if (eax) *eax = vec[0]; @@ -543,477 +615,493 @@ struct X86CPUDefinition { static X86CPUDefinition builtin_x86_defs[] = { { - .name = "qemu64", - .level = 4, - .vendor = CPUID_VENDOR_AMD, - .family = 6, - .model = 6, - .stepping = 3, - .features[FEAT_1_EDX] = + "qemu64", + 4, 0x8000000A, 0, + CPUID_VENDOR_AMD, + 6, 6, 3, + { + // FEAT_1_EDX PPRO_FEATURES | CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_PSE36, - .features[FEAT_1_ECX] = + // FEAT_1_ECX CPUID_EXT_SSE3 | CPUID_EXT_CX16 | CPUID_EXT_POPCNT, - .features[FEAT_8000_0001_EDX] = + // FEAT_7_0_EBX + 0, + // FEAT_8000_0001_EDX (PPRO_FEATURES & CPUID_EXT2_AMD_ALIASES) | CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX, - .features[FEAT_8000_0001_ECX] = + // FEAT_8000_0001_ECX CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM | CPUID_EXT3_ABM | CPUID_EXT3_SSE4A, - .xlevel = 0x8000000A, + }, }, { - .name = "phenom", - .level = 5, - .vendor = CPUID_VENDOR_AMD, - .family = 16, - .model = 2, - .stepping = 3, - /* Missing: CPUID_HT */ - .features[FEAT_1_EDX] = + "phenom", + 5, 0x8000001A, 0, + CPUID_VENDOR_AMD, + 16, 2, 3, + { + /* Missing: CPUID_HT */ + // FEAT_1_EDX PPRO_FEATURES | CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_PSE36 | CPUID_VME, - .features[FEAT_1_ECX] = + // FEAT_1_ECX CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_CX16 | CPUID_EXT_POPCNT, - .features[FEAT_8000_0001_EDX] = + // FEAT_7_0_EBX + 0, + // FEAT_8000_0001_EDX (PPRO_FEATURES & CPUID_EXT2_AMD_ALIASES) | CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX | CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT | CPUID_EXT2_MMXEXT | CPUID_EXT2_FFXSR | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP, - /* Missing: CPUID_EXT3_CMP_LEG, CPUID_EXT3_EXTAPIC, - CPUID_EXT3_CR8LEG, - CPUID_EXT3_MISALIGNSSE, CPUID_EXT3_3DNOWPREFETCH, - CPUID_EXT3_OSVW, CPUID_EXT3_IBS */ - .features[FEAT_8000_0001_ECX] = + /* Missing: CPUID_EXT3_CMP_LEG, CPUID_EXT3_EXTAPIC, + CPUID_EXT3_CR8LEG, + CPUID_EXT3_MISALIGNSSE, CPUID_EXT3_3DNOWPREFETCH, + CPUID_EXT3_OSVW, CPUID_EXT3_IBS */ + // FEAT_8000_0001_ECX CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM | CPUID_EXT3_ABM | CPUID_EXT3_SSE4A, - /* Missing: CPUID_SVM_LBRV */ - .features[FEAT_SVM] = + // FEAT_8000_0007_EDX + 0, + // FEAT_C000_0001_EDX + 0, + // FEAT_KVM + 0, + /* Missing: CPUID_SVM_LBRV */ + // FEAT_SVM CPUID_SVM_NPT, - .xlevel = 0x8000001A, - .model_id = "AMD Phenom(tm) 9550 Quad-Core Processor" + }, + "AMD Phenom(tm) 9550 Quad-Core Processor", }, { - .name = "core2duo", - .level = 10, - .vendor = CPUID_VENDOR_INTEL, - .family = 6, - .model = 15, - .stepping = 11, + "core2duo", + 10, 0x80000008, 0, + CPUID_VENDOR_INTEL, + 6, 15, 11, + { /* Missing: CPUID_DTS, CPUID_HT, CPUID_TM, CPUID_PBE */ - .features[FEAT_1_EDX] = + // FEAT_1_EDX PPRO_FEATURES | CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_PSE36 | CPUID_VME | CPUID_ACPI | CPUID_SS, /* Missing: CPUID_EXT_DTES64, CPUID_EXT_DSCPL, CPUID_EXT_EST, * CPUID_EXT_TM2, CPUID_EXT_XTPR, CPUID_EXT_PDCM, CPUID_EXT_VMX */ - .features[FEAT_1_ECX] = + // FEAT_1_ECX CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 | CPUID_EXT_CX16, - .features[FEAT_8000_0001_EDX] = + // FEAT_7_0_EBX + 0, + // FEAT_8000_0001_EDX CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX, - .features[FEAT_8000_0001_ECX] = + // FEAT_8000_0001_ECX CPUID_EXT3_LAHF_LM, - .xlevel = 0x80000008, - .model_id = "Intel(R) Core(TM)2 Duo CPU T7700 @ 2.40GHz", + }, + "Intel(R) Core(TM)2 Duo CPU T7700 @ 2.40GHz", }, { - .name = "kvm64", - .level = 5, - .vendor = CPUID_VENDOR_INTEL, - .family = 15, - .model = 6, - .stepping = 1, + "kvm64", + 5, 0x80000008, 0, + CPUID_VENDOR_INTEL, + 15, 6, 1, + { /* Missing: CPUID_VME, CPUID_HT */ - .features[FEAT_1_EDX] = + // FEAT_1_EDX PPRO_FEATURES | CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_PSE36, /* Missing: CPUID_EXT_POPCNT, CPUID_EXT_MONITOR */ - .features[FEAT_1_ECX] = + // FEAT_1_ECX CPUID_EXT_SSE3 | CPUID_EXT_CX16, + // FEAT_7_0_EBX + 0, /* Missing: CPUID_EXT2_PDPE1GB, CPUID_EXT2_RDTSCP */ - .features[FEAT_8000_0001_EDX] = + // FEAT_8000_0001_EDX (PPRO_FEATURES & CPUID_EXT2_AMD_ALIASES) | CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX, /* Missing: CPUID_EXT3_LAHF_LM, CPUID_EXT3_CMP_LEG, CPUID_EXT3_EXTAPIC, CPUID_EXT3_CR8LEG, CPUID_EXT3_ABM, CPUID_EXT3_SSE4A, CPUID_EXT3_MISALIGNSSE, CPUID_EXT3_3DNOWPREFETCH, CPUID_EXT3_OSVW, CPUID_EXT3_IBS, CPUID_EXT3_SVM */ - .features[FEAT_8000_0001_ECX] = + // FEAT_8000_0001_ECX 0, - .xlevel = 0x80000008, - .model_id = "Common KVM processor" + }, + "Common KVM processor", }, { - .name = "qemu32", - .level = 4, - .vendor = CPUID_VENDOR_INTEL, - .family = 6, - .model = 6, - .stepping = 3, - .features[FEAT_1_EDX] = + "qemu32", + 4, 0x80000004, 0, + CPUID_VENDOR_INTEL, + 6, 6, 3, + { + // FEAT_1_EDX PPRO_FEATURES, - .features[FEAT_1_ECX] = + // FEAT_1_ECX CPUID_EXT_SSE3 | CPUID_EXT_POPCNT, - .xlevel = 0x80000004, + }, }, { - .name = "kvm32", - .level = 5, - .vendor = CPUID_VENDOR_INTEL, - .family = 15, - .model = 6, - .stepping = 1, - .features[FEAT_1_EDX] = + "kvm32", + 5, 0x80000008, 0, + CPUID_VENDOR_INTEL, + 15, 6, 1, + { + // FEAT_1_EDX PPRO_FEATURES | CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_PSE36, - .features[FEAT_1_ECX] = + // FEAT_1_ECX CPUID_EXT_SSE3, - .features[FEAT_8000_0001_EDX] = + // FEAT_7_0_EBX + 0, + // FEAT_8000_0001_EDX PPRO_FEATURES & CPUID_EXT2_AMD_ALIASES, - .features[FEAT_8000_0001_ECX] = + // FEAT_8000_0001_ECX 0, - .xlevel = 0x80000008, - .model_id = "Common 32-bit KVM processor" + }, + "Common 32-bit KVM processor", }, { - .name = "coreduo", - .level = 10, - .vendor = CPUID_VENDOR_INTEL, - .family = 6, - .model = 14, - .stepping = 8, + "coreduo", + 10, 0x80000008, 0, + CPUID_VENDOR_INTEL, + 6, 14, 8, + { /* Missing: CPUID_DTS, CPUID_HT, CPUID_TM, CPUID_PBE */ - .features[FEAT_1_EDX] = + // FEAT_1_EDX PPRO_FEATURES | CPUID_VME | CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_ACPI | CPUID_SS, /* Missing: CPUID_EXT_EST, CPUID_EXT_TM2 , CPUID_EXT_XTPR, * CPUID_EXT_PDCM, CPUID_EXT_VMX */ - .features[FEAT_1_ECX] = + // FEAT_1_ECX CPUID_EXT_SSE3 | CPUID_EXT_MONITOR, - .features[FEAT_8000_0001_EDX] = + // FEAT_7_0_EBX + 0, + // FEAT_8000_0001_EDX CPUID_EXT2_NX, - .xlevel = 0x80000008, - .model_id = "Genuine Intel(R) CPU T2600 @ 2.16GHz", + }, + "Genuine Intel(R) CPU T2600 @ 2.16GHz", }, { - .name = "486", - .level = 1, - .vendor = CPUID_VENDOR_INTEL, - .family = 4, - .model = 8, - .stepping = 0, - .features[FEAT_1_EDX] = + "486", + 1, 0, 0, + CPUID_VENDOR_INTEL, + 4, 8, 0, + { + // FEAT_1_EDX I486_FEATURES, - .xlevel = 0, + }, }, { - .name = "pentium", - .level = 1, - .vendor = CPUID_VENDOR_INTEL, - .family = 5, - .model = 4, - .stepping = 3, - .features[FEAT_1_EDX] = + "pentium", + 1, 0, 0, + CPUID_VENDOR_INTEL, + 5, 4, 3, + { + // FEAT_1_EDX PENTIUM_FEATURES, - .xlevel = 0, + }, }, { - .name = "pentium2", - .level = 2, - .vendor = CPUID_VENDOR_INTEL, - .family = 6, - .model = 5, - .stepping = 2, - .features[FEAT_1_EDX] = + "pentium2", + 2, 0, 0, + CPUID_VENDOR_INTEL, + 6, 5, 2, + { + // FEAT_1_EDX PENTIUM2_FEATURES, - .xlevel = 0, + }, }, { - .name = "pentium3", - .level = 2, - .vendor = CPUID_VENDOR_INTEL, - .family = 6, - .model = 7, - .stepping = 3, - .features[FEAT_1_EDX] = + "pentium3", + 2, 0, 0, + CPUID_VENDOR_INTEL, + 6, 7, 3, + { + // FEAT_1_EDX PENTIUM3_FEATURES, - .xlevel = 0, + }, }, { - .name = "athlon", - .level = 2, - .vendor = CPUID_VENDOR_AMD, - .family = 6, - .model = 2, - .stepping = 3, - .features[FEAT_1_EDX] = + "athlon", + 2, 0x80000008, 0, + CPUID_VENDOR_AMD, + 6, 2, 3, + { + // FEAT_1_EDX PPRO_FEATURES | CPUID_PSE36 | CPUID_VME | CPUID_MTRR | CPUID_MCA, - .features[FEAT_8000_0001_EDX] = + // FEAT_1_ECX + 0, + // FEAT_7_0_EBX + 0, + // FEAT_8000_0001_EDX (PPRO_FEATURES & CPUID_EXT2_AMD_ALIASES) | CPUID_EXT2_MMXEXT | CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT, - .xlevel = 0x80000008, + }, }, { - .name = "n270", + "n270", /* original is on level 10 */ - .level = 5, - .vendor = CPUID_VENDOR_INTEL, - .family = 6, - .model = 28, - .stepping = 2, + 5, 0x8000000A, 0, + CPUID_VENDOR_INTEL, + 6, 28, 2, + { /* Missing: CPUID_DTS, CPUID_HT, CPUID_TM, CPUID_PBE */ - .features[FEAT_1_EDX] = + // FEAT_1_EDX PPRO_FEATURES | CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_VME | CPUID_ACPI | CPUID_SS, /* Some CPUs got no CPUID_SEP */ /* Missing: CPUID_EXT_DSCPL, CPUID_EXT_EST, CPUID_EXT_TM2, * CPUID_EXT_XTPR */ - .features[FEAT_1_ECX] = + // FEAT_1_ECX CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 | CPUID_EXT_MOVBE, - .features[FEAT_8000_0001_EDX] = + // FEAT_7_0_EBX + 0, + // FEAT_8000_0001_EDX (PPRO_FEATURES & CPUID_EXT2_AMD_ALIASES) | CPUID_EXT2_NX, - .features[FEAT_8000_0001_ECX] = + // FEAT_8000_0001_ECX CPUID_EXT3_LAHF_LM, - .xlevel = 0x8000000A, - .model_id = "Intel(R) Atom(TM) CPU N270 @ 1.60GHz", + }, + "Intel(R) Atom(TM) CPU N270 @ 1.60GHz", }, { - .name = "Conroe", - .level = 4, - .vendor = CPUID_VENDOR_INTEL, - .family = 6, - .model = 15, - .stepping = 3, - .features[FEAT_1_EDX] = + "Conroe", + 4, 0x8000000A, 0, + CPUID_VENDOR_INTEL, + 6, 15, 3, + { + // FEAT_1_EDX CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | CPUID_DE | CPUID_FP87, - .features[FEAT_1_ECX] = + // FEAT_1_ECX CPUID_EXT_SSSE3 | CPUID_EXT_SSE3, - .features[FEAT_8000_0001_EDX] = + // FEAT_7_0_EBX + 0, + // FEAT_8000_0001_EDX CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL, - .features[FEAT_8000_0001_ECX] = + // FEAT_8000_0001_ECX CPUID_EXT3_LAHF_LM, - .xlevel = 0x8000000A, - .model_id = "Intel Celeron_4x0 (Conroe/Merom Class Core 2)", + }, + "Intel Celeron_4x0 (Conroe/Merom Class Core 2)", }, { - .name = "Penryn", - .level = 4, - .vendor = CPUID_VENDOR_INTEL, - .family = 6, - .model = 23, - .stepping = 3, - .features[FEAT_1_EDX] = + "Penryn", + 4, 0x8000000A, 0, + CPUID_VENDOR_INTEL, + 6, 23, 3, + { + // FEAT_1_EDX CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | CPUID_DE | CPUID_FP87, - .features[FEAT_1_ECX] = + // FEAT_1_ECX CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_SSE3, - .features[FEAT_8000_0001_EDX] = + // FEAT_7_0_EBX + 0, + // FEAT_8000_0001_EDX CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL, - .features[FEAT_8000_0001_ECX] = + // FEAT_8000_0001_ECX CPUID_EXT3_LAHF_LM, - .xlevel = 0x8000000A, - .model_id = "Intel Core 2 Duo P9xxx (Penryn Class Core 2)", + }, + "Intel Core 2 Duo P9xxx (Penryn Class Core 2)", }, { - .name = "Nehalem", - .level = 4, - .vendor = CPUID_VENDOR_INTEL, - .family = 6, - .model = 26, - .stepping = 3, - .features[FEAT_1_EDX] = + "Nehalem", + 4, 0x8000000A, 0, + CPUID_VENDOR_INTEL, + 6, 26, 3, + { + // FEAT_1_EDX CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | CPUID_DE | CPUID_FP87, - .features[FEAT_1_ECX] = + // FEAT_1_ECX CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_SSE3, - .features[FEAT_8000_0001_EDX] = + // FEAT_7_0_EBX + 0, + // FEAT_8000_0001_EDX CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX, - .features[FEAT_8000_0001_ECX] = + // FEAT_8000_0001_ECX CPUID_EXT3_LAHF_LM, - .xlevel = 0x8000000A, - .model_id = "Intel Core i7 9xx (Nehalem Class Core i7)", + }, + "Intel Core i7 9xx (Nehalem Class Core i7)", }, { - .name = "Westmere", - .level = 11, - .vendor = CPUID_VENDOR_INTEL, - .family = 6, - .model = 44, - .stepping = 1, - .features[FEAT_1_EDX] = + "Westmere", + 11, 0x8000000A, 0, + CPUID_VENDOR_INTEL, + 6, 44, 1, + { + // FEAT_1_EDX CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | CPUID_DE | CPUID_FP87, - .features[FEAT_1_ECX] = + // FEAT_1_ECX CPUID_EXT_AES | CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3, - .features[FEAT_8000_0001_EDX] = + // FEAT_7_0_EBX + 0, + // FEAT_8000_0001_EDX CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX, - .features[FEAT_8000_0001_ECX] = + // FEAT_8000_0001_ECX CPUID_EXT3_LAHF_LM, - .xlevel = 0x8000000A, - .model_id = "Westmere E56xx/L56xx/X56xx (Nehalem-C)", + }, + "Westmere E56xx/L56xx/X56xx (Nehalem-C)", }, { - .name = "SandyBridge", - .level = 0xd, - .vendor = CPUID_VENDOR_INTEL, - .family = 6, - .model = 42, - .stepping = 1, - .features[FEAT_1_EDX] = + "SandyBridge", + 0xd, 0x8000000A, 0, + CPUID_VENDOR_INTEL, + 6, 42, 1, + { + // FEAT_1_EDX CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | CPUID_DE | CPUID_FP87, - .features[FEAT_1_ECX] = + // FEAT_1_ECX CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES | CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3, - .features[FEAT_8000_0001_EDX] = + // FEAT_7_0_EBX + 0, + // FEAT_8000_0001_EDX CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL, - .features[FEAT_8000_0001_ECX] = + // FEAT_8000_0001_ECX CPUID_EXT3_LAHF_LM, - .xlevel = 0x8000000A, - .model_id = "Intel Xeon E312xx (Sandy Bridge)", + }, + "Intel Xeon E312xx (Sandy Bridge)", }, { - .name = "Haswell", - .level = 0xd, - .vendor = CPUID_VENDOR_INTEL, - .family = 6, - .model = 60, - .stepping = 1, - .features[FEAT_1_EDX] = + "Haswell", + 0xd, 0x8000000A, 0, + CPUID_VENDOR_INTEL, + 6, 60, 1, + { + // FEAT_1_EDX CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | CPUID_DE | CPUID_FP87, - .features[FEAT_1_ECX] = + // FEAT_1_ECX CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES | CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 | CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE | CPUID_EXT_PCID, - .features[FEAT_8000_0001_EDX] = - CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX | - CPUID_EXT2_SYSCALL, - .features[FEAT_8000_0001_ECX] = - CPUID_EXT3_LAHF_LM, - .features[FEAT_7_0_EBX] = + // FEAT_7_0_EBX CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID | CPUID_7_0_EBX_RTM, - .xlevel = 0x8000000A, - .model_id = "Intel Core Processor (Haswell)", + // FEAT_8000_0001_EDX + CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX | + CPUID_EXT2_SYSCALL, + // FEAT_8000_0001_ECX + CPUID_EXT3_LAHF_LM, + }, + "Intel Core Processor (Haswell)", }, { - .name = "Broadwell", - .level = 0xd, - .vendor = CPUID_VENDOR_INTEL, - .family = 6, - .model = 61, - .stepping = 2, - .features[FEAT_1_EDX] = + "Broadwell", + 0xd, 0x8000000A, 0, + CPUID_VENDOR_INTEL, + 6, 61, 2, + { + // FEAT_1_EDX CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | CPUID_DE | CPUID_FP87, - .features[FEAT_1_ECX] = + // FEAT_1_ECX CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES | CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 | CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE | CPUID_EXT_PCID, - .features[FEAT_8000_0001_EDX] = - CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX | - CPUID_EXT2_SYSCALL, - .features[FEAT_8000_0001_ECX] = - CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH, - .features[FEAT_7_0_EBX] = + // FEAT_7_0_EBX CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID | CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX | CPUID_7_0_EBX_SMAP, - .xlevel = 0x8000000A, - .model_id = "Intel Core Processor (Broadwell)", + // FEAT_8000_0001_EDX + CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX | + CPUID_EXT2_SYSCALL, + // FEAT_8000_0001_ECX + CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH, + }, + "Intel Core Processor (Broadwell)", }, { - .name = "Opteron_G1", - .level = 5, - .vendor = CPUID_VENDOR_AMD, - .family = 15, - .model = 6, - .stepping = 1, - .features[FEAT_1_EDX] = + "Opteron_G1", + 5, 0x80000008, 0, + CPUID_VENDOR_AMD, + 15, 6, 1, + { + // FEAT_1_EDX CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | CPUID_DE | CPUID_FP87, - .features[FEAT_1_ECX] = + // FEAT_1_ECX CPUID_EXT_SSE3, - .features[FEAT_8000_0001_EDX] = + // FEAT_7_0_EBX + 0, + // FEAT_8000_0001_EDX CPUID_EXT2_LM | CPUID_EXT2_FXSR | CPUID_EXT2_MMX | CPUID_EXT2_NX | CPUID_EXT2_PSE36 | CPUID_EXT2_PAT | CPUID_EXT2_CMOV | CPUID_EXT2_MCA | CPUID_EXT2_PGE | CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL | CPUID_EXT2_APIC | CPUID_EXT2_CX8 | CPUID_EXT2_MCE | CPUID_EXT2_PAE | CPUID_EXT2_MSR | CPUID_EXT2_TSC | CPUID_EXT2_PSE | CPUID_EXT2_DE | CPUID_EXT2_FPU, - .xlevel = 0x80000008, - .model_id = "AMD Opteron 240 (Gen 1 Class Opteron)", + }, + "AMD Opteron 240 (Gen 1 Class Opteron)", }, { - .name = "Opteron_G2", - .level = 5, - .vendor = CPUID_VENDOR_AMD, - .family = 15, - .model = 6, - .stepping = 1, - .features[FEAT_1_EDX] = + "Opteron_G2", + 5, 0x80000008, 0, + CPUID_VENDOR_AMD, + 15, 6, 1, + { + // FEAT_1_EDX CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | CPUID_DE | CPUID_FP87, - .features[FEAT_1_ECX] = + // FEAT_1_ECX CPUID_EXT_CX16 | CPUID_EXT_SSE3, - .features[FEAT_8000_0001_EDX] = + // FEAT_7_0_EBX + 0, + // FEAT_8000_0001_EDX CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_FXSR | CPUID_EXT2_MMX | CPUID_EXT2_NX | CPUID_EXT2_PSE36 | CPUID_EXT2_PAT | CPUID_EXT2_CMOV | CPUID_EXT2_MCA | @@ -1021,28 +1109,29 @@ static X86CPUDefinition builtin_x86_defs[] = { CPUID_EXT2_APIC | CPUID_EXT2_CX8 | CPUID_EXT2_MCE | CPUID_EXT2_PAE | CPUID_EXT2_MSR | CPUID_EXT2_TSC | CPUID_EXT2_PSE | CPUID_EXT2_DE | CPUID_EXT2_FPU, - .features[FEAT_8000_0001_ECX] = + // FEAT_8000_0001_ECX CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM, - .xlevel = 0x80000008, - .model_id = "AMD Opteron 22xx (Gen 2 Class Opteron)", + }, + "AMD Opteron 22xx (Gen 2 Class Opteron)", }, { - .name = "Opteron_G3", - .level = 5, - .vendor = CPUID_VENDOR_AMD, - .family = 15, - .model = 6, - .stepping = 1, - .features[FEAT_1_EDX] = + "Opteron_G3", + 5, 0x80000008, 0, + CPUID_VENDOR_AMD, + 15, 6, 1, + { + // FEAT_1_EDX CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | CPUID_DE | CPUID_FP87, - .features[FEAT_1_ECX] = + // FEAT_1_ECX CPUID_EXT_POPCNT | CPUID_EXT_CX16 | CPUID_EXT_MONITOR | CPUID_EXT_SSE3, - .features[FEAT_8000_0001_EDX] = + // FEAT_7_0_EBX + 0, + // FEAT_8000_0001_EDX CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_FXSR | CPUID_EXT2_MMX | CPUID_EXT2_NX | CPUID_EXT2_PSE36 | CPUID_EXT2_PAT | CPUID_EXT2_CMOV | CPUID_EXT2_MCA | @@ -1050,31 +1139,32 @@ static X86CPUDefinition builtin_x86_defs[] = { CPUID_EXT2_APIC | CPUID_EXT2_CX8 | CPUID_EXT2_MCE | CPUID_EXT2_PAE | CPUID_EXT2_MSR | CPUID_EXT2_TSC | CPUID_EXT2_PSE | CPUID_EXT2_DE | CPUID_EXT2_FPU, - .features[FEAT_8000_0001_ECX] = + // FEAT_8000_0001_ECX CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM, - .xlevel = 0x80000008, - .model_id = "AMD Opteron 23xx (Gen 3 Class Opteron)", + }, + "AMD Opteron 23xx (Gen 3 Class Opteron)", }, { - .name = "Opteron_G4", - .level = 0xd, - .vendor = CPUID_VENDOR_AMD, - .family = 21, - .model = 1, - .stepping = 2, - .features[FEAT_1_EDX] = + "Opteron_G4", + 0xd, 0x8000001A, 0, + CPUID_VENDOR_AMD, + 21, 1, 2, + { + // FEAT_1_EDX CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | CPUID_DE | CPUID_FP87, - .features[FEAT_1_ECX] = + // FEAT_1_ECX CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES | CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3, - .features[FEAT_8000_0001_EDX] = + // FEAT_7_0_EBX + 0, + // FEAT_8000_0001_EDX CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_PDPE1GB | CPUID_EXT2_FXSR | CPUID_EXT2_MMX | CPUID_EXT2_NX | CPUID_EXT2_PSE36 | CPUID_EXT2_PAT | @@ -1082,33 +1172,34 @@ static X86CPUDefinition builtin_x86_defs[] = { CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL | CPUID_EXT2_APIC | CPUID_EXT2_CX8 | CPUID_EXT2_MCE | CPUID_EXT2_PAE | CPUID_EXT2_MSR | CPUID_EXT2_TSC | CPUID_EXT2_PSE | CPUID_EXT2_DE | CPUID_EXT2_FPU, - .features[FEAT_8000_0001_ECX] = + // FEAT_8000_0001_ECX CPUID_EXT3_FMA4 | CPUID_EXT3_XOP | CPUID_EXT3_3DNOWPREFETCH | CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM, - .xlevel = 0x8000001A, - .model_id = "AMD Opteron 62xx class CPU", + }, + "AMD Opteron 62xx class CPU", }, { - .name = "Opteron_G5", - .level = 0xd, - .vendor = CPUID_VENDOR_AMD, - .family = 21, - .model = 2, - .stepping = 0, - .features[FEAT_1_EDX] = + "Opteron_G5", + 0xd, 0x8000001A, 0, + CPUID_VENDOR_AMD, + 21, 2, 0, + { + // FEAT_1_EDX CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | CPUID_DE | CPUID_FP87, - .features[FEAT_1_ECX] = + // FEAT_1_ECX CPUID_EXT_F16C | CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES | CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_FMA | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3, - .features[FEAT_8000_0001_EDX] = + // FEAT_7_0_EBX + 0, + // FEAT_8000_0001_EDX CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_PDPE1GB | CPUID_EXT2_FXSR | CPUID_EXT2_MMX | CPUID_EXT2_NX | CPUID_EXT2_PSE36 | CPUID_EXT2_PAT | @@ -1116,13 +1207,13 @@ static X86CPUDefinition builtin_x86_defs[] = { CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL | CPUID_EXT2_APIC | CPUID_EXT2_CX8 | CPUID_EXT2_MCE | CPUID_EXT2_PAE | CPUID_EXT2_MSR | CPUID_EXT2_TSC | CPUID_EXT2_PSE | CPUID_EXT2_DE | CPUID_EXT2_FPU, - .features[FEAT_8000_0001_ECX] = + // FEAT_8000_0001_ECX CPUID_EXT3_TBM | CPUID_EXT3_FMA4 | CPUID_EXT3_XOP | CPUID_EXT3_3DNOWPREFETCH | CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM, - .xlevel = 0x8000001A, - .model_id = "AMD Opteron 63xx class CPU", + }, + "AMD Opteron 63xx class CPU", }, }; @@ -1413,7 +1504,7 @@ static int x86_cpuid_set_tsc_freq(struct uc_struct *uc, Object *obj, Visitor *v, return -1; } - cpu->env.tsc_khz = value / 1000; + cpu->env.tsc_khz = (int)(value / 1000); return 0; } @@ -1459,7 +1550,7 @@ static int x86_cpuid_set_apic_id(struct uc_struct *uc, Object *obj, Visitor *v, error_setg(errp, "CPU with APIC ID %" PRIi64 " exists", value); return -1; } - cpu->env.cpuid_apic_id = value; + cpu->env.cpuid_apic_id = (uint32_t)value; return 0; } @@ -1471,8 +1562,8 @@ static void x86_cpu_get_feature_words(struct uc_struct *uc, Object *obj, Visitor uint32_t *array = (uint32_t *)opaque; FeatureWord w; Error *err = NULL; - X86CPUFeatureWordInfo word_infos[FEATURE_WORDS] = { }; - X86CPUFeatureWordInfoList list_entries[FEATURE_WORDS] = { }; + X86CPUFeatureWordInfo word_infos[FEATURE_WORDS] = { 0 }; + X86CPUFeatureWordInfoList list_entries[FEATURE_WORDS] = { 0 }; X86CPUFeatureWordInfoList *list = NULL; for (w = 0; w < FEATURE_WORDS; w++) { @@ -1568,7 +1659,7 @@ static void x86_cpu_parse_featurestr(CPUState *cs, char *features, error_setg(errp, "bad numerical value %s", val); return; } - if (numvalue < min) { + if (numvalue < (uint32_t)min) { numvalue = min; } snprintf(num, sizeof(num), "%" PRId32, numvalue); @@ -1748,10 +1839,20 @@ static void x86_register_cpudef_type(struct uc_struct *uc, X86CPUDefinition *def { char *typename = x86_cpu_type_name(def->name); TypeInfo ti = { - .name = typename, - .parent = TYPE_X86_CPU, - .class_init = x86_cpu_cpudef_class_init, - .class_data = def, + typename, + TYPE_X86_CPU, + + 0, + 0, + NULL, + + NULL, + NULL, + NULL, + + def, + + x86_cpu_cpudef_class_init, }; type_register(uc, &ti); @@ -2198,7 +2299,7 @@ static void x86_cpu_reset(CPUState *s) #ifndef CONFIG_USER_ONLY bool cpu_is_bsp(X86CPU *cpu) { - return cpu_get_apic_base((&cpu->env)->uc, cpu->apic_state) & MSR_IA32_APICBASE_BSP; + return (cpu_get_apic_base((&cpu->env)->uc, cpu->apic_state) & MSR_IA32_APICBASE_BSP) != 0; } #endif @@ -2422,7 +2523,7 @@ static bool x86_cpu_get_paging_enabled(const CPUState *cs) { X86CPU *cpu = X86_CPU(cs->uc, cs); - return cpu->env.cr[0] & CR0_PG_MASK; + return (cpu->env.cr[0] & CR0_PG_MASK) != 0; } static void x86_cpu_set_pc(CPUState *cs, vaddr value) @@ -2500,14 +2601,24 @@ static void x86_cpu_common_class_init(struct uc_struct *uc, ObjectClass *oc, voi void x86_cpu_register_types(void *opaque) { const TypeInfo x86_cpu_type_info = { - .name = TYPE_X86_CPU, - .parent = TYPE_CPU, - .instance_userdata = opaque, - .instance_size = sizeof(X86CPU), - .instance_init = x86_cpu_initfn, - .abstract = true, - .class_size = sizeof(X86CPUClass), - .class_init = x86_cpu_common_class_init, + TYPE_X86_CPU, + TYPE_CPU, + + sizeof(X86CPUClass), + sizeof(X86CPU), + opaque, + + x86_cpu_initfn, + NULL, + NULL, + + NULL, + + x86_cpu_common_class_init, + NULL, + NULL, + + true, }; //printf("... register X86 cpu\n"); diff --git a/qemu/target-i386/cpu.h b/qemu/target-i386/cpu.h index 8cc951fc..5f3921d6 100644 --- a/qemu/target-i386/cpu.h +++ b/qemu/target-i386/cpu.h @@ -805,7 +805,7 @@ typedef struct BNDCSReg { #define MMX_Q(n) q typedef union { - floatx80 d __attribute__((aligned(16))); + floatx80 QEMU_ALIGN(16, d); MMXReg mmx; } FPReg; @@ -869,7 +869,8 @@ typedef struct CPUX86State { uint64_t msr_bndcfgs; /* Beginning of state preserved by INIT (dummy marker). */ - struct {} start_init_save; + //struct {} start_init_save; + int start_init_save; /* FPU state */ unsigned int fpstt; /* top of stack index */ @@ -937,7 +938,8 @@ typedef struct CPUX86State { uint32_t smbase; /* End of state preserved by INIT (dummy marker). */ - struct {} end_init_save; + //struct {} end_init_save; + int end_init_save; uint64_t system_time_msr; uint64_t wall_clock_msr; diff --git a/qemu/target-i386/fpu_helper.c b/qemu/target-i386/fpu_helper.c index a74380f0..9ef803d6 100644 --- a/qemu/target-i386/fpu_helper.c +++ b/qemu/target-i386/fpu_helper.c @@ -489,42 +489,58 @@ void helper_fabs_ST0(CPUX86State *env) void helper_fld1_ST0(CPUX86State *env) { - ST0 = floatx80_one; + //ST0 = floatx80_one; + floatx80 one = { 0x8000000000000000LL, 0x3fff }; + ST0 = one; } void helper_fldl2t_ST0(CPUX86State *env) { - ST0 = floatx80_l2t; + //ST0 = floatx80_l2t; + floatx80 l2t = { 0xd49a784bcd1b8afeLL, 0x4000 }; + ST0 = l2t; } void helper_fldl2e_ST0(CPUX86State *env) { - ST0 = floatx80_l2e; + //ST0 = floatx80_l2e; + floatx80 l2e = { 0xb8aa3b295c17f0bcLL, 0x3fff }; + ST0 = l2e; } void helper_fldpi_ST0(CPUX86State *env) { - ST0 = floatx80_pi; + //ST0 = floatx80_pi; + floatx80 pi = { 0xc90fdaa22168c235LL, 0x4000 }; + ST0 = pi; } void helper_fldlg2_ST0(CPUX86State *env) { - ST0 = floatx80_lg2; + //ST0 = floatx80_lg2; + floatx80 lg2 = { 0x9a209a84fbcff799LL, 0x3ffd }; + ST0 = lg2; } void helper_fldln2_ST0(CPUX86State *env) { - ST0 = floatx80_ln2; + //ST0 = floatx80_ln2; + floatx80 ln2 = { 0xb17217f7d1cf79acLL, 0x3ffe }; + ST0 = ln2; } void helper_fldz_ST0(CPUX86State *env) { - ST0 = floatx80_zero; + //ST0 = floatx80_zero; + floatx80 zero = { 0x0000000000000000LL, 0x0000 }; + ST0 = zero; } void helper_fldz_FT0(CPUX86State *env) { - FT0 = floatx80_zero; + //FT0 = floatx80_zero; + floatx80 zero = { 0x0000000000000000LL, 0x0000 }; + ST0 = zero; } uint32_t helper_fnstsw(CPUX86State *env) @@ -686,10 +702,11 @@ void helper_fptan(CPUX86State *env) if ((fptemp > MAXTAN) || (fptemp < -MAXTAN)) { env->fpus |= 0x400; } else { - fptemp = tan(fptemp); + floatx80 one = { 0x8000000000000000LL, 0x3fff }; + fptemp = tan(fptemp); ST0 = double_to_floatx80(env, fptemp); fpush(env); - ST0 = floatx80_one; + ST0 = one; env->fpus &= ~0x400; /* C2 <-- 0 */ /* the above code is for |arg| < 2**52 only */ } @@ -713,7 +730,9 @@ void helper_fxtract(CPUX86State *env) if (floatx80_is_zero(ST0)) { /* Easy way to generate -inf and raising division by 0 exception */ - ST0 = floatx80_div(floatx80_chs(floatx80_one), floatx80_zero, + floatx80 zero = { 0x0000000000000000LL, 0x0000 }; + floatx80 one = { 0x8000000000000000LL, 0x3fff }; + ST0 = floatx80_div(floatx80_chs(one), zero, &env->fp_status); fpush(env); ST0 = temp.d; @@ -740,7 +759,8 @@ void helper_fprem1(CPUX86State *env) st1 = floatx80_to_double(env, ST1); if (isinf(st0) || isnan(st0) || isnan(st1) || (st1 == 0.0)) { - ST0 = double_to_floatx80(env, 0.0 / 0.0); /* NaN */ + + ST0 = double_to_floatx80(env, NAN); /* NaN */ env->fpus &= ~0x4700; /* (C3,C2,C1,C0) <-- 0000 */ return; } @@ -799,7 +819,7 @@ void helper_fprem(CPUX86State *env) st1 = floatx80_to_double(env, ST1); if (isinf(st0) || isnan(st0) || isnan(st1) || (st1 == 0.0)) { - ST0 = double_to_floatx80(env, 0.0 / 0.0); /* NaN */ + ST0 = double_to_floatx80(env, NAN); /* NaN */ env->fpus &= ~0x4700; /* (C3,C2,C1,C0) <-- 0000 */ return; } @@ -992,7 +1012,7 @@ void helper_fstenv(CPUX86State *env, target_ulong ptr, int data32) cpu_stl_data(env, ptr, env->fpuc); cpu_stl_data(env, ptr + 4, fpus); cpu_stl_data(env, ptr + 8, fptag); - cpu_stl_data(env, ptr + 12, env->fpip); /* fpip */ + cpu_stl_data(env, ptr + 12, (uint32_t)env->fpip); /* fpip */ cpu_stl_data(env, ptr + 20, 0); /* fpcs */ cpu_stl_data(env, ptr + 24, 0); /* fpoo */ cpu_stl_data(env, ptr + 28, 0); /* fpos */ @@ -1001,7 +1021,7 @@ void helper_fstenv(CPUX86State *env, target_ulong ptr, int data32) cpu_stl_data(env, ptr, env->fpuc); cpu_stl_data(env, ptr + 4, fpus); cpu_stl_data(env, ptr + 8, fptag); - cpu_stl_data(env, ptr + 12, env->fpip); /* fpip */ + cpu_stl_data(env, ptr + 12, (uint32_t)env->fpip); /* fpip */ cpu_stl_data(env, ptr + 16, 0); /* fpcs */ cpu_stl_data(env, ptr + 20, 0); /* fpoo */ cpu_stl_data(env, ptr + 24, 0); /* fpos */ @@ -1010,7 +1030,7 @@ void helper_fstenv(CPUX86State *env, target_ulong ptr, int data32) cpu_stw_data(env, ptr, env->fpuc); cpu_stw_data(env, ptr + 2, fpus); cpu_stw_data(env, ptr + 4, fptag); - cpu_stw_data(env, ptr + 6, env->fpip); + cpu_stw_data(env, ptr + 6, (uint32_t)env->fpip); cpu_stw_data(env, ptr + 8, 0); cpu_stw_data(env, ptr + 10, 0); cpu_stw_data(env, ptr + 12, 0); diff --git a/qemu/target-i386/helper.c b/qemu/target-i386/helper.c index 5341094e..0ff3df6f 100644 --- a/qemu/target-i386/helper.c +++ b/qemu/target-i386/helper.c @@ -1002,7 +1002,7 @@ bool check_hw_breakpoints(CPUX86State *env, bool force_dr6_update) break; } if (bp_match || wp_match) { - dr6 |= 1 << reg; + dr6 |= 1ULL << reg; if (hw_breakpoint_enabled(env->dr[7], reg)) { hit_enabled = true; } @@ -1083,7 +1083,7 @@ int cpu_x86_get_descr_debug(CPUX86State *env, unsigned int selector, dt = &env->gdt; index = selector & ~7; ptr = dt->base + index; - if ((index + 7) > dt->limit + if ((uint32_t)(index + 7) > dt->limit || cpu_memory_rw_debug(cs, ptr, (uint8_t *)&e1, sizeof(e1), 0) != 0 || cpu_memory_rw_debug(cs, ptr+4, (uint8_t *)&e2, sizeof(e2), 0) != 0) return 0; diff --git a/qemu/target-i386/int_helper.c b/qemu/target-i386/int_helper.c index 7f1074a1..6d73ac9a 100644 --- a/qemu/target-i386/int_helper.c +++ b/qemu/target-i386/int_helper.c @@ -121,7 +121,7 @@ void helper_divl_EAX(CPUX86State *env, target_ulong t0) uint64_t num, q; num = ((uint32_t)env->regs[R_EAX]) | ((uint64_t)((uint32_t)env->regs[R_EDX]) << 32); - den = t0; + den = (unsigned int)t0; if (den == 0) { raise_exception(env, EXCP00_DIVZ); } @@ -140,7 +140,7 @@ void helper_idivl_EAX(CPUX86State *env, target_ulong t0) int64_t num, q; num = ((uint32_t)env->regs[R_EAX]) | ((uint64_t)((uint32_t)env->regs[R_EDX]) << 32); - den = t0; + den = (int)t0; if (den == 0) { raise_exception(env, EXCP00_DIVZ); } @@ -362,14 +362,14 @@ static int idiv64(uint64_t *plow, uint64_t *phigh, int64_t b) if (*plow > (1ULL << 63)) { return 1; } - *plow = -*plow; + *plow = 0-*plow; } else { if (*plow >= (1ULL << 63)) { return 1; } } if (sa) { - *phigh = -*phigh; + *phigh = 0-*phigh; } return 0; } diff --git a/qemu/target-i386/misc_helper.c b/qemu/target-i386/misc_helper.c index 2704fea7..a3950b7c 100644 --- a/qemu/target-i386/misc_helper.c +++ b/qemu/target-i386/misc_helper.c @@ -126,17 +126,17 @@ void helper_write_crN(CPUX86State *env, int reg, target_ulong t0) cpu_svm_check_intercept_param(env, SVM_EXIT_WRITE_CR0 + reg, 0); switch (reg) { case 0: - cpu_x86_update_cr0(env, t0); + cpu_x86_update_cr0(env, (uint32_t)t0); break; case 3: cpu_x86_update_cr3(env, t0); break; case 4: - cpu_x86_update_cr4(env, t0); + cpu_x86_update_cr4(env, (uint32_t)t0); break; case 8: if (!(env->hflags2 & HF2_VINTR_MASK)) { - cpu_set_apic_tpr(env->uc, x86_env_get_cpu(env)->apic_state, t0); + cpu_set_apic_tpr(env->uc, x86_env_get_cpu(env)->apic_state, (uint8_t)t0); } env->v_tpr = t0 & 0x0f; break; diff --git a/qemu/target-i386/ops_sse.h b/qemu/target-i386/ops_sse.h index 886e0a82..57b152c8 100644 --- a/qemu/target-i386/ops_sse.h +++ b/qemu/target-i386/ops_sse.h @@ -1945,7 +1945,7 @@ static inline int pcmp_elen(CPUX86State *env, int reg, uint32_t ctrl) /* Presence of REX.W is indicated by a bit higher than 7 set */ if (ctrl >> 8) { - val = abs1((int64_t)env->regs[reg]); + val = abs1((int)env->regs[reg]); } else { val = abs1((int32_t)env->regs[reg]); } diff --git a/qemu/target-i386/seg_helper.c b/qemu/target-i386/seg_helper.c index 326fb870..c3e4f938 100644 --- a/qemu/target-i386/seg_helper.c +++ b/qemu/target-i386/seg_helper.c @@ -947,6 +947,7 @@ void helper_syscall(CPUX86State *env, int next_eip_addend) { // Unicorn: call registered syscall hooks struct hook *hook; + HOOK_FOREACH_VAR_DECLARE; HOOK_FOREACH(env->uc, hook, UC_HOOK_INSN) { if (!HOOK_BOUND_CHECK(hook, env->eip)) continue; @@ -956,7 +957,7 @@ void helper_syscall(CPUX86State *env, int next_eip_addend) env->eip += next_eip_addend; return; - +/* int selector; if (!(env->efer & MSR_EFER_SCE)) { @@ -1005,6 +1006,7 @@ void helper_syscall(CPUX86State *env, int next_eip_addend) DESC_W_MASK | DESC_A_MASK); env->eip = (uint32_t)env->star; } +*/ } #endif #endif @@ -2307,6 +2309,7 @@ void helper_sysenter(CPUX86State *env, int next_eip_addend) { // Unicorn: call registered SYSENTER hooks struct hook *hook; + HOOK_FOREACH_VAR_DECLARE; HOOK_FOREACH(env->uc, hook, UC_HOOK_INSN) { if (!HOOK_BOUND_CHECK(hook, env->eip)) continue; diff --git a/qemu/target-i386/shift_helper_template.h b/qemu/target-i386/shift_helper_template.h index cf91a2d2..9e646d74 100644 --- a/qemu/target-i386/shift_helper_template.h +++ b/qemu/target-i386/shift_helper_template.h @@ -55,7 +55,7 @@ target_ulong glue(helper_rcl, SUFFIX)(CPUX86State *env, target_ulong t0, count = rclb_table[count]; #endif if (count) { - eflags = env->cc_src; + eflags = (int)env->cc_src; t0 &= DATA_MASK; src = t0; res = (t0 << count) | ((target_ulong)(eflags & CC_C) << (count - 1)); @@ -84,7 +84,7 @@ target_ulong glue(helper_rcr, SUFFIX)(CPUX86State *env, target_ulong t0, count = rclb_table[count]; #endif if (count) { - eflags = env->cc_src; + eflags = (int)env->cc_src; t0 &= DATA_MASK; src = t0; res = (t0 >> count) | diff --git a/qemu/target-i386/smm_helper.c b/qemu/target-i386/smm_helper.c index 58051d3b..7875ff03 100644 --- a/qemu/target-i386/smm_helper.c +++ b/qemu/target-i386/smm_helper.c @@ -97,12 +97,12 @@ void do_smm_enter(X86CPU *cpu) } stq_phys(cs->as, sm_state + 0x7f78, env->eip); stl_phys(cs->as, sm_state + 0x7f70, cpu_compute_eflags(env)); - stl_phys(cs->as, sm_state + 0x7f68, env->dr[6]); - stl_phys(cs->as, sm_state + 0x7f60, env->dr[7]); + stl_phys(cs->as, sm_state + 0x7f68, (uint32_t)env->dr[6]); + stl_phys(cs->as, sm_state + 0x7f60, (uint32_t)env->dr[7]); - stl_phys(cs->as, sm_state + 0x7f48, env->cr[4]); - stl_phys(cs->as, sm_state + 0x7f50, env->cr[3]); - stl_phys(cs->as, sm_state + 0x7f58, env->cr[0]); + stl_phys(cs->as, sm_state + 0x7f48, (uint32_t)env->cr[4]); + stl_phys(cs->as, sm_state + 0x7f50, (uint32_t)env->cr[3]); + stl_phys(cs->as, sm_state + 0x7f58, (uint32_t)env->cr[0]); stl_phys(cs->as, sm_state + 0x7efc, SMM_REVISION_ID); stl_phys(cs->as, sm_state + 0x7f00, env->smbase); diff --git a/qemu/target-i386/svm.h b/qemu/target-i386/svm.h index 04193ed6..c84ff47f 100644 --- a/qemu/target-i386/svm.h +++ b/qemu/target-i386/svm.h @@ -130,7 +130,7 @@ #define SVM_CR0_SELECTIVE_MASK (1 << 3 | 1) /* TS and MP */ -struct QEMU_PACKED vmcb_control_area { +QEMU_PACK( struct vmcb_control_area { uint16_t intercept_cr_read; uint16_t intercept_cr_write; uint16_t intercept_dr_read; @@ -160,16 +160,16 @@ struct QEMU_PACKED vmcb_control_area { uint64_t nested_cr3; uint64_t lbr_ctl; uint8_t reserved_5[832]; -}; +}); -struct QEMU_PACKED vmcb_seg { +QEMU_PACK( struct vmcb_seg { uint16_t selector; uint16_t attrib; uint32_t limit; uint64_t base; -}; +}); -struct QEMU_PACKED vmcb_save_area { +QEMU_PACK( struct vmcb_save_area { struct vmcb_seg es; struct vmcb_seg cs; struct vmcb_seg ss; @@ -212,11 +212,11 @@ struct QEMU_PACKED vmcb_save_area { uint64_t br_to; uint64_t last_excp_from; uint64_t last_excp_to; -}; +}); -struct QEMU_PACKED vmcb { +QEMU_PACK( struct vmcb { struct vmcb_control_area control; struct vmcb_save_area save; -}; +}); #endif diff --git a/qemu/target-i386/svm_helper.c b/qemu/target-i386/svm_helper.c index 429d029a..df69c816 100644 --- a/qemu/target-i386/svm_helper.c +++ b/qemu/target-i386/svm_helper.c @@ -486,33 +486,27 @@ void helper_svm_check_intercept_param(CPUX86State *env, uint32_t type, if (likely(!(env->hflags & HF_SVMI_MASK))) { return; } - switch (type) { - case SVM_EXIT_READ_CR0 ... SVM_EXIT_READ_CR0 + 8: + if( type >= SVM_EXIT_READ_CR0 && type <= SVM_EXIT_READ_CR0 + 8 ) { if (env->intercept_cr_read & (1 << (type - SVM_EXIT_READ_CR0))) { helper_vmexit(env, type, param); } - break; - case SVM_EXIT_WRITE_CR0 ... SVM_EXIT_WRITE_CR0 + 8: + } else if( type >= SVM_EXIT_WRITE_CR0 && type <= SVM_EXIT_WRITE_CR0 + 8 ) { if (env->intercept_cr_write & (1 << (type - SVM_EXIT_WRITE_CR0))) { helper_vmexit(env, type, param); } - break; - case SVM_EXIT_READ_DR0 ... SVM_EXIT_READ_DR0 + 7: + } else if( type >= SVM_EXIT_READ_DR0 && type <= SVM_EXIT_READ_DR0 + 7 ) { if (env->intercept_dr_read & (1 << (type - SVM_EXIT_READ_DR0))) { helper_vmexit(env, type, param); } - break; - case SVM_EXIT_WRITE_DR0 ... SVM_EXIT_WRITE_DR0 + 7: + } else if( type >= SVM_EXIT_WRITE_DR0 && type <= SVM_EXIT_WRITE_DR0 + 7 ) { if (env->intercept_dr_write & (1 << (type - SVM_EXIT_WRITE_DR0))) { helper_vmexit(env, type, param); } - break; - case SVM_EXIT_EXCP_BASE ... SVM_EXIT_EXCP_BASE + 31: + } else if( type >= SVM_EXIT_EXCP_BASE && type <= SVM_EXIT_EXCP_BASE + 31 ) { if (env->intercept_exceptions & (1 << (type - SVM_EXIT_EXCP_BASE))) { helper_vmexit(env, type, param); } - break; - case SVM_EXIT_MSR: + } else if( type == SVM_EXIT_MSR ) { if (env->intercept & (1ULL << (SVM_EXIT_MSR - SVM_EXIT_INTR))) { /* FIXME: this should be read in at vmrun (faster this way?) */ uint64_t addr = ldq_phys(cs->as, env->vm_vmcb + @@ -520,38 +514,32 @@ void helper_svm_check_intercept_param(CPUX86State *env, uint32_t type, control.msrpm_base_pa)); uint32_t t0, t1; - switch ((uint32_t)env->regs[R_ECX]) { - case 0 ... 0x1fff: + uint32_t ecx = (uint32_t)env->regs[R_ECX]; + if( ecx >= 0 && ecx <= 0x1fff ) { t0 = (env->regs[R_ECX] * 2) % 8; t1 = (env->regs[R_ECX] * 2) / 8; - break; - case 0xc0000000 ... 0xc0001fff: + } else if( ecx >= 0xc0000000 && ecx <= 0xc0001fff ) { t0 = (8192 + env->regs[R_ECX] - 0xc0000000) * 2; t1 = (t0 / 8); t0 %= 8; - break; - case 0xc0010000 ... 0xc0011fff: + } else if( ecx >= 0xc0010000 && ecx <= 0xc0011fff ) { t0 = (16384 + env->regs[R_ECX] - 0xc0010000) * 2; t1 = (t0 / 8); t0 %= 8; - break; - default: + } else { helper_vmexit(env, type, param); t0 = 0; t1 = 0; - break; } if (ldub_phys(cs->as, addr + t1) & ((1 << param) << t0)) { helper_vmexit(env, type, param); } } - break; - default: + } else { if (env->intercept & (1ULL << (type - SVM_EXIT_INTR))) { helper_vmexit(env, type, param); } - break; - } + } } void cpu_svm_check_intercept_param(CPUX86State *env, uint32_t type, diff --git a/qemu/target-i386/topology.h b/qemu/target-i386/topology.h index 07a6c5fb..87f1820d 100644 --- a/qemu/target-i386/topology.h +++ b/qemu/target-i386/topology.h @@ -38,7 +38,7 @@ * CPUID Fn8000_0008_ECX[ApicIdCoreIdSize[3:0]] is set to apicid_core_width(). */ -#include +#include "platform.h" #include #include "qemu/bitops.h" diff --git a/qemu/target-i386/translate.c b/qemu/target-i386/translate.c index 771b294b..4792a697 100644 --- a/qemu/target-i386/translate.c +++ b/qemu/target-i386/translate.c @@ -20,7 +20,7 @@ #include #include #include -#include +#include "platform.h" #include #include "qemu/host-utils.h" @@ -173,7 +173,72 @@ enum { /* Bit set if the global variable is live after setting CC_OP to X. */ static const uint8_t cc_op_live[CC_OP_NB] = { - [CC_OP_DYNAMIC] = USES_CC_DST | USES_CC_SRC | USES_CC_SRC2, +#ifdef _MSC_VER + USES_CC_DST | USES_CC_SRC | USES_CC_SRC2, // CC_OP_DYNAMIC, /* must use dynamic code to get cc_op */ + USES_CC_SRC, // CC_OP_EFLAGS, /* all cc are explicitly computed, CC_SRC = flags */ + + USES_CC_DST | USES_CC_SRC, // CC_OP_MULB, /* modify all flags, C, O = (CC_SRC != 0) */ + USES_CC_DST | USES_CC_SRC, // CC_OP_MULW, + USES_CC_DST | USES_CC_SRC, // CC_OP_MULL, + USES_CC_DST | USES_CC_SRC, // CC_OP_MULQ, + + USES_CC_DST | USES_CC_SRC, // CC_OP_ADDB, /* modify all flags, CC_DST = res, CC_SRC = src1 */ + USES_CC_DST | USES_CC_SRC, // CC_OP_ADDW, + USES_CC_DST | USES_CC_SRC, // CC_OP_ADDL, + USES_CC_DST | USES_CC_SRC, // CC_OP_ADDQ, + + USES_CC_DST | USES_CC_SRC | USES_CC_SRC2, // CC_OP_ADCB, /* modify all flags, CC_DST = res, CC_SRC = src1 */ + USES_CC_DST | USES_CC_SRC | USES_CC_SRC2, // CC_OP_ADCW, + USES_CC_DST | USES_CC_SRC | USES_CC_SRC2, // CC_OP_ADCL, + USES_CC_DST | USES_CC_SRC | USES_CC_SRC2, // CC_OP_ADCQ, + + USES_CC_DST | USES_CC_SRC | USES_CC_SRCT, // CC_OP_SUBB, /* modify all flags, CC_DST = res, CC_SRC = src1 */ + USES_CC_DST | USES_CC_SRC | USES_CC_SRCT, // CC_OP_SUBW, + USES_CC_DST | USES_CC_SRC | USES_CC_SRCT, // CC_OP_SUBL, + USES_CC_DST | USES_CC_SRC | USES_CC_SRCT, // CC_OP_SUBQ, + + USES_CC_DST | USES_CC_SRC | USES_CC_SRC2, // CC_OP_SBBB, /* modify all flags, CC_DST = res, CC_SRC = src1 */ + USES_CC_DST | USES_CC_SRC | USES_CC_SRC2, // CC_OP_SBBW, + USES_CC_DST | USES_CC_SRC | USES_CC_SRC2, // CC_OP_SBBL, + USES_CC_DST | USES_CC_SRC | USES_CC_SRC2, // CC_OP_SBBQ, + + USES_CC_DST, // CC_OP_LOGICB, /* modify all flags, CC_DST = res */ + USES_CC_DST, // CC_OP_LOGICW, + USES_CC_DST, // CC_OP_LOGICL, + USES_CC_DST, // CC_OP_LOGICQ, + + USES_CC_DST | USES_CC_SRC, // CC_OP_INCB, /* modify all flags except, CC_DST = res, CC_SRC = C */ + USES_CC_DST | USES_CC_SRC, // CC_OP_INCW, + USES_CC_DST | USES_CC_SRC, // CC_OP_INCL, + USES_CC_DST | USES_CC_SRC, // CC_OP_INCQ, + + USES_CC_DST | USES_CC_SRC, // CC_OP_DECB, /* modify all flags except, CC_DST = res, CC_SRC = C */ + USES_CC_DST | USES_CC_SRC, // CC_OP_DECW, + USES_CC_DST | USES_CC_SRC, // CC_OP_DECL, + USES_CC_DST | USES_CC_SRC, // CC_OP_DECQ, + + USES_CC_DST | USES_CC_SRC, // CC_OP_SHLB, /* modify all flags, CC_DST = res, CC_SRC.msb = C */ + USES_CC_DST | USES_CC_SRC, // CC_OP_SHLW, + USES_CC_DST | USES_CC_SRC, // CC_OP_SHLL, + USES_CC_DST | USES_CC_SRC, // CC_OP_SHLQ, + + USES_CC_DST | USES_CC_SRC, // CC_OP_SARB, /* modify all flags, CC_DST = res, CC_SRC.lsb = C */ + USES_CC_DST | USES_CC_SRC, // CC_OP_SARW, + USES_CC_DST | USES_CC_SRC, // CC_OP_SARL, + USES_CC_DST | USES_CC_SRC, // CC_OP_SARQ, + + USES_CC_DST | USES_CC_SRC, // CC_OP_BMILGB, /* Z,S via CC_DST, C = SRC==0; O=0; P,A undefined */ + USES_CC_DST | USES_CC_SRC, // CC_OP_BMILGW, + USES_CC_DST | USES_CC_SRC, // CC_OP_BMILGL, + USES_CC_DST | USES_CC_SRC, // CC_OP_BMILGQ, + + USES_CC_DST | USES_CC_SRC, // CC_OP_ADCX, /* CC_DST = C, CC_SRC = rest. */ + USES_CC_SRC | USES_CC_SRC2, // CC_OP_ADOX, /* CC_DST = O, CC_SRC = rest. */ + USES_CC_DST | USES_CC_SRC | USES_CC_SRC2, // CC_OP_ADCOX, /* CC_DST = C, CC_SRC2 = O, CC_SRC = rest. */ + + 0, // CC_OP_CLR, /* Z set, all other flags clear. */ +#else + [CC_OP_DYNAMIC] = USES_CC_DST | USES_CC_SRC | USES_CC_SRC2, [CC_OP_EFLAGS] = USES_CC_SRC, [CC_OP_MULB ... CC_OP_MULQ] = USES_CC_DST | USES_CC_SRC, [CC_OP_ADDB ... CC_OP_ADDQ] = USES_CC_DST | USES_CC_SRC, @@ -190,6 +255,7 @@ static const uint8_t cc_op_live[CC_OP_NB] = { [CC_OP_ADOX] = USES_CC_SRC | USES_CC_SRC2, [CC_OP_ADCOX] = USES_CC_DST | USES_CC_SRC | USES_CC_SRC2, [CC_OP_CLR] = 0, +#endif }; static inline void gen_jmp_im(DisasContext *s, target_ulong pc); @@ -886,7 +952,7 @@ static void gen_compute_eflags(DisasContext *s) } typedef struct CCPrepare { - TCGCond cond; + TCGCond cond; TCGv reg; TCGv reg2; target_ulong imm; @@ -895,10 +961,19 @@ typedef struct CCPrepare { bool no_setcond; } CCPrepare; +CCPrepare ccprepare_setup(TCGCond cond, + TCGv reg, TCGv reg2, + target_ulong imm, target_ulong mask, + bool use_reg2, bool no_setcond) +{ + CCPrepare cc = { cond, reg, reg2, imm, mask, use_reg2, no_setcond }; + return cc; +} + /* compute eflags.C to reg */ static CCPrepare gen_prepare_eflags_c(DisasContext *s, TCGv reg) { - TCGv t0, t1; + TCGv t0, t1; int size, shift; TCGContext *tcg_ctx = s->uc->tcg_ctx; TCGv_i32 cpu_cc_op = tcg_ctx->cpu_cc_op; @@ -909,69 +984,62 @@ static CCPrepare gen_prepare_eflags_c(DisasContext *s, TCGv reg) TCGv cpu_tmp0 = *(TCGv *)tcg_ctx->cpu_tmp0; switch (s->cc_op) { - case CC_OP_SUBB ... CC_OP_SUBQ: - /* (DATA_TYPE)CC_SRCT < (DATA_TYPE)CC_SRC */ - size = s->cc_op - CC_OP_SUBB; - t1 = gen_ext_tl(tcg_ctx, cpu_tmp0, cpu_cc_src, size, false); - /* If no temporary was used, be careful not to alias t1 and t0. */ - t0 = TCGV_EQUAL(t1, cpu_cc_src) ? cpu_tmp0 : reg; - tcg_gen_mov_tl(tcg_ctx, t0, cpu_cc_srcT); - gen_extu(tcg_ctx, size, t0); - goto add_sub; + case CC_OP_SUBB: case CC_OP_SUBW: case CC_OP_SUBL: case CC_OP_SUBQ: + /* (DATA_TYPE)CC_SRCT < (DATA_TYPE)CC_SRC */ + size = s->cc_op - CC_OP_SUBB; + t1 = gen_ext_tl(tcg_ctx, cpu_tmp0, cpu_cc_src, size, false); + /* If no temporary was used, be careful not to alias t1 and t0. */ + t0 = TCGV_EQUAL(t1, cpu_cc_src) ? cpu_tmp0 : reg; + tcg_gen_mov_tl(tcg_ctx, t0, cpu_cc_srcT); + gen_extu(tcg_ctx, size, t0); + goto add_sub; - case CC_OP_ADDB ... CC_OP_ADDQ: - /* (DATA_TYPE)CC_DST < (DATA_TYPE)CC_SRC */ - size = s->cc_op - CC_OP_ADDB; - t1 = gen_ext_tl(tcg_ctx, cpu_tmp0, cpu_cc_src, size, false); - t0 = gen_ext_tl(tcg_ctx, reg, cpu_cc_dst, size, false); - add_sub: - return (CCPrepare) { .cond = TCG_COND_LTU, .reg = t0, - .reg2 = t1, .mask = -1, .use_reg2 = true }; + case CC_OP_ADDB: case CC_OP_ADDW: case CC_OP_ADDL: case CC_OP_ADDQ: + /* (DATA_TYPE)CC_DST < (DATA_TYPE)CC_SRC */ + size = s->cc_op - CC_OP_ADDB; + t1 = gen_ext_tl(tcg_ctx, cpu_tmp0, cpu_cc_src, size, false); + t0 = gen_ext_tl(tcg_ctx, reg, cpu_cc_dst, size, false); + add_sub: + return ccprepare_setup(TCG_COND_LTU, t0,t1, 0,-1, true,false); - case CC_OP_LOGICB ... CC_OP_LOGICQ: + case CC_OP_LOGICB: case CC_OP_LOGICW: case CC_OP_LOGICL: case CC_OP_LOGICQ: case CC_OP_CLR: - return (CCPrepare) { .cond = TCG_COND_NEVER, .mask = -1 }; + return ccprepare_setup(TCG_COND_NEVER, 0,0, 0,-1, false,false); - case CC_OP_INCB ... CC_OP_INCQ: - case CC_OP_DECB ... CC_OP_DECQ: - return (CCPrepare) { .cond = TCG_COND_NE, .reg = cpu_cc_src, - .mask = -1, .no_setcond = true }; + case CC_OP_INCB: case CC_OP_INCW: case CC_OP_INCL: case CC_OP_INCQ: + case CC_OP_DECB: case CC_OP_DECW: case CC_OP_DECL: case CC_OP_DECQ: + return ccprepare_setup(TCG_COND_NE, cpu_cc_src,0, 0,-1, false,true ); - case CC_OP_SHLB ... CC_OP_SHLQ: + case CC_OP_SHLB: case CC_OP_SHLW: case CC_OP_SHLL: case CC_OP_SHLQ: /* (CC_SRC >> (DATA_BITS - 1)) & 1 */ - size = s->cc_op - CC_OP_SHLB; + size = s->cc_op - CC_OP_SHLB; shift = (8 << size) - 1; - return (CCPrepare) { .cond = TCG_COND_NE, .reg = cpu_cc_src, - .mask = (target_ulong)1 << shift }; + return ccprepare_setup(TCG_COND_NE, cpu_cc_src,0, 0,(target_ulong)(1 << shift), false,false); - case CC_OP_MULB ... CC_OP_MULQ: - return (CCPrepare) { .cond = TCG_COND_NE, - .reg = cpu_cc_src, .mask = -1 }; + case CC_OP_MULB: case CC_OP_MULW: case CC_OP_MULL: case CC_OP_MULQ: + return ccprepare_setup(TCG_COND_NE, cpu_cc_src,0, 0,-1, false,false ); - case CC_OP_BMILGB ... CC_OP_BMILGQ: - size = s->cc_op - CC_OP_BMILGB; + case CC_OP_BMILGB: case CC_OP_BMILGW: case CC_OP_BMILGL: case CC_OP_BMILGQ: + size = s->cc_op - CC_OP_BMILGB; t0 = gen_ext_tl(tcg_ctx, reg, cpu_cc_src, size, false); - return (CCPrepare) { .cond = TCG_COND_EQ, .reg = t0, .mask = -1 }; + return ccprepare_setup(TCG_COND_EQ, t0,0, 0,-1, false,false); case CC_OP_ADCX: case CC_OP_ADCOX: - return (CCPrepare) { .cond = TCG_COND_NE, .reg = cpu_cc_dst, - .mask = -1, .no_setcond = true }; + return ccprepare_setup(TCG_COND_NE, cpu_cc_dst,0, 0,-1, false,true); case CC_OP_EFLAGS: - case CC_OP_SARB ... CC_OP_SARQ: + case CC_OP_SARB: case CC_OP_SARW: case CC_OP_SARL: case CC_OP_SARQ: /* CC_SRC & 1 */ - return (CCPrepare) { .cond = TCG_COND_NE, - .reg = cpu_cc_src, .mask = CC_C }; + return ccprepare_setup(TCG_COND_NE, cpu_cc_src,0, 0,CC_C, false,false); default: - /* The need to compute only C from CC_OP_DYNAMIC is important - in efficiently implementing e.g. INC at the start of a TB. */ - gen_update_cc_op(s); - gen_helper_cc_compute_c(tcg_ctx, reg, cpu_cc_dst, cpu_cc_src, - cpu_cc_src2, cpu_cc_op); - return (CCPrepare) { .cond = TCG_COND_NE, .reg = reg, - .mask = -1, .no_setcond = true }; + /* The need to compute only C from CC_OP_DYNAMIC is important + in efficiently implementing e.g. INC at the start of a TB. */ + gen_update_cc_op(s); + gen_helper_cc_compute_c(tcg_ctx, reg, cpu_cc_dst, cpu_cc_src, + cpu_cc_src2, cpu_cc_op); + return ccprepare_setup(TCG_COND_NE, reg,0, 0,-1, false,true); } } @@ -982,8 +1050,7 @@ static CCPrepare gen_prepare_eflags_p(DisasContext *s, TCGv reg) TCGv cpu_cc_src = *(TCGv *)tcg_ctx->cpu_cc_src; gen_compute_eflags(s); - return (CCPrepare) { .cond = TCG_COND_NE, .reg = cpu_cc_src, - .mask = CC_P }; + return ccprepare_setup(TCG_COND_NE, cpu_cc_src,0, 0,CC_P, false,false); } /* compute eflags.S to reg */ @@ -1001,15 +1068,14 @@ static CCPrepare gen_prepare_eflags_s(DisasContext *s, TCGv reg) case CC_OP_ADCX: case CC_OP_ADOX: case CC_OP_ADCOX: - return (CCPrepare) { .cond = TCG_COND_NE, .reg = cpu_cc_src, - .mask = CC_S }; + return ccprepare_setup(TCG_COND_NE, cpu_cc_src,0, 0,CC_S, false,false); case CC_OP_CLR: - return (CCPrepare) { .cond = TCG_COND_NEVER, .mask = -1 }; + return ccprepare_setup(TCG_COND_NEVER, 0,0, 0,-1, false,false); default: { TCGMemOp size = (s->cc_op - CC_OP_ADDB) & 3; TCGv t0 = gen_ext_tl(tcg_ctx, reg, cpu_cc_dst, size, true); - return (CCPrepare) { .cond = TCG_COND_LT, .reg = t0, .mask = -1 }; + return ccprepare_setup(TCG_COND_LT, t0,0, 0,-1, false,false); } } } @@ -1024,14 +1090,12 @@ static CCPrepare gen_prepare_eflags_o(DisasContext *s, TCGv reg) switch (s->cc_op) { case CC_OP_ADOX: case CC_OP_ADCOX: - return (CCPrepare) { .cond = TCG_COND_NE, .reg = cpu_cc_src2, - .mask = -1, .no_setcond = true }; + return ccprepare_setup(TCG_COND_NE, cpu_cc_src2,0, 0,-1, false,true); case CC_OP_CLR: - return (CCPrepare) { .cond = TCG_COND_NEVER, .mask = -1 }; + return ccprepare_setup(TCG_COND_NEVER, 0,0, 0,-1, false,false); default: - gen_compute_eflags(s); - return (CCPrepare) { .cond = TCG_COND_NE, .reg = cpu_cc_src, - .mask = CC_O }; + gen_compute_eflags(s); + return ccprepare_setup(TCG_COND_NE, cpu_cc_src,0, 0,CC_O, false,false ); } } @@ -1050,16 +1114,15 @@ static CCPrepare gen_prepare_eflags_z(DisasContext *s, TCGv reg) case CC_OP_ADCX: case CC_OP_ADOX: case CC_OP_ADCOX: - return (CCPrepare) { .cond = TCG_COND_NE, .reg = cpu_cc_src, - .mask = CC_Z }; + return ccprepare_setup(TCG_COND_NE, cpu_cc_src,0, 0,CC_Z, false,false); case CC_OP_CLR: - return (CCPrepare) { .cond = TCG_COND_ALWAYS, .mask = -1 }; + return ccprepare_setup(TCG_COND_ALWAYS, 0,0, 0,-1, false,false); default: - { + { TCGMemOp size = (s->cc_op - CC_OP_ADDB) & 3; TCGv t0 = gen_ext_tl(tcg_ctx, reg, cpu_cc_dst, size, false); - return (CCPrepare) { .cond = TCG_COND_EQ, .reg = t0, .mask = -1 }; - } + return ccprepare_setup(TCG_COND_EQ, t0,0, 0,-1, false,false); + } } } @@ -1067,7 +1130,7 @@ static CCPrepare gen_prepare_eflags_z(DisasContext *s, TCGv reg) value 'b'. In the fast case, T0 is guaranted not to be used. */ static CCPrepare gen_prepare_cc(DisasContext *s, int b, TCGv reg) { - int inv, jcc_op, cond; + int inv, jcc_op, cond; TCGMemOp size; CCPrepare cc; TCGv t0; @@ -1081,7 +1144,10 @@ static CCPrepare gen_prepare_cc(DisasContext *s, int b, TCGv reg) jcc_op = (b >> 1) & 7; switch (s->cc_op) { - case CC_OP_SUBB ... CC_OP_SUBQ: + case CC_OP_SUBB: + case CC_OP_SUBW: + case CC_OP_SUBL: + case CC_OP_SUBQ: /* We optimize relational operators for the cmp/jcc case. */ size = s->cc_op - CC_OP_SUBB; switch (jcc_op) { @@ -1089,8 +1155,7 @@ static CCPrepare gen_prepare_cc(DisasContext *s, int b, TCGv reg) tcg_gen_mov_tl(tcg_ctx, cpu_tmp4, cpu_cc_srcT); gen_extu(tcg_ctx, size, cpu_tmp4); t0 = gen_ext_tl(tcg_ctx, cpu_tmp0, cpu_cc_src, size, false); - cc = (CCPrepare) { .cond = TCG_COND_LEU, .reg = cpu_tmp4, - .reg2 = t0, .mask = -1, .use_reg2 = true }; + cc = ccprepare_setup(TCG_COND_LEU, cpu_tmp4,t0, 0,-1, true,false); break; case JCC_L: @@ -1102,8 +1167,7 @@ static CCPrepare gen_prepare_cc(DisasContext *s, int b, TCGv reg) tcg_gen_mov_tl(tcg_ctx, cpu_tmp4, cpu_cc_srcT); gen_exts(tcg_ctx, size, cpu_tmp4); t0 = gen_ext_tl(tcg_ctx, cpu_tmp0, cpu_cc_src, size, true); - cc = (CCPrepare) { .cond = cond, .reg = cpu_tmp4, - .reg2 = t0, .mask = -1, .use_reg2 = true }; + cc = ccprepare_setup(cond, cpu_tmp4,t0, 0,-1, true,false); break; default: @@ -1126,8 +1190,7 @@ static CCPrepare gen_prepare_cc(DisasContext *s, int b, TCGv reg) break; case JCC_BE: gen_compute_eflags(s); - cc = (CCPrepare) { .cond = TCG_COND_NE, .reg = cpu_cc_src, - .mask = CC_Z | CC_C }; + cc = ccprepare_setup(TCG_COND_NE, cpu_cc_src,0, 0,CC_Z | CC_C, false,false); break; case JCC_S: cc = gen_prepare_eflags_s(s, reg); @@ -1142,8 +1205,7 @@ static CCPrepare gen_prepare_cc(DisasContext *s, int b, TCGv reg) } tcg_gen_shri_tl(tcg_ctx, reg, cpu_cc_src, 4); /* CC_O -> CC_S */ tcg_gen_xor_tl(tcg_ctx, reg, reg, cpu_cc_src); - cc = (CCPrepare) { .cond = TCG_COND_NE, .reg = reg, - .mask = CC_S }; + cc = ccprepare_setup(TCG_COND_NE, reg,0, 0,CC_S, false,false); break; default: case JCC_LE: @@ -1153,8 +1215,7 @@ static CCPrepare gen_prepare_cc(DisasContext *s, int b, TCGv reg) } tcg_gen_shri_tl(tcg_ctx, reg, cpu_cc_src, 4); /* CC_O -> CC_S */ tcg_gen_xor_tl(tcg_ctx, reg, reg, cpu_cc_src); - cc = (CCPrepare) { .cond = TCG_COND_NE, .reg = reg, - .mask = CC_S | CC_Z }; + cc = ccprepare_setup(TCG_COND_NE, reg,0, 0,CC_S | CC_Z, false,false); break; } break; @@ -2956,141 +3017,200 @@ typedef void (*SSEFunc_0_eppt)(TCGContext *s, TCGv_ptr env, TCGv_ptr reg_a, TCGv gen_helper_ ## x ## ss, gen_helper_ ## x ## sd, } static const SSEFunc_0_epp sse_op_table1[256][4] = { - /* 3DNow! extensions */ - [0x0e] = { SSE_DUMMY }, /* femms */ - [0x0f] = { SSE_DUMMY }, /* pf... */ + // filler: 0x00 - 0x0e + {0},{0},{0},{0},{0},{0},{0},{0},{0},{0},{0},{0},{0},{0}, + + /* 3DNow! extensions */ + { SSE_DUMMY }, /* femms */ + { SSE_DUMMY }, /* pf. . . */ + /* pure SSE operations */ - [0x10] = { SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL }, /* movups, movupd, movss, movsd */ - [0x11] = { SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL }, /* movups, movupd, movss, movsd */ - [0x12] = { SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL }, /* movlps, movlpd, movsldup, movddup */ - [0x13] = { SSE_SPECIAL, SSE_SPECIAL }, /* movlps, movlpd */ - [0x14] = { gen_helper_punpckldq_xmm, gen_helper_punpcklqdq_xmm }, - [0x15] = { gen_helper_punpckhdq_xmm, gen_helper_punpckhqdq_xmm }, - [0x16] = { SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL }, /* movhps, movhpd, movshdup */ - [0x17] = { SSE_SPECIAL, SSE_SPECIAL }, /* movhps, movhpd */ - - [0x28] = { SSE_SPECIAL, SSE_SPECIAL }, /* movaps, movapd */ - [0x29] = { SSE_SPECIAL, SSE_SPECIAL }, /* movaps, movapd */ - [0x2a] = { SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL }, /* cvtpi2ps, cvtpi2pd, cvtsi2ss, cvtsi2sd */ - [0x2b] = { SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL }, /* movntps, movntpd, movntss, movntsd */ - [0x2c] = { SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL }, /* cvttps2pi, cvttpd2pi, cvttsd2si, cvttss2si */ - [0x2d] = { SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL }, /* cvtps2pi, cvtpd2pi, cvtsd2si, cvtss2si */ - [0x2e] = { gen_helper_ucomiss, gen_helper_ucomisd }, - [0x2f] = { gen_helper_comiss, gen_helper_comisd }, - [0x50] = { SSE_SPECIAL, SSE_SPECIAL }, /* movmskps, movmskpd */ - [0x51] = SSE_FOP(sqrt), - [0x52] = { gen_helper_rsqrtps, NULL, gen_helper_rsqrtss, NULL }, - [0x53] = { gen_helper_rcpps, NULL, gen_helper_rcpss, NULL }, - [0x54] = { gen_helper_pand_xmm, gen_helper_pand_xmm }, /* andps, andpd */ - [0x55] = { gen_helper_pandn_xmm, gen_helper_pandn_xmm }, /* andnps, andnpd */ - [0x56] = { gen_helper_por_xmm, gen_helper_por_xmm }, /* orps, orpd */ - [0x57] = { gen_helper_pxor_xmm, gen_helper_pxor_xmm }, /* xorps, xorpd */ - [0x58] = SSE_FOP(add), - [0x59] = SSE_FOP(mul), - [0x5a] = { gen_helper_cvtps2pd, gen_helper_cvtpd2ps, - gen_helper_cvtss2sd, gen_helper_cvtsd2ss }, - [0x5b] = { gen_helper_cvtdq2ps, gen_helper_cvtps2dq, gen_helper_cvttps2dq }, - [0x5c] = SSE_FOP(sub), - [0x5d] = SSE_FOP(min), - [0x5e] = SSE_FOP(div), - [0x5f] = SSE_FOP(max), - - [0xc2] = SSE_FOP(cmpeq), - [0xc6] = { (SSEFunc_0_epp)gen_helper_shufps, - (SSEFunc_0_epp)gen_helper_shufpd }, /* XXX: casts */ - + { SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL }, /* movups, movupd, movss, movsd */ + { SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL }, /* movups, movupd, movss, movsd */ + { SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL }, /* movlps, movlpd, movsldup, movddup */ + { SSE_SPECIAL, SSE_SPECIAL }, /* movlps, movlpd */ + { gen_helper_punpckldq_xmm, gen_helper_punpcklqdq_xmm }, + { gen_helper_punpckhdq_xmm, gen_helper_punpckhqdq_xmm }, + { SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL }, /* movhps, movhpd, movshdup */ + { SSE_SPECIAL, SSE_SPECIAL }, /* movhps, movhpd */ + + // filler: 0x18 - 0x27 + {0},{0},{0},{0},{0},{0},{0},{0}, {0},{0},{0},{0},{0},{0},{0},{0}, + + /* pure SSE operations */ + { SSE_SPECIAL, SSE_SPECIAL }, /* movaps, movapd */ + { SSE_SPECIAL, SSE_SPECIAL }, /* movaps, movapd */ + { SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL }, /* cvtpi2ps, cvtpi2pd, cvtsi2ss, cvtsi2sd */ + { SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL }, /* movntps, movntpd, movntss, movntsd */ + { SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL }, /* cvttps2pi, cvttpd2pi, cvttsd2si, cvttss2si */ + { SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL }, /* cvtps2pi, cvtpd2pi, cvtsd2si, cvtss2si */ + { gen_helper_ucomiss, gen_helper_ucomisd }, + { gen_helper_comiss, gen_helper_comisd }, + + // filler: 0x30 - 0x37 + {0},{0},{0},{0},{0},{0},{0},{0}, + /* SSSE3, SSE4, MOVBE, CRC32, BMI1, BMI2, ADX. */ - [0x38] = { SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL }, - [0x3a] = { SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL }, + { SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL }, + {0}, // filler: 0x39 + { SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL }, + + // filler: 0x3b - 0x4f + {0},{0},{0},{0},{0}, {0},{0},{0},{0},{0},{0},{0},{0}, {0},{0},{0},{0},{0},{0},{0},{0}, + + /* pure SSE operations */ + { SSE_SPECIAL, SSE_SPECIAL }, /* movmskps, movmskpd */ + SSE_FOP(sqrt), + { gen_helper_rsqrtps, NULL, gen_helper_rsqrtss, NULL }, + { gen_helper_rcpps, NULL, gen_helper_rcpss, NULL }, + { gen_helper_pand_xmm, gen_helper_pand_xmm }, /* andps, andpd */ + { gen_helper_pandn_xmm, gen_helper_pandn_xmm }, /* andnps, andnpd */ + { gen_helper_por_xmm, gen_helper_por_xmm }, /* orps, orpd */ + { gen_helper_pxor_xmm, gen_helper_pxor_xmm }, /* xorps, xorpd */ + SSE_FOP(add), + SSE_FOP(mul), + { gen_helper_cvtps2pd, gen_helper_cvtpd2ps, + gen_helper_cvtss2sd, gen_helper_cvtsd2ss }, + { gen_helper_cvtdq2ps, gen_helper_cvtps2dq, gen_helper_cvttps2dq }, + SSE_FOP(sub), + SSE_FOP(min), + SSE_FOP(div), + SSE_FOP(max), /* MMX ops and their SSE extensions */ - [0x60] = MMX_OP2(punpcklbw), - [0x61] = MMX_OP2(punpcklwd), - [0x62] = MMX_OP2(punpckldq), - [0x63] = MMX_OP2(packsswb), - [0x64] = MMX_OP2(pcmpgtb), - [0x65] = MMX_OP2(pcmpgtw), - [0x66] = MMX_OP2(pcmpgtl), - [0x67] = MMX_OP2(packuswb), - [0x68] = MMX_OP2(punpckhbw), - [0x69] = MMX_OP2(punpckhwd), - [0x6a] = MMX_OP2(punpckhdq), - [0x6b] = MMX_OP2(packssdw), - [0x6c] = { NULL, gen_helper_punpcklqdq_xmm }, - [0x6d] = { NULL, gen_helper_punpckhqdq_xmm }, - [0x6e] = { SSE_SPECIAL, SSE_SPECIAL }, /* movd mm, ea */ - [0x6f] = { SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL }, /* movq, movdqa, , movqdu */ - [0x70] = { (SSEFunc_0_epp)gen_helper_pshufw_mmx, - (SSEFunc_0_epp)gen_helper_pshufd_xmm, - (SSEFunc_0_epp)gen_helper_pshufhw_xmm, - (SSEFunc_0_epp)gen_helper_pshuflw_xmm }, /* XXX: casts */ - [0x71] = { SSE_SPECIAL, SSE_SPECIAL }, /* shiftw */ - [0x72] = { SSE_SPECIAL, SSE_SPECIAL }, /* shiftd */ - [0x73] = { SSE_SPECIAL, SSE_SPECIAL }, /* shiftq */ - [0x74] = MMX_OP2(pcmpeqb), - [0x75] = MMX_OP2(pcmpeqw), - [0x76] = MMX_OP2(pcmpeql), - [0x77] = { SSE_DUMMY }, /* emms */ - [0x78] = { NULL, SSE_SPECIAL, NULL, SSE_SPECIAL }, /* extrq_i, insertq_i */ - [0x79] = { NULL, gen_helper_extrq_r, NULL, gen_helper_insertq_r }, - [0x7c] = { NULL, gen_helper_haddpd, NULL, gen_helper_haddps }, - [0x7d] = { NULL, gen_helper_hsubpd, NULL, gen_helper_hsubps }, - [0x7e] = { SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL }, /* movd, movd, , movq */ - [0x7f] = { SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL }, /* movq, movdqa, movdqu */ - [0xc4] = { SSE_SPECIAL, SSE_SPECIAL }, /* pinsrw */ - [0xc5] = { SSE_SPECIAL, SSE_SPECIAL }, /* pextrw */ - [0xd0] = { NULL, gen_helper_addsubpd, NULL, gen_helper_addsubps }, - [0xd1] = MMX_OP2(psrlw), - [0xd2] = MMX_OP2(psrld), - [0xd3] = MMX_OP2(psrlq), - [0xd4] = MMX_OP2(paddq), - [0xd5] = MMX_OP2(pmullw), - [0xd6] = { NULL, SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL }, - [0xd7] = { SSE_SPECIAL, SSE_SPECIAL }, /* pmovmskb */ - [0xd8] = MMX_OP2(psubusb), - [0xd9] = MMX_OP2(psubusw), - [0xda] = MMX_OP2(pminub), - [0xdb] = MMX_OP2(pand), - [0xdc] = MMX_OP2(paddusb), - [0xdd] = MMX_OP2(paddusw), - [0xde] = MMX_OP2(pmaxub), - [0xdf] = MMX_OP2(pandn), - [0xe0] = MMX_OP2(pavgb), - [0xe1] = MMX_OP2(psraw), - [0xe2] = MMX_OP2(psrad), - [0xe3] = MMX_OP2(pavgw), - [0xe4] = MMX_OP2(pmulhuw), - [0xe5] = MMX_OP2(pmulhw), - [0xe6] = { NULL, gen_helper_cvttpd2dq, gen_helper_cvtdq2pd, gen_helper_cvtpd2dq }, - [0xe7] = { SSE_SPECIAL , SSE_SPECIAL }, /* movntq, movntq */ - [0xe8] = MMX_OP2(psubsb), - [0xe9] = MMX_OP2(psubsw), - [0xea] = MMX_OP2(pminsw), - [0xeb] = MMX_OP2(por), - [0xec] = MMX_OP2(paddsb), - [0xed] = MMX_OP2(paddsw), - [0xee] = MMX_OP2(pmaxsw), - [0xef] = MMX_OP2(pxor), - [0xf0] = { NULL, NULL, NULL, SSE_SPECIAL }, /* lddqu */ - [0xf1] = MMX_OP2(psllw), - [0xf2] = MMX_OP2(pslld), - [0xf3] = MMX_OP2(psllq), - [0xf4] = MMX_OP2(pmuludq), - [0xf5] = MMX_OP2(pmaddwd), - [0xf6] = MMX_OP2(psadbw), - [0xf7] = { (SSEFunc_0_epp)gen_helper_maskmov_mmx, - (SSEFunc_0_epp)gen_helper_maskmov_xmm }, /* XXX: casts */ - [0xf8] = MMX_OP2(psubb), - [0xf9] = MMX_OP2(psubw), - [0xfa] = MMX_OP2(psubl), - [0xfb] = MMX_OP2(psubq), - [0xfc] = MMX_OP2(paddb), - [0xfd] = MMX_OP2(paddw), - [0xfe] = MMX_OP2(paddl), + MMX_OP2(punpcklbw), + MMX_OP2(punpcklwd), + MMX_OP2(punpckldq), + MMX_OP2(packsswb), + MMX_OP2(pcmpgtb), + MMX_OP2(pcmpgtw), + MMX_OP2(pcmpgtl), + MMX_OP2(packuswb), + MMX_OP2(punpckhbw), + MMX_OP2(punpckhwd), + MMX_OP2(punpckhdq), + MMX_OP2(packssdw), + { NULL, gen_helper_punpcklqdq_xmm }, + { NULL, gen_helper_punpckhqdq_xmm }, + { SSE_SPECIAL, SSE_SPECIAL }, /* movd mm, ea */ + { SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL }, /* movq, movdqa, , movqdu */ + { (SSEFunc_0_epp)gen_helper_pshufw_mmx, + (SSEFunc_0_epp)gen_helper_pshufd_xmm, + (SSEFunc_0_epp)gen_helper_pshufhw_xmm, + (SSEFunc_0_epp)gen_helper_pshuflw_xmm }, /* XXX: casts */ + { SSE_SPECIAL, SSE_SPECIAL }, /* shiftw */ + { SSE_SPECIAL, SSE_SPECIAL }, /* shiftd */ + { SSE_SPECIAL, SSE_SPECIAL }, /* shiftq */ + MMX_OP2(pcmpeqb), + MMX_OP2(pcmpeqw), + MMX_OP2(pcmpeql), + { SSE_DUMMY }, /* emms */ + { NULL, SSE_SPECIAL, NULL, SSE_SPECIAL }, /* extrq_i, insertq_i */ + { NULL, gen_helper_extrq_r, NULL, gen_helper_insertq_r }, + {0},{0}, // filler: 0x7a - 0x7b + { NULL, gen_helper_haddpd, NULL, gen_helper_haddps }, + { NULL, gen_helper_hsubpd, NULL, gen_helper_hsubps }, + { SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL }, /* movd, movd, , movq */ + { SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL }, /* movq, movdqa, movdqu */ + + // filler: 0x80 - 0xc1 + {0},{0},{0},{0},{0},{0},{0},{0}, {0},{0},{0},{0},{0},{0},{0},{0}, + {0},{0},{0},{0},{0},{0},{0},{0}, {0},{0},{0},{0},{0},{0},{0},{0}, + {0},{0},{0},{0},{0},{0},{0},{0}, {0},{0},{0},{0},{0},{0},{0},{0}, + {0},{0},{0},{0},{0},{0},{0},{0}, {0},{0},{0},{0},{0},{0},{0},{0}, + {0},{0}, + + SSE_FOP(cmpeq), + + // filler: 0xc3 + {0}, + + /* MMX ops and their SSE extensions */ + { SSE_SPECIAL, SSE_SPECIAL }, /* pinsrw */ + { SSE_SPECIAL, SSE_SPECIAL }, /* pextrw */ + + { (SSEFunc_0_epp)gen_helper_shufps, + (SSEFunc_0_epp)gen_helper_shufpd }, /* XXX: casts */ + + // filler: 0xc7 - 0xcf + {0}, {0},{0},{0},{0},{0},{0},{0},{0}, + + /* MMX ops and their SSE extensions */ + { NULL, gen_helper_addsubpd, NULL, gen_helper_addsubps }, + MMX_OP2(psrlw), + MMX_OP2(psrld), + MMX_OP2(psrlq), + MMX_OP2(paddq), + MMX_OP2(pmullw), + { NULL, SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL }, + { SSE_SPECIAL, SSE_SPECIAL }, /* pmovmskb */ + MMX_OP2(psubusb), + MMX_OP2(psubusw), + MMX_OP2(pminub), + MMX_OP2(pand), + MMX_OP2(paddusb), + MMX_OP2(paddusw), + MMX_OP2(pmaxub), + MMX_OP2(pandn), + MMX_OP2(pavgb), + MMX_OP2(psraw), + MMX_OP2(psrad), + MMX_OP2(pavgw), + MMX_OP2(pmulhuw), + MMX_OP2(pmulhw), + { NULL, gen_helper_cvttpd2dq, gen_helper_cvtdq2pd, gen_helper_cvtpd2dq }, + { SSE_SPECIAL , SSE_SPECIAL }, /* movntq, movntq */ + MMX_OP2(psubsb), + MMX_OP2(psubsw), + MMX_OP2(pminsw), + MMX_OP2(por), + MMX_OP2(paddsb), + MMX_OP2(paddsw), + MMX_OP2(pmaxsw), + MMX_OP2(pxor), + { NULL, NULL, NULL, SSE_SPECIAL }, /* lddqu */ + MMX_OP2(psllw), + MMX_OP2(pslld), + MMX_OP2(psllq), + MMX_OP2(pmuludq), + MMX_OP2(pmaddwd), + MMX_OP2(psadbw), + { (SSEFunc_0_epp)gen_helper_maskmov_mmx, + (SSEFunc_0_epp)gen_helper_maskmov_xmm }, /* XXX: casts */ + MMX_OP2(psubb), + MMX_OP2(psubw), + MMX_OP2(psubl), + MMX_OP2(psubq), + MMX_OP2(paddb), + MMX_OP2(paddw), + MMX_OP2(paddl), + + // filler: 0xff + {0}, }; static const SSEFunc_0_epp sse_op_table2[3 * 8][2] = { - [0 + 2] = MMX_OP2(psrlw), +#ifdef _MSC_VER + {0},{0}, + MMX_OP2(psrlw), + {0}, + MMX_OP2(psraw), + {0}, + MMX_OP2(psllw), + {0},{0},{0}, + MMX_OP2(psrld), + {0}, + MMX_OP2(psrad), + {0}, + MMX_OP2(pslld), + {0},{0},{0}, + MMX_OP2(psrlq), + { NULL, gen_helper_psrldq_xmm }, + {0},{0}, + MMX_OP2(psllq), + { NULL, gen_helper_pslldq_xmm }, +#else + [0 + 2] = MMX_OP2(psrlw), [0 + 4] = MMX_OP2(psraw), [0 + 6] = MMX_OP2(psllw), [8 + 2] = MMX_OP2(psrld), @@ -3100,6 +3220,7 @@ static const SSEFunc_0_epp sse_op_table2[3 * 8][2] = { [16 + 3] = { NULL, gen_helper_psrldq_xmm }, [16 + 6] = MMX_OP2(psllq), [16 + 7] = { NULL, gen_helper_pslldq_xmm }, +#endif }; static const SSEFunc_0_epi sse_op_table3ai[] = { @@ -3142,7 +3263,65 @@ static const SSEFunc_0_epp sse_op_table4[8][4] = { }; static const SSEFunc_0_epp sse_op_table5[256] = { - [0x0c] = gen_helper_pi2fw, +#ifdef _MSC_VER + {0},{0},{0},{0},{0},{0},{0},{0}, {0},{0},{0},{0}, // filler: 0x00 - 0x0b + gen_helper_pi2fw, + gen_helper_pi2fd, + {0},{0}, {0},{0},{0},{0},{0},{0},{0},{0}, {0},{0},{0},{0}, // filler: 0x0e - 0x01b + gen_helper_pf2iw, + gen_helper_pf2id, + // filler: 0x1e - 0x89 + {0},{0}, + {0},{0},{0},{0},{0},{0},{0},{0}, {0},{0},{0},{0},{0},{0},{0},{0}, + {0},{0},{0},{0},{0},{0},{0},{0}, {0},{0},{0},{0},{0},{0},{0},{0}, + {0},{0},{0},{0},{0},{0},{0},{0}, {0},{0},{0},{0},{0},{0},{0},{0}, + {0},{0},{0},{0},{0},{0},{0},{0}, {0},{0},{0},{0},{0},{0},{0},{0}, + {0},{0},{0},{0},{0},{0},{0},{0}, {0},{0},{0},{0},{0},{0},{0},{0}, + {0},{0},{0},{0},{0},{0},{0},{0}, {0},{0},{0},{0},{0},{0},{0},{0}, + {0},{0},{0},{0},{0},{0},{0},{0}, {0},{0}, + gen_helper_pfnacc, + {0},{0},{0}, // filler: 0x8b - 0x8d + gen_helper_pfpnacc, + {0}, // filler: 0x8f + gen_helper_pfcmpge, + {0},{0},{0}, // filler: 0x91 - 0x93 + gen_helper_pfmin, + {0}, // filler: 0x95 + gen_helper_pfrcp, + gen_helper_pfrsqrt, + {0},{0}, // filler: 0x98 - 0x99 + gen_helper_pfsub, + {0},{0},{0}, // filler: 0x9b - 0x9d + gen_helper_pfadd, + {0}, // filler: 0x9f + gen_helper_pfcmpgt, + {0},{0},{0}, // filler: 0xa1 - 0xa3 + gen_helper_pfmax, + {0}, // filler: 0xa5 + gen_helper_movq, /* pfrcpit1; no need to actually increase precision */ + gen_helper_movq, /* pfrsqit1 */ + {0},{0}, // filler: 0xa8 - 0xa9 + gen_helper_pfsubr, + {0},{0},{0}, // filler: 0xab - 0xad + gen_helper_pfacc, + {0}, // filler: 0xaf + gen_helper_pfcmpeq, + {0},{0},{0}, // filler: 0xb1 - 0xb3 + gen_helper_pfmul, + {0}, // filler: 0xb5 + gen_helper_movq, /* pfrcpit2 */ + gen_helper_pmulhrw_mmx, + {0},{0},{0}, // filler: 0xb8 - 0xba + gen_helper_pswapd, + {0},{0},{0}, // filler: 0xbc - 0xbe + gen_helper_pavgb_mmx, /* pavgusb */ + // filler: 0xc0 - 0xff + {0},{0},{0},{0},{0},{0},{0},{0}, {0},{0},{0},{0},{0},{0},{0},{0}, + {0},{0},{0},{0},{0},{0},{0},{0}, {0},{0},{0},{0},{0},{0},{0},{0}, + {0},{0},{0},{0},{0},{0},{0},{0}, {0},{0},{0},{0},{0},{0},{0},{0}, + {0},{0},{0},{0},{0},{0},{0},{0}, {0},{0},{0},{0},{0},{0},{0},{0}, +#else + [0x0c] = gen_helper_pi2fw, [0x0d] = gen_helper_pi2fd, [0x1c] = gen_helper_pf2iw, [0x1d] = gen_helper_pf2id, @@ -3166,6 +3345,7 @@ static const SSEFunc_0_epp sse_op_table5[256] = { [0xb7] = gen_helper_pmulhrw_mmx, [0xbb] = gen_helper_pswapd, [0xbf] = gen_helper_pavgb_mmx /* pavgusb */ +#endif }; struct SSEOpHelper_epp { @@ -3187,61 +3367,131 @@ struct SSEOpHelper_eppi { #define AESNI_OP(x) { { NULL, gen_helper_ ## x ## _xmm }, CPUID_EXT_AES } static const struct SSEOpHelper_epp sse_op_table6[256] = { - [0x00] = SSSE3_OP(pshufb), - [0x01] = SSSE3_OP(phaddw), - [0x02] = SSSE3_OP(phaddd), - [0x03] = SSSE3_OP(phaddsw), - [0x04] = SSSE3_OP(pmaddubsw), - [0x05] = SSSE3_OP(phsubw), - [0x06] = SSSE3_OP(phsubd), - [0x07] = SSSE3_OP(phsubsw), - [0x08] = SSSE3_OP(psignb), - [0x09] = SSSE3_OP(psignw), - [0x0a] = SSSE3_OP(psignd), - [0x0b] = SSSE3_OP(pmulhrsw), - [0x10] = SSE41_OP(pblendvb), - [0x14] = SSE41_OP(blendvps), - [0x15] = SSE41_OP(blendvpd), - [0x17] = SSE41_OP(ptest), - [0x1c] = SSSE3_OP(pabsb), - [0x1d] = SSSE3_OP(pabsw), - [0x1e] = SSSE3_OP(pabsd), - [0x20] = SSE41_OP(pmovsxbw), - [0x21] = SSE41_OP(pmovsxbd), - [0x22] = SSE41_OP(pmovsxbq), - [0x23] = SSE41_OP(pmovsxwd), - [0x24] = SSE41_OP(pmovsxwq), - [0x25] = SSE41_OP(pmovsxdq), - [0x28] = SSE41_OP(pmuldq), - [0x29] = SSE41_OP(pcmpeqq), - [0x2a] = SSE41_SPECIAL, /* movntqda */ - [0x2b] = SSE41_OP(packusdw), - [0x30] = SSE41_OP(pmovzxbw), - [0x31] = SSE41_OP(pmovzxbd), - [0x32] = SSE41_OP(pmovzxbq), - [0x33] = SSE41_OP(pmovzxwd), - [0x34] = SSE41_OP(pmovzxwq), - [0x35] = SSE41_OP(pmovzxdq), - [0x37] = SSE42_OP(pcmpgtq), - [0x38] = SSE41_OP(pminsb), - [0x39] = SSE41_OP(pminsd), - [0x3a] = SSE41_OP(pminuw), - [0x3b] = SSE41_OP(pminud), - [0x3c] = SSE41_OP(pmaxsb), - [0x3d] = SSE41_OP(pmaxsd), - [0x3e] = SSE41_OP(pmaxuw), - [0x3f] = SSE41_OP(pmaxud), - [0x40] = SSE41_OP(pmulld), - [0x41] = SSE41_OP(phminposuw), - [0xdb] = AESNI_OP(aesimc), - [0xdc] = AESNI_OP(aesenc), - [0xdd] = AESNI_OP(aesenclast), - [0xde] = AESNI_OP(aesdec), - [0xdf] = AESNI_OP(aesdeclast), + SSSE3_OP(pshufb), + SSSE3_OP(phaddw), + SSSE3_OP(phaddd), + SSSE3_OP(phaddsw), + SSSE3_OP(pmaddubsw), + SSSE3_OP(phsubw), + SSSE3_OP(phsubd), + SSSE3_OP(phsubsw), + SSSE3_OP(psignb), + SSSE3_OP(psignw), + SSSE3_OP(psignd), + SSSE3_OP(pmulhrsw), + {0},{0},{0},{0}, // filler: 0x0c - 0x0f + SSE41_OP(pblendvb), + {0},{0},{0}, // filler: 0x11 - 0x13 + SSE41_OP(blendvps), + SSE41_OP(blendvpd), + {0}, // filler: 0x16 + SSE41_OP(ptest), + {0},{0},{0},{0}, // filler: 0x18 - 0x1b + SSSE3_OP(pabsb), + SSSE3_OP(pabsw), + SSSE3_OP(pabsd), + {0}, // filler: 0x1f + SSE41_OP(pmovsxbw), + SSE41_OP(pmovsxbd), + SSE41_OP(pmovsxbq), + SSE41_OP(pmovsxwd), + SSE41_OP(pmovsxwq), + SSE41_OP(pmovsxdq), + {0},{0}, // filler: 0x26 - 0x27 + SSE41_OP(pmuldq), + SSE41_OP(pcmpeqq), + SSE41_SPECIAL, /* movntqda */ + SSE41_OP(packusdw), + {0},{0},{0},{0}, // filler: 0x2c - 0x2f + SSE41_OP(pmovzxbw), + SSE41_OP(pmovzxbd), + SSE41_OP(pmovzxbq), + SSE41_OP(pmovzxwd), + SSE41_OP(pmovzxwq), + SSE41_OP(pmovzxdq), + {0}, // filler: 0x36 + SSE42_OP(pcmpgtq), + SSE41_OP(pminsb), + SSE41_OP(pminsd), + SSE41_OP(pminuw), + SSE41_OP(pminud), + SSE41_OP(pmaxsb), + SSE41_OP(pmaxsd), + SSE41_OP(pmaxuw), + SSE41_OP(pmaxud), + SSE41_OP(pmulld), + SSE41_OP(phminposuw), + // filler: 0x42 - 0xda + {0},{0},{0},{0},{0},{0}, {0},{0},{0},{0},{0},{0},{0},{0}, + {0},{0},{0},{0},{0},{0},{0},{0}, {0},{0},{0},{0},{0},{0},{0},{0}, + {0},{0},{0},{0},{0},{0},{0},{0}, {0},{0},{0},{0},{0},{0},{0},{0}, + {0},{0},{0},{0},{0},{0},{0},{0}, {0},{0},{0},{0},{0},{0},{0},{0}, + {0},{0},{0},{0},{0},{0},{0},{0}, {0},{0},{0},{0},{0},{0},{0},{0}, + {0},{0},{0},{0},{0},{0},{0},{0}, {0},{0},{0},{0},{0},{0},{0},{0}, + {0},{0},{0},{0},{0},{0},{0},{0}, {0},{0},{0},{0},{0},{0},{0},{0}, + {0},{0},{0},{0},{0},{0},{0},{0}, {0},{0},{0},{0},{0},{0},{0},{0}, + {0},{0},{0},{0},{0},{0},{0},{0}, {0},{0},{0},{0},{0},{0},{0},{0}, + {0},{0},{0},{0},{0},{0},{0},{0}, {0},{0},{0}, + AESNI_OP(aesimc), + AESNI_OP(aesenc), + AESNI_OP(aesenclast), + AESNI_OP(aesdec), + AESNI_OP(aesdeclast), + // filler: 0xe0 - 0xff + {0},{0},{0},{0},{0},{0},{0},{0}, {0},{0},{0},{0},{0},{0},{0},{0}, + {0},{0},{0},{0},{0},{0},{0},{0}, {0},{0},{0},{0},{0},{0},{0},{0}, }; static const struct SSEOpHelper_eppi sse_op_table7[256] = { - [0x08] = SSE41_OP(roundps), +#ifdef _MSC_VER + {0},{0},{0},{0},{0},{0},{0},{0}, // filler: 0x00 - 0x07 + SSE41_OP(roundps), + SSE41_OP(roundpd), + SSE41_OP(roundss), + SSE41_OP(roundsd), + SSE41_OP(blendps), + SSE41_OP(blendpd), + SSE41_OP(pblendw), + SSSE3_OP(palignr), + {0},{0},{0},{0}, // filler: 0x10 - 0x13 + SSE41_SPECIAL, /* pextrb */ + SSE41_SPECIAL, /* pextrw */ + SSE41_SPECIAL, /* pextrd/pextrq */ + SSE41_SPECIAL, /* extractps */ + {0},{0},{0},{0},{0},{0},{0},{0}, // filler: 0x18 - 0x1f + SSE41_SPECIAL, /* pinsrb */ + SSE41_SPECIAL, /* insertps */ + SSE41_SPECIAL, /* pinsrd/pinsrq */ + // filler: 0x23 - 0x3f + {0},{0},{0},{0},{0}, {0},{0},{0},{0},{0},{0},{0},{0}, + {0},{0},{0},{0},{0},{0},{0},{0}, {0},{0},{0},{0},{0},{0},{0},{0}, + SSE41_OP(dpps), + SSE41_OP(dppd), + SSE41_OP(mpsadbw), + {0}, // filler: 0x43 + PCLMULQDQ_OP(pclmulqdq), + // filler: 0x45 - 0x5f + {0},{0},{0}, {0},{0},{0},{0},{0},{0},{0},{0}, + {0},{0},{0},{0},{0},{0},{0},{0}, {0},{0},{0},{0},{0},{0},{0},{0}, + SSE42_OP(pcmpestrm), + SSE42_OP(pcmpestri), + SSE42_OP(pcmpistrm), + SSE42_OP(pcmpistri), + // filler: 0x64 - 0xde + {0},{0},{0},{0}, {0},{0},{0},{0},{0},{0},{0},{0}, + {0},{0},{0},{0},{0},{0},{0},{0}, {0},{0},{0},{0},{0},{0},{0},{0}, + {0},{0},{0},{0},{0},{0},{0},{0}, {0},{0},{0},{0},{0},{0},{0},{0}, + {0},{0},{0},{0},{0},{0},{0},{0}, {0},{0},{0},{0},{0},{0},{0},{0}, + {0},{0},{0},{0},{0},{0},{0},{0}, {0},{0},{0},{0},{0},{0},{0},{0}, + {0},{0},{0},{0},{0},{0},{0},{0}, {0},{0},{0},{0},{0},{0},{0},{0}, + {0},{0},{0},{0},{0},{0},{0},{0}, {0},{0},{0},{0},{0},{0},{0},{0}, + {0},{0},{0},{0},{0},{0},{0},{0}, {0},{0},{0},{0},{0},{0},{0}, + AESNI_OP(aeskeygenassist), + // filler: 0xe0 - 0xff + {0},{0},{0},{0},{0},{0},{0},{0}, {0},{0},{0},{0},{0},{0},{0},{0}, + {0},{0},{0},{0},{0},{0},{0},{0}, {0},{0},{0},{0},{0},{0},{0},{0}, +#else + [0x08] = SSE41_OP(roundps), [0x09] = SSE41_OP(roundpd), [0x0a] = SSE41_OP(roundss), [0x0b] = SSE41_OP(roundsd), @@ -3265,6 +3515,7 @@ static const struct SSEOpHelper_eppi sse_op_table7[256] = { [0x62] = SSE42_OP(pcmpistrm), [0x63] = SSE42_OP(pcmpistri), [0xdf] = AESNI_OP(aeskeygenassist), +#endif }; static void gen_sse(CPUX86State *env, DisasContext *s, int b, @@ -4598,26 +4849,25 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b, gen_lea_modrm(env, s, modrm); op2_offset = offsetof(CPUX86State,xmm_t0); - switch (b) { - case 0x50 ... 0x5a: - case 0x5c ... 0x5f: - case 0xc2: + if( (b >= 0x50 && b <= 0x5a) || + (b >= 0x5c && b <= 0x5f) || + b == 0xc2 ) + { /* Most sse scalar operations. */ if (b1 == 2) { sz = 2; } else if (b1 == 3) { sz = 3; } - break; - - case 0x2e: /* ucomis[sd] */ - case 0x2f: /* comis[sd] */ + } + else if( b == 0x2e || /* ucomis[sd] */ + b == 0x2f ) /* comis[sd] */ + { if (b1 == 0) { sz = 2; } else { sz = 3; } - break; } switch (sz) { @@ -4842,7 +5092,22 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s, prefixes |= PREFIX_ADR; goto next_byte; #ifdef TARGET_X86_64 - case 0x40 ... 0x4f: + case 0x40: + case 0x41: + case 0x42: + case 0x43: + case 0x44: + case 0x45: + case 0x46: + case 0x47: + case 0x48: + case 0x49: + case 0x4a: + case 0x4b: + case 0x4c: + case 0x4d: + case 0x4e: + case 0x4f: if (CODE64(s)) { /* REX prefix */ rex_w = (b >> 3) & 1; @@ -4955,14 +5220,14 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s, /**************************/ /* arith & logic */ - case 0x00 ... 0x05: - case 0x08 ... 0x0d: - case 0x10 ... 0x15: - case 0x18 ... 0x1d: - case 0x20 ... 0x25: - case 0x28 ... 0x2d: - case 0x30 ... 0x35: - case 0x38 ... 0x3d: + case 0x00: case 0x01: case 0x02: case 0x03: case 0x04: case 0x05: //case 0x00 ... 0x05: + case 0x08: case 0x09: case 0x0a: case 0x0b: case 0x0c: case 0x0d: //case 0x08 ... 0x0d: + case 0x10: case 0x11: case 0x12: case 0x13: case 0x14: case 0x15: //case 0x10 ... 0x15: + case 0x18: case 0x19: case 0x1a: case 0x1b: case 0x1c: case 0x1d: //case 0x18 ... 0x1d: + case 0x20: case 0x21: case 0x22: case 0x23: case 0x24: case 0x25: //case 0x20 ... 0x25: + case 0x28: case 0x29: case 0x2a: case 0x2b: case 0x2c: case 0x2d: //case 0x28 ... 0x2d: + case 0x30: case 0x31: case 0x32: case 0x33: case 0x34: case 0x35: //case 0x30 ... 0x35: + case 0x38: case 0x39: case 0x3a: case 0x3b: case 0x3c: case 0x3d: //case 0x38 ... 0x3d: { int op, f, val; op = (b >> 3) & 7; @@ -5061,11 +5326,13 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s, /**************************/ /* inc, dec, and other misc arith */ - case 0x40 ... 0x47: /* inc Gv */ + case 0x40: case 0x41: case 0x42: case 0x43: + case 0x44: case 0x45: case 0x46: case 0x47: //case 0x40 ... 0x47: /* inc Gv */ ot = dflag; gen_inc(s, ot, OR_EAX + (b & 7), 1); break; - case 0x48 ... 0x4f: /* dec Gv */ + case 0x48: case 0x49: case 0x4a: case 0x4b: + case 0x4c: case 0x4d: case 0x4e: case 0x4f: //case 0x48 ... 0x4f: /* dec Gv */ ot = dflag; gen_inc(s, ot, OR_EAX + (b & 7), -1); break; @@ -5606,11 +5873,13 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s, /**************************/ /* push/pop */ - case 0x50 ... 0x57: /* push */ + case 0x50: case 0x51: case 0x52: case 0x53: + case 0x54: case 0x55: case 0x56: case 0x57: //case 0x50 ... 0x57: /* push */ gen_op_mov_v_reg(tcg_ctx, MO_32, *cpu_T[0], (b & 7) | REX_B(s)); gen_push_v(s, *cpu_T[0]); break; - case 0x58 ... 0x5f: /* pop */ + case 0x58: case 0x59: case 0x5a: case 0x5b: + case 0x5c: case 0x5d: case 0x5e: case 0x5f: //case 0x58 ... 0x5f: /* pop */ ot = gen_pop_T0(s); /* NOTE: order is important for pop %sp */ gen_pop_update(s, ot); @@ -5894,12 +6163,14 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s, gen_op_ld_v(s, MO_8, *cpu_T[0], cpu_A0); gen_op_mov_reg_v(tcg_ctx, MO_8, R_EAX, *cpu_T[0]); break; - case 0xb0 ... 0xb7: /* mov R, Ib */ + case 0xb0: case 0xb1: case 0xb2: case 0xb3: + case 0xb4: case 0xb5: case 0xb6: case 0xb7: //case 0xb0 ... 0xb7: /* mov R, Ib */ val = insn_get(env, s, MO_8); tcg_gen_movi_tl(tcg_ctx, *cpu_T[0], val); gen_op_mov_reg_v(tcg_ctx, MO_8, (b & 7) | REX_B(s), *cpu_T[0]); break; - case 0xb8 ... 0xbf: /* mov R, Iv */ + case 0xb8: case 0xb9: case 0xba: case 0xbb: + case 0xbc: case 0xbd: case 0xbe: case 0xbf: //case 0xb8 ... 0xbf: /* mov R, Iv */ #ifdef TARGET_X86_64 if (dflag == MO_64) { uint64_t tmp; @@ -5920,7 +6191,8 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s, } break; - case 0x91 ... 0x97: /* xchg R, EAX */ + case 0x91: case 0x92: case 0x93: + case 0x94: case 0x95: case 0x96: case 0x97: //case 0x91 ... 0x97: /* xchg R, EAX */ do_xchg_reg_eax: ot = dflag; reg = (b & 7) | REX_B(s); @@ -5995,7 +6267,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s, case 0xc1: /* shift Ev,Ib */ shift = 2; - grp2: + grp2_label: { ot = mo_b_d(b, dflag); modrm = cpu_ldub_code(env, s->pc++); @@ -6027,12 +6299,12 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s, case 0xd1: /* shift Ev,1 */ shift = 1; - goto grp2; + goto grp2_label; case 0xd2: case 0xd3: /* shift Ev,cl */ shift = 0; - goto grp2; + goto grp2_label; case 0x1a4: /* shld imm */ op = 0; @@ -6074,7 +6346,8 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s, /************************/ /* floats */ - case 0xd8 ... 0xdf: + case 0xd8: case 0xd9: case 0xda: case 0xdb: + case 0xdc: case 0xdd: case 0xde: case 0xdf: //case 0xd8 ... 0xdf: if (s->flags & (HF_EM_MASK | HF_TS_MASK)) { /* if CR0.EM or CR0.TS are set, generate an FPU exception */ /* XXX: what to do if illegal op ? */ @@ -6088,12 +6361,12 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s, if (mod != 3) { /* memory op */ gen_lea_modrm(env, s, modrm); - switch(op) { - case 0x00 ... 0x07: /* fxxxs */ - case 0x10 ... 0x17: /* fixxxl */ - case 0x20 ... 0x27: /* fxxxl */ - case 0x30 ... 0x37: /* fixxx */ - { + + if( (op >= 0x00 && op <= 0x07) || /* fxxxs */ + (op >= 0x10 && op <= 0x17) || /* fixxxl */ + (op >= 0x20 && op <= 0x27) || /* fxxxl */ + (op >= 0x30 && op <= 0x37) ) /* fixxx */ + { int op1; op1 = op & 7; @@ -6127,14 +6400,14 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s, gen_helper_fpop(tcg_ctx, cpu_env); } fpu_update_ip(env, pc_start); - } - break; - case 0x08: /* flds */ - case 0x0a: /* fsts */ - case 0x0b: /* fstps */ - case 0x18 ... 0x1b: /* fildl, fisttpl, fistl, fistpl */ - case 0x28 ... 0x2b: /* fldl, fisttpll, fstl, fstpl */ - case 0x38 ... 0x3b: /* filds, fisttps, fists, fistps */ + } + else if((op == 0x08) || /* flds */ + (op == 0x0a) || /* fsts */ + (op == 0x0b) || /* fstps */ + (op >= 0x18 && op <= 0x1b) || /* fildl, fisttpl, fistl, fistpl */ + (op >= 0x28 && op <= 0x2b) || /* fldl, fisttpll, fstl, fstpl */ + (op >= 0x38 && op <= 0x3b) ) /* filds, fisttps, fists, fistps */ + { switch(op & 7) { case 0: switch(op >> 4) { @@ -6212,80 +6485,94 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s, break; } fpu_update_ip(env, pc_start); - break; - case 0x0c: /* fldenv mem */ + } + else if(op == 0x0c) /* fldenv mem */ + { gen_update_cc_op(s); gen_jmp_im(s, pc_start - s->cs_base); gen_helper_fldenv(tcg_ctx, cpu_env, cpu_A0, tcg_const_i32(tcg_ctx, dflag - 1)); - break; - case 0x0d: /* fldcw mem */ + } + else if(op == 0x0d) /* fldcw mem */ + { tcg_gen_qemu_ld_i32(s->uc, cpu_tmp2_i32, cpu_A0, s->mem_index, MO_LEUW); gen_helper_fldcw(tcg_ctx, cpu_env, cpu_tmp2_i32); - break; - case 0x0e: /* fnstenv mem */ + } + else if(op == 0x0e) /* fnstenv mem */ + { gen_update_cc_op(s); gen_jmp_im(s, pc_start - s->cs_base); gen_helper_fstenv(tcg_ctx, cpu_env, cpu_A0, tcg_const_i32(tcg_ctx, dflag - 1)); - break; - case 0x0f: /* fnstcw mem */ + } + else if(op == 0x0f) /* fnstcw mem */ + { gen_helper_fnstcw(tcg_ctx, cpu_tmp2_i32, cpu_env); tcg_gen_qemu_st_i32(s->uc, cpu_tmp2_i32, cpu_A0, s->mem_index, MO_LEUW); - break; - case 0x1d: /* fldt mem */ + } + else if(op == 0x1d) /* fldt mem */ + { gen_update_cc_op(s); gen_jmp_im(s, pc_start - s->cs_base); gen_helper_fldt_ST0(tcg_ctx, cpu_env, cpu_A0); fpu_update_ip(env, pc_start); - break; - case 0x1f: /* fstpt mem */ + } + else if(op == 0x1f) /* fstpt mem */ + { gen_update_cc_op(s); gen_jmp_im(s, pc_start - s->cs_base); gen_helper_fstt_ST0(tcg_ctx, cpu_env, cpu_A0); gen_helper_fpop(tcg_ctx, cpu_env); fpu_update_ip(env, pc_start); - break; - case 0x2c: /* frstor mem */ + } + else if(op == 0x2c) /* frstor mem */ + { gen_update_cc_op(s); gen_jmp_im(s, pc_start - s->cs_base); gen_helper_frstor(tcg_ctx, cpu_env, cpu_A0, tcg_const_i32(tcg_ctx, dflag - 1)); - break; - case 0x2e: /* fnsave mem */ + } + else if(op == 0x2e) /* fnsave mem */ + { gen_update_cc_op(s); gen_jmp_im(s, pc_start - s->cs_base); gen_helper_fsave(tcg_ctx, cpu_env, cpu_A0, tcg_const_i32(tcg_ctx, dflag - 1)); - break; - case 0x2f: /* fnstsw mem */ + } + else if(op == 0x2f) /* fnstsw mem */ + { gen_helper_fnstsw(tcg_ctx, cpu_tmp2_i32, cpu_env); tcg_gen_qemu_st_i32(s->uc, cpu_tmp2_i32, cpu_A0, s->mem_index, MO_LEUW); - break; - case 0x3c: /* fbld */ + } + else if(op == 0x3c) /* fbld */ + { gen_update_cc_op(s); gen_jmp_im(s, pc_start - s->cs_base); gen_helper_fbld_ST0(tcg_ctx, cpu_env, cpu_A0); fpu_update_ip(env, pc_start); - break; - case 0x3e: /* fbstp */ + } + else if(op == 0x3e) /* fbstp */ + { gen_update_cc_op(s); gen_jmp_im(s, pc_start - s->cs_base); gen_helper_fbst_ST0(tcg_ctx, cpu_env, cpu_A0); gen_helper_fpop(tcg_ctx, cpu_env); fpu_update_ip(env, pc_start); - break; - case 0x3d: /* fildll */ + } + else if(op == 0x3d) /* fildll */ + { tcg_gen_qemu_ld_i64(s->uc, cpu_tmp1_i64, cpu_A0, s->mem_index, MO_LEQ); gen_helper_fildll_ST0(tcg_ctx, cpu_env, cpu_tmp1_i64); fpu_update_ip(env, pc_start); - break; - case 0x3f: /* fistpll */ + } + else if(op == 0x3f) /* fistpll */ + { gen_helper_fistll_ST0(tcg_ctx, cpu_tmp1_i64, cpu_env); tcg_gen_qemu_st_i64(s->uc, cpu_tmp1_i64, cpu_A0, s->mem_index, MO_LEQ); gen_helper_fpop(tcg_ctx, cpu_env); fpu_update_ip(env, pc_start); - break; - default: + } + else + { goto illegal_op; } } else { @@ -6428,9 +6715,9 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s, break; } break; - case 0x00: case 0x01: case 0x04 ... 0x07: /* fxxx st, sti */ - case 0x20: case 0x21: case 0x24 ... 0x27: /* fxxx sti, st */ - case 0x30: case 0x31: case 0x34 ... 0x37: /* fxxxp sti, st */ + case 0x00: case 0x01: case 0x04: case 0x05: case 0x06: case 0x07: /* fxxx st, sti */ + case 0x20: case 0x21: case 0x24: case 0x25: case 0x26: case 0x27: /* fxxx sti, st */ + case 0x30: case 0x31: case 0x34: case 0x35: case 0x36: case 0x37: /* fxxxp sti, st */ { int op1; @@ -6574,8 +6861,8 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s, gen_helper_fpop(tcg_ctx, cpu_env); set_cc_op(s, CC_OP_EFLAGS); break; - case 0x10 ... 0x13: /* fcmovxx */ - case 0x18 ... 0x1b: + case 0x10: case 0x11: case 0x12: case 0x13: /* fcmovxx */ + case 0x18: case 0x19: case 0x1a: case 0x1b: { int op1, l1; static const uint8_t fcmov_cc[8] = { @@ -6867,10 +7154,14 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s, } gen_jmp(s, tval); break; - case 0x70 ... 0x7f: /* jcc Jb */ + //case 0x70 ... 0x7f: /* jcc Jb */ + case 0x70: case 0x71: case 0x72: case 0x73: case 0x74: case 0x75: case 0x76: case 0x77: + case 0x78: case 0x79: case 0x7a: case 0x7b: case 0x7c: case 0x7d: case 0x7e: case 0x7f: tval = (int8_t)insn_get(env, s, MO_8); goto do_jcc; - case 0x180 ... 0x18f: /* jcc Jv */ + //case 0x180 ... 0x18f: /* jcc Jv */ + case 0x180: case 0x181: case 0x182: case 0x183: case 0x184: case 0x185: case 0x186: case 0x187: + case 0x188: case 0x189: case 0x18a: case 0x18b: case 0x18c: case 0x18d: case 0x18e: case 0x18f: if (dflag != MO_16) { tval = (int32_t)insn_get(env, s, MO_32); } else { @@ -6885,12 +7176,16 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s, gen_jcc(s, b, tval, next_eip); break; - case 0x190 ... 0x19f: /* setcc Gv */ + //case 0x190 ... 0x19f: /* setcc Gv */ + case 0x190: case 0x191: case 0x192: case 0x193: case 0x194: case 0x195: case 0x196: case 0x197: + case 0x198: case 0x199: case 0x19a: case 0x19b: case 0x19c: case 0x19d: case 0x19e: case 0x19f: modrm = cpu_ldub_code(env, s->pc++); gen_setcc1(s, b, *cpu_T[0]); gen_ldst_modrm(env, s, modrm, MO_8, OR_TMP0, 1); break; - case 0x140 ... 0x14f: /* cmov Gv, Ev */ + //case 0x140 ... 0x14f: /* cmov Gv, Ev */ + case 0x140: case 0x141: case 0x142: case 0x143: case 0x144: case 0x145: case 0x146: case 0x147: + case 0x148: case 0x149: case 0x14a: case 0x14b: case 0x14c: case 0x14d: case 0x14e: case 0x14f: if (!(s->cpuid_features & CPUID_CMOV)) { goto illegal_op; } @@ -7094,17 +7389,17 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s, C is the result of the test, Z is unchanged, and the others are all undefined. */ switch (s->cc_op) { - case CC_OP_MULB ... CC_OP_MULQ: - case CC_OP_ADDB ... CC_OP_ADDQ: - case CC_OP_ADCB ... CC_OP_ADCQ: - case CC_OP_SUBB ... CC_OP_SUBQ: - case CC_OP_SBBB ... CC_OP_SBBQ: - case CC_OP_LOGICB ... CC_OP_LOGICQ: - case CC_OP_INCB ... CC_OP_INCQ: - case CC_OP_DECB ... CC_OP_DECQ: - case CC_OP_SHLB ... CC_OP_SHLQ: - case CC_OP_SARB ... CC_OP_SARQ: - case CC_OP_BMILGB ... CC_OP_BMILGQ: + case CC_OP_MULB: case CC_OP_MULW: case CC_OP_MULL: case CC_OP_MULQ: //case CC_OP_MULB ... CC_OP_MULQ: + case CC_OP_ADDB: case CC_OP_ADDW: case CC_OP_ADDL: case CC_OP_ADDQ: //case CC_OP_ADDB ... CC_OP_ADDQ: + case CC_OP_ADCB: case CC_OP_ADCW: case CC_OP_ADCL: case CC_OP_ADCQ: //case CC_OP_ADCB ... CC_OP_ADCQ: + case CC_OP_SUBB: case CC_OP_SUBW: case CC_OP_SUBL: case CC_OP_SUBQ: //case CC_OP_SUBB ... CC_OP_SUBQ: + case CC_OP_SBBB: case CC_OP_SBBW: case CC_OP_SBBL: case CC_OP_SBBQ: //case CC_OP_SBBB ... CC_OP_SBBQ: + case CC_OP_LOGICB: case CC_OP_LOGICW: case CC_OP_LOGICL: case CC_OP_LOGICQ: //case CC_OP_LOGICB ... CC_OP_LOGICQ: + case CC_OP_INCB: case CC_OP_INCW: case CC_OP_INCL: case CC_OP_INCQ: //case CC_OP_INCB ... CC_OP_INCQ: + case CC_OP_DECB: case CC_OP_DECW: case CC_OP_DECL: case CC_OP_DECQ: //case CC_OP_DECB ... CC_OP_DECQ: + case CC_OP_SHLB: case CC_OP_SHLW: case CC_OP_SHLL: case CC_OP_SHLQ: //case CC_OP_SHLB ... CC_OP_SHLQ: + case CC_OP_SARB: case CC_OP_SARW: case CC_OP_SARL: case CC_OP_SARQ: //case CC_OP_SARB ... CC_OP_SARQ: + case CC_OP_BMILGB: case CC_OP_BMILGW: case CC_OP_BMILGL: case CC_OP_BMILGQ: //case CC_OP_BMILGB ... CC_OP_BMILGQ: /* Z was going to be computed from the non-zero status of CC_DST. We can get that same Z value (and the new C value) by leaving CC_DST alone, setting CC_SRC, and using a CC_OP_SAR of the @@ -7337,7 +7632,8 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s, gen_helper_boundl(tcg_ctx, cpu_env, cpu_A0, cpu_tmp2_i32); } break; - case 0x1c8 ... 0x1cf: /* bswap reg */ + case 0x1c8: case 0x1c9: case 0x1ca: case 0x1cb: + case 0x1cc: case 0x1cd: case 0x1ce: case 0x1cf: /* bswap reg */ reg = (b & 7) | REX_B(s); #ifdef TARGET_X86_64 if (dflag == MO_64) { @@ -7942,7 +8238,8 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s, break; } break; - case 0x119 ... 0x11f: /* nop (multi byte) */ + //case 0x119 ... 0x11f: /* nop (multi byte) */ + case 0x119: case 0x11a: case 0x11b: case 0x11c: case 0x11d: case 0x11e: case 0x11f: modrm = cpu_ldub_code(env, s->pc++); gen_nop_modrm(env, s, modrm); break; @@ -8159,17 +8456,30 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s, set_cc_op(s, CC_OP_EFLAGS); break; - case 0x10e ... 0x10f: + case 0x10e: case 0x10f: /* 3DNow! instructions, ignore prefixes */ s->prefix &= ~(PREFIX_REPZ | PREFIX_REPNZ | PREFIX_DATA); - case 0x110 ... 0x117: - case 0x128 ... 0x12f: - case 0x138 ... 0x13a: - case 0x150 ... 0x179: - case 0x17c ... 0x17f: + case 0x110: case 0x111: case 0x112: case 0x113: case 0x114: case 0x115: case 0x116: case 0x117: //case 0x110 ... 0x117: + case 0x128: case 0x129: case 0x12a: case 0x12b: case 0x12c: case 0x12d: case 0x12e: case 0x12f: //case 0x128 ... 0x12f: + case 0x138: case 0x139: case 0x13a: + // case 0x150 ... 0x179: + case 0x150: case 0x151: case 0x152: case 0x153: case 0x154: case 0x155: case 0x156: case 0x157: + case 0x158: case 0x159: case 0x15a: case 0x15b: case 0x15c: case 0x15d: case 0x15e: case 0x15f: + case 0x160: case 0x161: case 0x162: case 0x163: case 0x164: case 0x165: case 0x166: case 0x167: + case 0x168: case 0x169: case 0x16a: case 0x16b: case 0x16c: case 0x16d: case 0x16e: case 0x16f: + case 0x170: case 0x171: case 0x172: case 0x173: case 0x174: case 0x175: case 0x176: case 0x177: + case 0x178: case 0x179: + // case 0x17c ... 0x17f: + case 0x17c: case 0x17d: case 0x17e: case 0x17f: case 0x1c2: - case 0x1c4 ... 0x1c6: - case 0x1d0 ... 0x1fe: + case 0x1c4: case 0x1c5: case 0x1c6: + //case 0x1d0 ... 0x1fe: + case 0x1d0: case 0x1d1: case 0x1d2: case 0x1d3: case 0x1d4: case 0x1d5: case 0x1d6: case 0x1d7: + case 0x1d8: case 0x1d9: case 0x1da: case 0x1db: case 0x1dc: case 0x1dd: case 0x1de: case 0x1df: + case 0x1e0: case 0x1e1: case 0x1e2: case 0x1e3: case 0x1e4: case 0x1e5: case 0x1e6: case 0x1e7: + case 0x1e8: case 0x1e9: case 0x1ea: case 0x1eb: case 0x1ec: case 0x1ed: case 0x1ee: case 0x1ef: + case 0x1f0: case 0x1f1: case 0x1f2: case 0x1f3: case 0x1f4: case 0x1f5: case 0x1f6: case 0x1f7: + case 0x1f8: case 0x1f9: case 0x1fa: case 0x1fb: case 0x1fc: case 0x1fd: case 0x1fe: gen_sse(env, s, b, pc_start, rex_r); break; default: @@ -8214,31 +8524,31 @@ void optimize_flags_init(struct uc_struct *uc) { static const char reg_names[CPU_NB_REGS][4] = { #ifdef TARGET_X86_64 - [R_EAX] = "rax", - [R_EBX] = "rbx", - [R_ECX] = "rcx", - [R_EDX] = "rdx", - [R_ESI] = "rsi", - [R_EDI] = "rdi", - [R_EBP] = "rbp", - [R_ESP] = "rsp", - [8] = "r8", - [9] = "r9", - [10] = "r10", - [11] = "r11", - [12] = "r12", - [13] = "r13", - [14] = "r14", - [15] = "r15", + "rax", + "rcx", + "rdx", + "rbx", + "rsp", + "rbp", + "rsi", + "rdi", + "r8", + "r9", + "r10", + "r11", + "r12", + "r13", + "r14", + "r15", #else - [R_EAX] = "eax", - [R_EBX] = "ebx", - [R_ECX] = "ecx", - [R_EDX] = "edx", - [R_ESI] = "esi", - [R_EDI] = "edi", - [R_EBP] = "ebp", - [R_ESP] = "esp", + "eax", + "ecx", + "edx", + "ebx", + "esp", + "ebp", + "esi", + "edi", #endif }; int i; diff --git a/qemu/target-i386/unicorn.c b/qemu/target-i386/unicorn.c index 5005c2f9..45838697 100644 --- a/qemu/target-i386/unicorn.c +++ b/qemu/target-i386/unicorn.c @@ -150,10 +150,17 @@ int x86_reg_read(struct uc_struct *uc, unsigned int *regs, void **vals, int coun switch(regid) { default: break; - case UC_X86_REG_FP0 ... UC_X86_REG_FP7: + case UC_X86_REG_FP0: + case UC_X86_REG_FP1: + case UC_X86_REG_FP2: + case UC_X86_REG_FP3: + case UC_X86_REG_FP4: + case UC_X86_REG_FP5: + case UC_X86_REG_FP6: + case UC_X86_REG_FP7: { floatx80 reg = X86_CPU(uc, mycpu)->env.fpregs[regid - UC_X86_REG_FP0].d; - cpu_get_fp80(value, value+sizeof(uint64_t), reg); + cpu_get_fp80(value, (uint16_t*)((char*)value+sizeof(uint64_t)), reg); } continue; case UC_X86_REG_FPSW: @@ -197,7 +204,14 @@ int x86_reg_read(struct uc_struct *uc, unsigned int *regs, void **vals, int coun *(uint16_t*) value = fptag; } continue; - case UC_X86_REG_XMM0 ... UC_X86_REG_XMM7: + case UC_X86_REG_XMM0: + case UC_X86_REG_XMM1: + case UC_X86_REG_XMM2: + case UC_X86_REG_XMM3: + case UC_X86_REG_XMM4: + case UC_X86_REG_XMM5: + case UC_X86_REG_XMM6: + case UC_X86_REG_XMM7: { float64 *dst = (float64*)value; XMMReg *reg = &X86_CPU(uc, mycpu)->env.xmm_regs[regid - UC_X86_REG_XMM0]; @@ -234,10 +248,21 @@ int x86_reg_read(struct uc_struct *uc, unsigned int *regs, void **vals, int coun switch(regid) { default: break; - case UC_X86_REG_CR0 ... UC_X86_REG_CR4: + case UC_X86_REG_CR0: + case UC_X86_REG_CR1: + case UC_X86_REG_CR2: + case UC_X86_REG_CR3: + case UC_X86_REG_CR4: *(int32_t *)value = X86_CPU(uc, mycpu)->env.cr[regid - UC_X86_REG_CR0]; break; - case UC_X86_REG_DR0 ... UC_X86_REG_DR7: + case UC_X86_REG_DR0: + case UC_X86_REG_DR1: + case UC_X86_REG_DR2: + case UC_X86_REG_DR3: + case UC_X86_REG_DR4: + case UC_X86_REG_DR5: + case UC_X86_REG_DR6: + case UC_X86_REG_DR7: *(int32_t *)value = X86_CPU(uc, mycpu)->env.dr[regid - UC_X86_REG_DR0]; break; case UC_X86_REG_EFLAGS: @@ -367,10 +392,21 @@ int x86_reg_read(struct uc_struct *uc, unsigned int *regs, void **vals, int coun switch(regid) { default: break; - case UC_X86_REG_CR0 ... UC_X86_REG_CR4: + case UC_X86_REG_CR0: + case UC_X86_REG_CR1: + case UC_X86_REG_CR2: + case UC_X86_REG_CR3: + case UC_X86_REG_CR4: *(int64_t *)value = X86_CPU(uc, mycpu)->env.cr[regid - UC_X86_REG_CR0]; break; - case UC_X86_REG_DR0 ... UC_X86_REG_DR7: + case UC_X86_REG_DR0: + case UC_X86_REG_DR1: + case UC_X86_REG_DR2: + case UC_X86_REG_DR3: + case UC_X86_REG_DR4: + case UC_X86_REG_DR5: + case UC_X86_REG_DR6: + case UC_X86_REG_DR7: *(int64_t *)value = X86_CPU(uc, mycpu)->env.dr[regid - UC_X86_REG_DR0]; break; case UC_X86_REG_EFLAGS: @@ -647,10 +683,17 @@ int x86_reg_write(struct uc_struct *uc, unsigned int *regs, void *const *vals, i switch(regid) { default: break; - case UC_X86_REG_FP0 ... UC_X86_REG_FP7: + case UC_X86_REG_FP0: + case UC_X86_REG_FP1: + case UC_X86_REG_FP2: + case UC_X86_REG_FP3: + case UC_X86_REG_FP4: + case UC_X86_REG_FP5: + case UC_X86_REG_FP6: + case UC_X86_REG_FP7: { uint64_t mant = *(uint64_t*) value; - uint16_t upper = *(uint16_t*) (value + sizeof(uint64_t)); + uint16_t upper = *(uint16_t*) ((char*)value + sizeof(uint64_t)); X86_CPU(uc, mycpu)->env.fpregs[regid - UC_X86_REG_FP0].d = cpu_set_fp80(mant, upper); } continue; @@ -676,7 +719,14 @@ int x86_reg_write(struct uc_struct *uc, unsigned int *regs, void *const *vals, i continue; } break; - case UC_X86_REG_XMM0 ... UC_X86_REG_XMM7: + case UC_X86_REG_XMM0: + case UC_X86_REG_XMM1: + case UC_X86_REG_XMM2: + case UC_X86_REG_XMM3: + case UC_X86_REG_XMM4: + case UC_X86_REG_XMM5: + case UC_X86_REG_XMM6: + case UC_X86_REG_XMM7: { float64 *src = (float64*)value; XMMReg *reg = &X86_CPU(uc, mycpu)->env.xmm_regs[regid - UC_X86_REG_XMM0]; @@ -714,10 +764,21 @@ int x86_reg_write(struct uc_struct *uc, unsigned int *regs, void *const *vals, i switch(regid) { default: break; - case UC_X86_REG_CR0 ... UC_X86_REG_CR4: + case UC_X86_REG_CR0: + case UC_X86_REG_CR1: + case UC_X86_REG_CR2: + case UC_X86_REG_CR3: + case UC_X86_REG_CR4: X86_CPU(uc, mycpu)->env.cr[regid - UC_X86_REG_CR0] = *(uint32_t *)value; break; - case UC_X86_REG_DR0 ... UC_X86_REG_DR7: + case UC_X86_REG_DR0: + case UC_X86_REG_DR1: + case UC_X86_REG_DR2: + case UC_X86_REG_DR3: + case UC_X86_REG_DR4: + case UC_X86_REG_DR5: + case UC_X86_REG_DR6: + case UC_X86_REG_DR7: X86_CPU(uc, mycpu)->env.dr[regid - UC_X86_REG_DR0] = *(uint32_t *)value; break; case UC_X86_REG_EFLAGS: @@ -854,10 +915,21 @@ int x86_reg_write(struct uc_struct *uc, unsigned int *regs, void *const *vals, i switch(regid) { default: break; - case UC_X86_REG_CR0 ... UC_X86_REG_CR4: + case UC_X86_REG_CR0: + case UC_X86_REG_CR1: + case UC_X86_REG_CR2: + case UC_X86_REG_CR3: + case UC_X86_REG_CR4: X86_CPU(uc, mycpu)->env.cr[regid - UC_X86_REG_CR0] = *(uint64_t *)value; break; - case UC_X86_REG_DR0 ... UC_X86_REG_DR7: + case UC_X86_REG_DR0: + case UC_X86_REG_DR1: + case UC_X86_REG_DR2: + case UC_X86_REG_DR3: + case UC_X86_REG_DR4: + case UC_X86_REG_DR5: + case UC_X86_REG_DR6: + case UC_X86_REG_DR7: X86_CPU(uc, mycpu)->env.dr[regid - UC_X86_REG_DR0] = *(uint64_t *)value; break; case UC_X86_REG_EFLAGS: @@ -1133,7 +1205,7 @@ int x86_reg_write(struct uc_struct *uc, unsigned int *regs, void *const *vals, i return 0; } -__attribute__ ((visibility ("default"))) +DEFAULT_VISIBILITY int x86_uc_machine_init(struct uc_struct *uc) { return machine_initialize(uc); @@ -1151,7 +1223,7 @@ static bool x86_stop_interrupt(int intno) void pc_machine_init(struct uc_struct *uc); -__attribute__ ((visibility ("default"))) +DEFAULT_VISIBILITY void x86_uc_init(struct uc_struct* uc) { apic_register_types(uc); diff --git a/qemu/target-m68k/m68k-semi.c b/qemu/target-m68k/m68k-semi.c index 8be5714c..4087c6d5 100644 --- a/qemu/target-m68k/m68k-semi.c +++ b/qemu/target-m68k/m68k-semi.c @@ -21,10 +21,9 @@ #include #include #include -#include +#include "platform.h" #include #include -#include #include #include "cpu.h" diff --git a/qemu/target-m68k/unicorn.c b/qemu/target-m68k/unicorn.c index 18befef0..0eb30b84 100644 --- a/qemu/target-m68k/unicorn.c +++ b/qemu/target-m68k/unicorn.c @@ -105,7 +105,7 @@ int m68k_reg_write(struct uc_struct *uc, unsigned int *regs, void *const *vals, return 0; } -__attribute__ ((visibility ("default"))) +DEFAULT_VISIBILITY void m68k_uc_init(struct uc_struct* uc) { register_accel_types(uc); diff --git a/qemu/target-mips/helper.c b/qemu/target-mips/helper.c index dca4416a..4dba9ff7 100644 --- a/qemu/target-mips/helper.c +++ b/qemu/target-mips/helper.c @@ -20,7 +20,7 @@ #include #include #include -#include +#include "platform.h" #include #include "cpu.h" diff --git a/qemu/target-mips/unicorn.c b/qemu/target-mips/unicorn.c index 3ca24390..43c98049 100644 --- a/qemu/target-mips/unicorn.c +++ b/qemu/target-mips/unicorn.c @@ -124,7 +124,7 @@ int mips_reg_write(struct uc_struct *uc, unsigned int *regs, void *const *vals, return 0; } -__attribute__ ((visibility ("default"))) +DEFAULT_VISIBILITY #ifdef TARGET_MIPS64 #ifdef TARGET_WORDS_BIGENDIAN void mips64_uc_init(struct uc_struct* uc) diff --git a/qemu/target-sparc/translate.c b/qemu/target-sparc/translate.c index f1e1c801..b974fa21 100644 --- a/qemu/target-sparc/translate.c +++ b/qemu/target-sparc/translate.c @@ -22,7 +22,7 @@ #include #include #include -#include +#include "platform.h" #include "cpu.h" #include "exec/helper-proto.h" diff --git a/qemu/target-sparc/unicorn.c b/qemu/target-sparc/unicorn.c index 354d48ca..8db2b52e 100644 --- a/qemu/target-sparc/unicorn.c +++ b/qemu/target-sparc/unicorn.c @@ -135,7 +135,7 @@ int sparc_reg_write(struct uc_struct *uc, unsigned int *regs, void *const *vals, return 0; } -__attribute__ ((visibility ("default"))) +DEFAULT_VISIBILITY void sparc_uc_init(struct uc_struct* uc) { register_accel_types(uc); diff --git a/qemu/target-sparc/unicorn64.c b/qemu/target-sparc/unicorn64.c index 8b58cad1..e6f07a33 100644 --- a/qemu/target-sparc/unicorn64.c +++ b/qemu/target-sparc/unicorn64.c @@ -100,7 +100,7 @@ int sparc_reg_write(struct uc_struct *uc, unsigned int *regs, void* const* vals, return 0; } -__attribute__ ((visibility ("default"))) +DEFAULT_VISIBILITY void sparc64_uc_init(struct uc_struct* uc) { register_accel_types(uc); diff --git a/qemu/tcg-runtime.c b/qemu/tcg-runtime.c index 9daba694..b9935910 100644 --- a/qemu/tcg-runtime.c +++ b/qemu/tcg-runtime.c @@ -21,7 +21,7 @@ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN * THE SOFTWARE. */ -#include +#include "platform.h" #include "qemu/host-utils.h" /* This file is compiled once, and thus we can't include the standard diff --git a/qemu/tcg/arm/tcg-target.c b/qemu/tcg/arm/tcg-target.c index 17289d92..da11ac00 100644 --- a/qemu/tcg/arm/tcg-target.c +++ b/qemu/tcg/arm/tcg-target.c @@ -1464,7 +1464,7 @@ static inline void tcg_out_qemu_ld_direct(TCGContext *s, TCGMemOp opc, static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, bool is64) { - TCGReg addrlo, datalo, datahi, addrhi __attribute__((unused)); + TCGReg addrlo, datalo, datahi, addrhi QEMU_UNUSED_VAR; TCGMemOp opc; #ifdef CONFIG_SOFTMMU int mem_index; @@ -1593,7 +1593,7 @@ static inline void tcg_out_qemu_st_direct(TCGContext *s, TCGMemOp opc, static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, bool is64) { - TCGReg addrlo, datalo, datahi, addrhi __attribute__((unused)); + TCGReg addrlo, datalo, datahi, addrhi QEMU_UNUQEMU_UNUSED_VARSED; TCGMemOp opc; #ifdef CONFIG_SOFTMMU int mem_index; diff --git a/qemu/tcg/i386/tcg-target.c b/qemu/tcg/i386/tcg-target.c index 414c4a72..741b957a 100644 --- a/qemu/tcg/i386/tcg-target.c +++ b/qemu/tcg/i386/tcg-target.c @@ -77,7 +77,13 @@ static const int tcg_target_call_iarg_regs[] = { TCG_REG_R8, TCG_REG_R9, #else - /* 32 bit mode uses stack based calling convention (GCC default). */ + /* 32 bit mode uses stack based calling convention (GCC default). + We add a dummy value here for MSVC compatibility for the error: + "error C2466: cannot allocate an array of constant size 0" + The "tcg_target_call_iarg_regs" array is not accessed when + TCG_TARGET_REG_BITS == 32 + */ + 0, #endif }; @@ -108,8 +114,19 @@ static const int tcg_target_call_oarg_regs[] = { detection, as we're not going to go so far as our own inline assembly. If not available, default values will be assumed. */ #if defined(CONFIG_CPUID_H) +#ifdef _MSC_VER +#include +/* %ecx */ +#define bit_MOVBE (1 << 22) +/* %edx */ +#define bit_CMOV (1 << 15) +/* Extended Features (%eax == 7) */ +#define bit_BMI (1 << 3) +#define bit_BMI2 (1 << 8) +#else #include #endif +#endif /* For 32-bit, we are going to attempt to determine at runtime whether cmov is available. */ @@ -393,7 +410,25 @@ static inline int tcg_target_const_match(tcg_target_long val, TCGType type, #define JCC_JG 0xf static const uint8_t tcg_cond_to_jcc[] = { - [TCG_COND_EQ] = JCC_JE, +#ifdef _MSC_VER + 0, // TCG_COND_NEVER + 0, // TCG_COND_ALWAYS + JCC_JL, // TCG_COND_LT + JCC_JGE, // TCG_COND_GE + JCC_JB, // TCG_COND_LTU + JCC_JAE, // TCG_COND_GEU + 0, // n/a + 0, // n/a + JCC_JE, // TCG_COND_EQ + JCC_JNE, // TCG_COND_NE + JCC_JLE, // TCG_COND_LE + JCC_JG, // TCG_COND_GT + JCC_JBE, // TCG_COND_LEU + JCC_JA, // TCG_COND_GTU + 0, // n/a + 0, // n/a +#else + [TCG_COND_EQ] = JCC_JE, [TCG_COND_NE] = JCC_JNE, [TCG_COND_LT] = JCC_JL, [TCG_COND_GE] = JCC_JGE, @@ -403,6 +438,7 @@ static const uint8_t tcg_cond_to_jcc[] = { [TCG_COND_GEU] = JCC_JAE, [TCG_COND_LEU] = JCC_JBE, [TCG_COND_GTU] = JCC_JA, +#endif }; #if TCG_TARGET_REG_BITS == 64 @@ -843,7 +879,7 @@ static void tcg_out_addi(TCGContext *s, int reg, tcg_target_long val) } /* Use SMALL != 0 to force a short forward branch. */ -static void tcg_out_jxx(TCGContext *s, int opc, int label_index, int small) +static void tcg_out_jxx(TCGContext *s, int opc, int label_index, int smallflag) { int32_t val, val1; TCGLabel *l = &s->labels[label_index]; @@ -859,7 +895,7 @@ static void tcg_out_jxx(TCGContext *s, int opc, int label_index, int small) } tcg_out8(s, val1); } else { - if (small) { + if (smallflag) { tcg_abort(); } if (opc == -1) { @@ -870,7 +906,7 @@ static void tcg_out_jxx(TCGContext *s, int opc, int label_index, int small) tcg_out32(s, val - 6); } } - } else if (small) { + } else if (smallflag) { if (opc == -1) { tcg_out8(s, OPC_JMP_short); } else { @@ -906,25 +942,25 @@ static void tcg_out_cmp(TCGContext *s, TCGArg arg1, TCGArg arg2, static void tcg_out_brcond32(TCGContext *s, TCGCond cond, TCGArg arg1, TCGArg arg2, int const_arg2, - int label_index, int small) + int label_index, int smallflag) { tcg_out_cmp(s, arg1, arg2, const_arg2, 0); - tcg_out_jxx(s, tcg_cond_to_jcc[cond], label_index, small); + tcg_out_jxx(s, tcg_cond_to_jcc[cond], label_index, smallflag); } #if TCG_TARGET_REG_BITS == 64 static void tcg_out_brcond64(TCGContext *s, TCGCond cond, TCGArg arg1, TCGArg arg2, int const_arg2, - int label_index, int small) + int label_index, int smallflag) { tcg_out_cmp(s, arg1, arg2, const_arg2, P_REXW); - tcg_out_jxx(s, tcg_cond_to_jcc[cond], label_index, small); + tcg_out_jxx(s, tcg_cond_to_jcc[cond], label_index, smallflag); } #else /* XXX: we implement it at the target level to avoid having to handle cross basic blocks temporaries */ static void tcg_out_brcond2(TCGContext *s, const TCGArg *args, - const int *const_args, int small) + const int *const_args, int smallflag) { int label_next; label_next = gen_new_label(s); @@ -933,69 +969,69 @@ static void tcg_out_brcond2(TCGContext *s, const TCGArg *args, tcg_out_brcond32(s, TCG_COND_NE, args[0], args[2], const_args[2], label_next, 1); tcg_out_brcond32(s, TCG_COND_EQ, args[1], args[3], const_args[3], - args[5], small); + args[5], smallflag); break; case TCG_COND_NE: tcg_out_brcond32(s, TCG_COND_NE, args[0], args[2], const_args[2], - args[5], small); + args[5], smallflag); tcg_out_brcond32(s, TCG_COND_NE, args[1], args[3], const_args[3], - args[5], small); + args[5], smallflag); break; case TCG_COND_LT: tcg_out_brcond32(s, TCG_COND_LT, args[1], args[3], const_args[3], - args[5], small); + args[5], smallflag); tcg_out_jxx(s, JCC_JNE, label_next, 1); tcg_out_brcond32(s, TCG_COND_LTU, args[0], args[2], const_args[2], - args[5], small); + args[5], smallflag); break; case TCG_COND_LE: tcg_out_brcond32(s, TCG_COND_LT, args[1], args[3], const_args[3], - args[5], small); + args[5], smallflag); tcg_out_jxx(s, JCC_JNE, label_next, 1); tcg_out_brcond32(s, TCG_COND_LEU, args[0], args[2], const_args[2], - args[5], small); + args[5], smallflag); break; case TCG_COND_GT: tcg_out_brcond32(s, TCG_COND_GT, args[1], args[3], const_args[3], - args[5], small); + args[5], smallflag); tcg_out_jxx(s, JCC_JNE, label_next, 1); tcg_out_brcond32(s, TCG_COND_GTU, args[0], args[2], const_args[2], - args[5], small); + args[5], smallflag); break; case TCG_COND_GE: tcg_out_brcond32(s, TCG_COND_GT, args[1], args[3], const_args[3], - args[5], small); + args[5], smallflag); tcg_out_jxx(s, JCC_JNE, label_next, 1); tcg_out_brcond32(s, TCG_COND_GEU, args[0], args[2], const_args[2], - args[5], small); + args[5], smallflag); break; case TCG_COND_LTU: tcg_out_brcond32(s, TCG_COND_LTU, args[1], args[3], const_args[3], - args[5], small); + args[5], smallflag); tcg_out_jxx(s, JCC_JNE, label_next, 1); tcg_out_brcond32(s, TCG_COND_LTU, args[0], args[2], const_args[2], - args[5], small); + args[5], smallflag); break; case TCG_COND_LEU: tcg_out_brcond32(s, TCG_COND_LTU, args[1], args[3], const_args[3], - args[5], small); + args[5], smallflag); tcg_out_jxx(s, JCC_JNE, label_next, 1); tcg_out_brcond32(s, TCG_COND_LEU, args[0], args[2], const_args[2], - args[5], small); + args[5], smallflag); break; case TCG_COND_GTU: tcg_out_brcond32(s, TCG_COND_GTU, args[1], args[3], const_args[3], - args[5], small); + args[5], smallflag); tcg_out_jxx(s, JCC_JNE, label_next, 1); tcg_out_brcond32(s, TCG_COND_GTU, args[0], args[2], const_args[2], - args[5], small); + args[5], smallflag); break; case TCG_COND_GEU: tcg_out_brcond32(s, TCG_COND_GTU, args[1], args[3], const_args[3], - args[5], small); + args[5], smallflag); tcg_out_jxx(s, JCC_JNE, label_next, 1); tcg_out_brcond32(s, TCG_COND_GEU, args[0], args[2], const_args[2], - args[5], small); + args[5], smallflag); break; default: tcg_abort(); @@ -1118,19 +1154,94 @@ static void tcg_out_jmp(TCGContext *s, tcg_insn_unit *dest) * int mmu_idx, uintptr_t ra) */ static void * const qemu_ld_helpers[16] = { - [MO_UB] = helper_ret_ldub_mmu, +#ifdef _MSC_VER + helper_ret_ldub_mmu, // MO_UB +# ifdef HOST_WORDS_BIGENDIAN + helper_be_lduw_mmu, // MO_BEUW + helper_be_ldul_mmu, // MO_BEUL + helper_be_ldq_mmu, // MO_BEQ + 0, // MO_SB + 0, // MO_BESW + 0, // MO_BESL + 0, // n/a + 0, // n/a + helper_le_lduw_mmu, // MO_LEUW + helper_le_ldul_mmu, // MO_LEUL + helper_le_ldq_mmu, // MO_LEQ + 0, // n/a + 0, // MO_LESW + 0, // MO_LESL + 0, // n/a +# else // !HOST_WORDS_BIGENDIAN + helper_le_lduw_mmu, // MO_LEUW + helper_le_ldul_mmu, // MO_LEUL + helper_le_ldq_mmu, // MO_LEQ + 0, // MO_SB + 0, // MO_LESW + 0, // MO_LESL + 0, // n/a + 0, // n/a + helper_be_lduw_mmu, // MO_BEUW + helper_be_ldul_mmu, // MO_BEUL + helper_be_ldq_mmu, // MO_BEQ + 0, // n/a + 0, // MO_BESW + 0, // MO_BESL + 0, // n/a +# endif // HOST_WORDS_BIGENDIAN + +#else //_MSC_VER + [MO_UB] = helper_ret_ldub_mmu, [MO_LEUW] = helper_le_lduw_mmu, [MO_LEUL] = helper_le_ldul_mmu, [MO_LEQ] = helper_le_ldq_mmu, [MO_BEUW] = helper_be_lduw_mmu, [MO_BEUL] = helper_be_ldul_mmu, [MO_BEQ] = helper_be_ldq_mmu, +#endif // _MSC_VER }; /* helper signature: helper_ret_st_mmu(CPUState *env, target_ulong addr, * uintxx_t val, int mmu_idx, uintptr_t ra) */ static void * const qemu_st_helpers[16] = { +#ifdef _MSC_VER + helper_ret_stb_mmu, // MO_UB +# ifdef HOST_WORDS_BIGENDIAN + helper_be_stw_mmu, // MO_BEUW + helper_be_stl_mmu, // MO_BEUL + helper_be_stq_mmu, // MO_BEQ + 0, // MO_SB + 0, // MO_BESW + 0, // MO_BESL + 0, // n/a + 0, // n/a + helper_le_stw_mmu, // MO_LEUW + helper_le_stl_mmu, // MO_LEUL + helper_le_stq_mmu, // MO_LEQ + 0, // n/a + 0, // MO_LESW + 0, // MO_LESL + 0, // n/a +# else // !HOST_WORDS_BIGENDIAN + helper_le_stw_mmu, // MO_LEUW + helper_le_stl_mmu, // MO_LEUL + helper_le_stq_mmu, // MO_LEQ + 0, // MO_SB + 0, // MO_LESW + 0, // MO_LESL + 0, // n/a + 0, // n/a + helper_be_stw_mmu, // MO_BEUW + helper_be_stl_mmu, // MO_BEUL + helper_be_stq_mmu, // MO_BEQ + 0, // n/a + 0, // MO_BESW + 0, // MO_BESL + 0, // n/a +# endif // HOST_WORDS_BIGENDIAN + +#else //_MSC_VER [MO_UB] = helper_ret_stb_mmu, [MO_LEUW] = helper_le_stw_mmu, [MO_LEUL] = helper_le_stl_mmu, @@ -1138,6 +1249,7 @@ static void * const qemu_st_helpers[16] = { [MO_BEUW] = helper_be_stw_mmu, [MO_BEUL] = helper_be_stl_mmu, [MO_BEQ] = helper_be_stq_mmu, +#endif // _MSC_VER }; /* Perform the TLB load and compare. @@ -1521,7 +1633,7 @@ static void tcg_out_qemu_ld_direct(TCGContext *s, TCGReg datalo, TCGReg datahi, static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, bool is64) { TCGReg datalo, datahi, addrlo; - TCGReg addrhi __attribute__((unused)); + TCGReg addrhi QEMU_UNUSED_VAR; TCGMemOp opc; #if defined(CONFIG_SOFTMMU) int mem_index; @@ -1652,7 +1764,7 @@ static void tcg_out_qemu_st_direct(TCGContext *s, TCGReg datalo, TCGReg datahi, static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, bool is64) { TCGReg datalo, datahi, addrlo; - TCGReg addrhi __attribute__((unused)); + TCGReg addrhi QEMU_UNUSED_VAR; TCGMemOp opc; #if defined(CONFIG_SOFTMMU) int mem_index; @@ -2059,9 +2171,9 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc, } static const TCGTargetOpDef x86_op_defs[] = { - { INDEX_op_exit_tb, { } }, - { INDEX_op_goto_tb, { } }, - { INDEX_op_br, { } }, + { INDEX_op_exit_tb, { NULL } }, + { INDEX_op_goto_tb, { NULL } }, + { INDEX_op_br, { NULL } }, { INDEX_op_ld8u_i32, { "r", "r" } }, { INDEX_op_ld8s_i32, { "r", "r" } }, { INDEX_op_ld16u_i32, { "r", "r" } }, @@ -2275,10 +2387,26 @@ static void tcg_target_init(TCGContext *s) { #ifdef CONFIG_CPUID_H unsigned a, b, c, d; - int max = __get_cpuid_max(0, 0); + int max; + +#ifdef _MSC_VER + int cpu_info[4]; + __cpuid(cpu_info, 0); + max = cpu_info[0]; +#else + max = __get_cpuid_max(0, 0); +#endif if (max >= 1) { +#ifdef _MSC_VER + __cpuid(cpu_info, 1); + a = cpu_info[0]; + b = cpu_info[1]; + c = cpu_info[2]; + d = cpu_info[3]; +#else __cpuid(1, a, b, c, d); +#endif #ifndef have_cmov /* For 32-bit, 99% certainty that we're running on hardware that supports cmov, but we still need to check. In case cmov is not @@ -2294,7 +2422,11 @@ static void tcg_target_init(TCGContext *s) if (max >= 7) { /* BMI1 is available on AMD Piledriver and Intel Haswell CPUs. */ +#ifdef _MSC_VER + __cpuidex(cpu_info, 7, 0); +#else __cpuid_count(7, 0, a, b, c, d); +#endif #ifdef bit_BMI have_bmi1 = (b & bit_BMI) != 0; #endif diff --git a/qemu/tcg/ia64/tcg-target.h b/qemu/tcg/ia64/tcg-target.h index d6755898..b8b2693f 100644 --- a/qemu/tcg/ia64/tcg-target.h +++ b/qemu/tcg/ia64/tcg-target.h @@ -27,7 +27,7 @@ #define TCG_TARGET_INSN_UNIT_SIZE 16 typedef struct { - uint64_t lo __attribute__((aligned(16))); + uint64_t QEMU_ALIGN(16, lo); uint64_t hi; } tcg_insn_unit; diff --git a/qemu/tcg/mips/tcg-target.c b/qemu/tcg/mips/tcg-target.c index 0adf88fc..3b53bb7b 100644 --- a/qemu/tcg/mips/tcg-target.c +++ b/qemu/tcg/mips/tcg-target.c @@ -1150,7 +1150,7 @@ static void tcg_out_qemu_ld_direct(TCGContext *s, TCGReg datalo, TCGReg datahi, static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, bool is_64) { - TCGReg addr_regl, addr_regh __attribute__((unused)); + TCGReg addr_regl, addr_regh QEMU_UNUSED_VAR; TCGReg data_regl, data_regh; TCGMemOp opc; #if defined(CONFIG_SOFTMMU) @@ -1279,7 +1279,7 @@ static void tcg_out_addsub2(TCGContext *s, TCGReg rl, TCGReg rh, TCGReg al, static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, bool is_64) { - TCGReg addr_regl, addr_regh __attribute__((unused)); + TCGReg addr_regl, addr_regh QEMU_UNUSED_VAR; TCGReg data_regl, data_regh, base; TCGMemOp opc; #if defined(CONFIG_SOFTMMU) diff --git a/qemu/tcg/optimize.c b/qemu/tcg/optimize.c index 3fad5bf9..d525f15b 100644 --- a/qemu/tcg/optimize.c +++ b/qemu/tcg/optimize.c @@ -105,13 +105,13 @@ static TCGArg find_better_copy(TCGContext *s, TCGArg temp) TCGArg i; /* If this is already a global, we can't do better. */ - if (temp < s->nb_globals) { + if (temp < (unsigned int)s->nb_globals) { return temp; } /* Search for a global first. */ for (i = temps[temp].next_copy ; i != temp ; i = temps[i].next_copy) { - if (i < s->nb_globals) { + if (i < (unsigned int)s->nb_globals) { return i; } } @@ -257,19 +257,19 @@ static TCGArg do_constant_folding_2(TCGOpcode op, TCGArg x, TCGArg y) return ror32(x, y & 31); case INDEX_op_rotr_i64: - return ror64(x, y & 63); + return (TCGArg)ror64(x, y & 63); case INDEX_op_rotl_i32: return rol32(x, y & 31); case INDEX_op_rotl_i64: - return rol64(x, y & 63); + return (TCGArg)rol64(x, y & 63); CASE_OP_32_64(not): return ~x; CASE_OP_32_64(neg): - return -x; + return 0-x; CASE_OP_32_64(andc): return x & ~y; @@ -311,29 +311,29 @@ static TCGArg do_constant_folding_2(TCGOpcode op, TCGArg x, TCGArg y) case INDEX_op_muluh_i64: mulu64(&l64, &h64, x, y); - return h64; + return (TCGArg)h64; case INDEX_op_mulsh_i64: muls64(&l64, &h64, x, y); - return h64; + return (TCGArg)h64; case INDEX_op_div_i32: /* Avoid crashing on divide by zero, otherwise undefined. */ - return (int32_t)x / ((int32_t)y ? : 1); + return (int32_t)x / ((int32_t)y ? (int32_t)y : 1); case INDEX_op_divu_i32: - return (uint32_t)x / ((uint32_t)y ? : 1); + return (uint32_t)x / ((uint32_t)y ? (uint32_t)y : 1); case INDEX_op_div_i64: - return (int64_t)x / ((int64_t)y ? : 1); + return (int64_t)x / ((int64_t)y ? (int64_t)y : 1); case INDEX_op_divu_i64: - return (uint64_t)x / ((uint64_t)y ? : 1); + return (uint64_t)x / ((uint64_t)y ? (uint64_t)y : 1); case INDEX_op_rem_i32: - return (int32_t)x % ((int32_t)y ? : 1); + return (int32_t)x % ((int32_t)y ? (int32_t)y : 1); case INDEX_op_remu_i32: - return (uint32_t)x % ((uint32_t)y ? : 1); + return (uint32_t)x % ((uint32_t)y ? (uint32_t)y : 1); case INDEX_op_rem_i64: - return (int64_t)x % ((int64_t)y ? : 1); + return (int64_t)x % ((int64_t)y ? (int64_t)y : 1); case INDEX_op_remu_i64: - return (uint64_t)x % ((uint64_t)y ? : 1); + return (uint64_t)x % ((uint64_t)y ? (uint64_t)y : 1); default: fprintf(stderr, @@ -867,11 +867,11 @@ static TCGArg *tcg_constant_folding(TCGContext *s, uint16_t *tcg_opc_ptr, CASE_OP_32_64(neg): /* Set to 1 all bits to the left of the rightmost. */ - mask = -(temps[args[1]].mask & -temps[args[1]].mask); + mask = 0-(temps[args[1]].mask & (0-temps[args[1]].mask)); break; CASE_OP_32_64(deposit): - mask = deposit64(temps[args[1]].mask, args[3], args[4], + mask = (tcg_target_ulong)deposit64(temps[args[1]].mask, args[3], args[4], temps[args[2]].mask); break; @@ -1088,7 +1088,7 @@ static TCGArg *tcg_constant_folding(TCGContext *s, uint16_t *tcg_opc_ptr, CASE_OP_32_64(deposit): if (temps[args[1]].state == TCG_TEMP_CONST && temps[args[2]].state == TCG_TEMP_CONST) { - tmp = deposit64(temps[args[1]].val, args[3], args[4], + tmp = (TCGArg)deposit64(temps[args[1]].val, args[3], args[4], temps[args[2]].val); tcg_opt_gen_movi(s, op_index, gen_args, op, args[0], tmp); gen_args += 2; diff --git a/qemu/tcg/ppc/tcg-target.c b/qemu/tcg/ppc/tcg-target.c index c713345d..cd7aabd4 100644 --- a/qemu/tcg/ppc/tcg-target.c +++ b/qemu/tcg/ppc/tcg-target.c @@ -1576,7 +1576,7 @@ static void tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *lb) static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, bool is_64) { TCGReg datalo, datahi, addrlo, rbase; - TCGReg addrhi __attribute__((unused)); + TCGReg addrhi QEMU_UNUSED_VAR; TCGMemOp opc, s_bits; #ifdef CONFIG_SOFTMMU int mem_index; @@ -1649,7 +1649,7 @@ static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, bool is_64) static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, bool is_64) { TCGReg datalo, datahi, addrlo, rbase; - TCGReg addrhi __attribute__((unused)); + TCGReg addrhi QEMU_UNUSED_VAR; TCGMemOp opc, s_bits; #ifdef CONFIG_SOFTMMU int mem_index; @@ -2603,14 +2603,14 @@ void flush_icache_range(uintptr_t start, uintptr_t stop) #if defined _AIX #include -static void __attribute__((constructor)) tcg_cache_init(void) +INITIALIZER(tcg_cache_init) { icache_bsize = _system_configuration.icache_line; dcache_bsize = _system_configuration.dcache_line; } #elif defined __linux__ -static void __attribute__((constructor)) tcg_cache_init(void) +INITIALIZER(tcg_cache_init) { unsigned long dsize = qemu_getauxval(AT_DCACHEBSIZE); unsigned long isize = qemu_getauxval(AT_ICACHEBSIZE); @@ -2633,7 +2633,7 @@ static void __attribute__((constructor)) tcg_cache_init(void) #include #include -static void __attribute__((constructor)) tcg_cache_init(void) +INITIALIZER(tcg_cache_init) { size_t len; unsigned cacheline; @@ -2656,7 +2656,7 @@ static void __attribute__((constructor)) tcg_cache_init(void) #include #include -static void __attribute__((constructor)) tcg_cache_init(void) +INITIALIZER(tcg_cache_init) { size_t len = 4; unsigned cacheline; diff --git a/qemu/tcg/sparc/tcg-target.h b/qemu/tcg/sparc/tcg-target.h index 0c4c8af0..f24dad04 100644 --- a/qemu/tcg/sparc/tcg-target.h +++ b/qemu/tcg/sparc/tcg-target.h @@ -148,12 +148,20 @@ extern bool use_vis3_instructions; #define TCG_AREG0 TCG_REG_I0 +#ifdef _MSC_VER +#include static inline void flush_icache_range(uintptr_t start, uintptr_t stop) { - uintptr_t p; + FlushInstructionCache(GetCurrentProcess(), (const void*)start, stop-start); +} +#else +static inline void flush_icache_range(uintptr_t start, uintptr_t stop) +{ + uintptr_t p; for (p = start & -8; p < ((stop + 7) & -8); p += 8) { __asm__ __volatile__("flush\t%0" : : "r" (p)); } } +#endif #endif diff --git a/qemu/tcg/tcg-be-null.h b/qemu/tcg/tcg-be-null.h index 74c57d5a..ba2da3c5 100644 --- a/qemu/tcg/tcg-be-null.h +++ b/qemu/tcg/tcg-be-null.h @@ -20,6 +20,8 @@ * THE SOFTWARE. */ +#include "tcg.h" + typedef struct TCGBackendData { /* Empty */ char dummy; diff --git a/qemu/tcg/tcg-op.h b/qemu/tcg/tcg-op.h index 87358240..5d2edee5 100644 --- a/qemu/tcg/tcg-op.h +++ b/qemu/tcg/tcg-op.h @@ -747,7 +747,7 @@ static inline void tcg_gen_mov_i64(TCGContext *s, TCGv_i64 ret, TCGv_i64 arg) static inline void tcg_gen_movi_i64(TCGContext *s, TCGv_i64 ret, int64_t arg) { - tcg_gen_movi_i32(s, TCGV_LOW(ret), arg); + tcg_gen_movi_i32(s, TCGV_LOW(ret), (int32_t)arg); tcg_gen_movi_i32(s, TCGV_HIGH(ret), arg >> 32); } @@ -863,7 +863,7 @@ static inline void tcg_gen_and_i64(TCGContext *s, TCGv_i64 ret, TCGv_i64 arg1, T static inline void tcg_gen_andi_i64(TCGContext *s, TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2) { - tcg_gen_andi_i32(s, TCGV_LOW(ret), TCGV_LOW(arg1), arg2); + tcg_gen_andi_i32(s, TCGV_LOW(ret), TCGV_LOW(arg1), (uint32_t)arg2); tcg_gen_andi_i32(s, TCGV_HIGH(ret), TCGV_HIGH(arg1), arg2 >> 32); } @@ -875,7 +875,7 @@ static inline void tcg_gen_or_i64(TCGContext *s, TCGv_i64 ret, TCGv_i64 arg1, TC static inline void tcg_gen_ori_i64(TCGContext *s, TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2) { - tcg_gen_ori_i32(s, TCGV_LOW(ret), TCGV_LOW(arg1), arg2); + tcg_gen_ori_i32(s, TCGV_LOW(ret), TCGV_LOW(arg1), (uint32_t)arg2); tcg_gen_ori_i32(s, TCGV_HIGH(ret), TCGV_HIGH(arg1), arg2 >> 32); } @@ -887,7 +887,7 @@ static inline void tcg_gen_xor_i64(TCGContext *s, TCGv_i64 ret, TCGv_i64 arg1, T static inline void tcg_gen_xori_i64(TCGContext *s, TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2) { - tcg_gen_xori_i32(s, TCGV_LOW(ret), TCGV_LOW(arg1), arg2); + tcg_gen_xori_i32(s, TCGV_LOW(ret), TCGV_LOW(arg1), (int32_t)arg2); tcg_gen_xori_i32(s, TCGV_HIGH(ret), TCGV_HIGH(arg1), arg2 >> 32); } @@ -900,7 +900,7 @@ static inline void tcg_gen_shl_i64(TCGContext *s, TCGv_i64 ret, TCGv_i64 arg1, T static inline void tcg_gen_shli_i64(TCGContext *s, TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2) { - tcg_gen_shifti_i64(s, ret, arg1, arg2, 0, 0); + tcg_gen_shifti_i64(s, ret, arg1, (int)arg2, 0, 0); } static inline void tcg_gen_shr_i64(TCGContext *s, TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) @@ -910,7 +910,7 @@ static inline void tcg_gen_shr_i64(TCGContext *s, TCGv_i64 ret, TCGv_i64 arg1, T static inline void tcg_gen_shri_i64(TCGContext *s, TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2) { - tcg_gen_shifti_i64(s, ret, arg1, arg2, 1, 0); + tcg_gen_shifti_i64(s, ret, arg1, (int)arg2, 1, 0); } static inline void tcg_gen_sar_i64(TCGContext *s, TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) @@ -920,7 +920,7 @@ static inline void tcg_gen_sar_i64(TCGContext *s, TCGv_i64 ret, TCGv_i64 arg1, T static inline void tcg_gen_sari_i64(TCGContext *s, TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2) { - tcg_gen_shifti_i64(s, ret, arg1, arg2, 1, 1); + tcg_gen_shifti_i64(s, ret, arg1, (int)arg2, 1, 1); } static inline void tcg_gen_brcond_i64(TCGContext *s, TCGCond cond, TCGv_i64 arg1, diff --git a/qemu/tcg/tcg-opc.h b/qemu/tcg/tcg-opc.h index 042d442c..9df65bc7 100644 --- a/qemu/tcg/tcg-opc.h +++ b/qemu/tcg/tcg-opc.h @@ -44,7 +44,12 @@ DEF(call, 0, 0, 3, TCG_OPF_CALL_CLOBBER | TCG_OPF_NOT_PRESENT) DEF(br, 0, 0, 1, TCG_OPF_BB_END) +#ifdef _MSC_VER +#define IMPL(X) ((0 && !(X)) ? TCG_OPF_NOT_PRESENT : 0) +#else #define IMPL(X) (__builtin_constant_p(X) && !(X) ? TCG_OPF_NOT_PRESENT : 0) +#endif + #if TCG_TARGET_REG_BITS == 32 # define IMPL64 TCG_OPF_64BIT | TCG_OPF_NOT_PRESENT #else diff --git a/qemu/tcg/tcg.c b/qemu/tcg/tcg.c index 6c0a09cf..624ef8d8 100644 --- a/qemu/tcg/tcg.c +++ b/qemu/tcg/tcg.c @@ -69,7 +69,8 @@ static void patch_reloc(tcg_insn_unit *code_ptr, int type, /* The CIE and FDE header definitions will be common to all hosts. */ typedef struct { - uint32_t len __attribute__((aligned((sizeof(void *))))); + //uint32_t QEMU_ALIGN(sizeof(void *), len); + uint32_t QEMU_ALIGN(8, len); uint32_t id; uint8_t version; char augmentation[1]; @@ -78,17 +79,18 @@ typedef struct { uint8_t return_column; } DebugFrameCIE; -typedef struct QEMU_PACKED { - uint32_t len __attribute__((aligned((sizeof(void *))))); +QEMU_PACK( typedef struct { +// uint32_t QEMU_ALIGN(sizeof(void *), len); + uint32_t QEMU_ALIGN(8, len); uint32_t cie_offset; uintptr_t func_start; uintptr_t func_len; -} DebugFrameFDEHeader; +}) DebugFrameFDEHeader; -typedef struct QEMU_PACKED { +QEMU_PACK( typedef struct { DebugFrameCIE cie; DebugFrameFDEHeader fde; -} DebugFrameHeader; +}) DebugFrameHeader; /* Forward declarations for functions declared and used in tcg-target.c. */ static int target_parse_constraint(TCGArgConstraint *ct, const char **pct_str); @@ -115,12 +117,12 @@ TCGOpDef tcg_op_defs_org[] = { }; #if TCG_TARGET_INSN_UNIT_SIZE == 1 -static __attribute__((unused)) inline void tcg_out8(TCGContext *s, uint8_t v) +static QEMU_UNUSED_FUNC inline void tcg_out8(TCGContext *s, uint8_t v) { *s->code_ptr++ = v; } -static __attribute__((unused)) inline void tcg_patch8(tcg_insn_unit *p, +static QEMU_UNUSED_FUNC inline void tcg_patch8(tcg_insn_unit *p, uint8_t v) { *p = v; @@ -128,10 +130,10 @@ static __attribute__((unused)) inline void tcg_patch8(tcg_insn_unit *p, #endif #if TCG_TARGET_INSN_UNIT_SIZE <= 2 -static __attribute__((unused)) inline void tcg_out16(TCGContext *s, uint16_t v) +static QEMU_UNUSED_FUNC inline void tcg_out16(TCGContext *s, uint16_t v) { if (TCG_TARGET_INSN_UNIT_SIZE == 2) { - *s->code_ptr++ = v; + *s->code_ptr++ = (tcg_insn_unit)v; } else { tcg_insn_unit *p = s->code_ptr; memcpy(p, &v, sizeof(v)); @@ -139,11 +141,11 @@ static __attribute__((unused)) inline void tcg_out16(TCGContext *s, uint16_t v) } } -static __attribute__((unused)) inline void tcg_patch16(tcg_insn_unit *p, +static QEMU_UNUSED_FUNC inline void tcg_patch16(tcg_insn_unit *p, uint16_t v) { if (TCG_TARGET_INSN_UNIT_SIZE == 2) { - *p = v; + *p = (tcg_insn_unit)v; } else { memcpy(p, &v, sizeof(v)); } @@ -151,7 +153,7 @@ static __attribute__((unused)) inline void tcg_patch16(tcg_insn_unit *p, #endif #if TCG_TARGET_INSN_UNIT_SIZE <= 4 -static __attribute__((unused)) inline void tcg_out32(TCGContext *s, uint32_t v) +static QEMU_UNUSED_FUNC inline void tcg_out32(TCGContext *s, uint32_t v) { if (TCG_TARGET_INSN_UNIT_SIZE == 4) { *s->code_ptr++ = v; @@ -162,7 +164,7 @@ static __attribute__((unused)) inline void tcg_out32(TCGContext *s, uint32_t v) } } -static __attribute__((unused)) inline void tcg_patch32(tcg_insn_unit *p, +static QEMU_UNUSED_FUNC inline void tcg_patch32(tcg_insn_unit *p, uint32_t v) { if (TCG_TARGET_INSN_UNIT_SIZE == 4) { @@ -174,10 +176,10 @@ static __attribute__((unused)) inline void tcg_patch32(tcg_insn_unit *p, #endif #if TCG_TARGET_INSN_UNIT_SIZE <= 8 -static __attribute__((unused)) inline void tcg_out64(TCGContext *s, uint64_t v) +static QEMU_UNUSED_FUNC inline void tcg_out64(TCGContext *s, uint64_t v) { if (TCG_TARGET_INSN_UNIT_SIZE == 8) { - *s->code_ptr++ = v; + *s->code_ptr++ = (tcg_insn_unit)v; } else { tcg_insn_unit *p = s->code_ptr; memcpy(p, &v, sizeof(v)); @@ -185,11 +187,11 @@ static __attribute__((unused)) inline void tcg_out64(TCGContext *s, uint64_t v) } } -static __attribute__((unused)) inline void tcg_patch64(tcg_insn_unit *p, +static QEMU_UNUSED_FUNC inline void tcg_patch64(tcg_insn_unit *p, uint64_t v) { if (TCG_TARGET_INSN_UNIT_SIZE == 8) { - *p = v; + *p = (tcg_insn_unit)v; } else { memcpy(p, &v, sizeof(v)); } @@ -486,7 +488,7 @@ static inline int tcg_global_mem_new_internal(TCGContext *s, TCGType type, int r #endif pstrcpy(buf, sizeof(buf), name); pstrcat(buf, sizeof(buf), "_0"); - ts->name = strdup(buf); + ts->name = g_strdup(buf); ts++; ts->base_type = type; @@ -501,7 +503,7 @@ static inline int tcg_global_mem_new_internal(TCGContext *s, TCGType type, int r #endif pstrcpy(buf, sizeof(buf), name); pstrcat(buf, sizeof(buf), "_1"); - ts->name = strdup(buf); + ts->name = g_strdup(buf); s->nb_globals += 2; } else @@ -1097,6 +1099,24 @@ static inline const char *tcg_find_helper(TCGContext *s, uintptr_t val) static const char * const cond_name[] = { +#ifdef _MSC_VER + "never", // TCG_COND_NEVER + "always", // TCG_COND_ALWAYS + "lt", // TCG_COND_LT + "ge", // TCG_COND_GE + "ltu", // TCG_COND_LTU + "geu", // TCG_COND_GEU + NULL, // n/a + NULL, // n/a + "eq", // TCG_COND_EQ + "ne", // TCG_COND_NE + "le", // TCG_COND_LE + "gt", // TCG_COND_GT + "leu", // TCG_COND_LEU + "gtu", // TCG_COND_GTU + NULL, // n/a + NULL, // n/a +#else [TCG_COND_NEVER] = "never", [TCG_COND_ALWAYS] = "always", [TCG_COND_EQ] = "eq", @@ -1109,11 +1129,49 @@ static const char * const cond_name[] = [TCG_COND_GEU] = "geu", [TCG_COND_LEU] = "leu", [TCG_COND_GTU] = "gtu" +#endif }; static const char * const ldst_name[] = { - [MO_UB] = "ub", +#ifdef _MSC_VER + "ub", // MO_UB +# ifdef HOST_WORDS_BIGENDIAN + "beuw", // MO_BEUW + "beul", // MO_BEUL + "beq", // MO_BEQ + "sb", // MO_SB + "besw", // MO_BESW + "besl", // MO_BESL + NULL, // n/a + NULL, // n/a + "leuw", // MO_LEUW + "leul", // MO_LEUL + "leq", // MO_LEQ + NULL, // n/a + "lesw", // MO_LESW + "lesl", // MO_LESL + NULL, // n/a +# else // !HOST_WORDS_BIGENDIAN + "leuw", // MO_LEUW + "leul", // MO_LEUL + "leq", // MO_LEQ + "sb", // MO_SB + "lesw", // MO_LESW + "lesl", // MO_LESL + NULL, // n/a + NULL, // n/a + "beuw", // MO_BEUW + "beul", // MO_BEUL + "beq", // MO_BEQ + NULL, // n/a + "besw", // MO_BESW + "besl", // MO_BESL + NULL, // n/a +# endif // HOST_WORDS_BIGENDIAN + +#else //_MSC_VER + [MO_UB] = "ub", [MO_SB] = "sb", [MO_LEUW] = "leuw", [MO_LESW] = "lesw", @@ -1125,6 +1183,7 @@ static const char * const ldst_name[] = [MO_BEUL] = "beul", [MO_BESL] = "besl", [MO_BEQ] = "beq", +#endif // _MSC_VER }; void tcg_dump_ops(TCGContext *s) @@ -1921,7 +1980,7 @@ static inline void temp_sync(TCGContext *s, int temp, TCGRegSet allocated_regs) if (!ts->fixed_reg) { switch(ts->val_type) { case TEMP_VAL_CONST: - ts->reg = tcg_reg_alloc(s, s->tcg_target_available_regs[ts->type], + ts->reg = tcg_reg_alloc(s, (TCGRegSet)s->tcg_target_available_regs[ts->type], allocated_regs); ts->val_type = TEMP_VAL_REG; s->reg_to_temp[ts->reg] = temp; @@ -2061,7 +2120,7 @@ static void tcg_reg_alloc_mov(TCGContext *s, const TCGOpDef *def, we don't have to reload SOURCE the next time it is used. */ if (((NEED_SYNC_ARG(0) || ots->fixed_reg) && ts->val_type != TEMP_VAL_REG) || ts->val_type == TEMP_VAL_MEM) { - ts->reg = tcg_reg_alloc(s, s->tcg_target_available_regs[itype], + ts->reg = tcg_reg_alloc(s, (TCGRegSet)s->tcg_target_available_regs[itype], allocated_regs); if (ts->val_type == TEMP_VAL_MEM) { tcg_out_ld(s, itype, ts->reg, ts->mem_reg, ts->mem_offset); @@ -2111,7 +2170,7 @@ static void tcg_reg_alloc_mov(TCGContext *s, const TCGOpDef *def, /* When allocating a new register, make sure to not spill the input one. */ tcg_regset_set_reg(allocated_regs, ts->reg); - ots->reg = tcg_reg_alloc(s, s->tcg_target_available_regs[otype], + ots->reg = tcg_reg_alloc(s, (TCGRegSet)s->tcg_target_available_regs[otype], allocated_regs); } tcg_out_mov(s, otype, ots->reg, ts->reg); @@ -2342,13 +2401,13 @@ static int tcg_reg_alloc_call(TCGContext *s, const TCGOpDef *def, if (ts->val_type == TEMP_VAL_REG) { tcg_out_st(s, ts->type, ts->reg, TCG_REG_CALL_STACK, stack_offset); } else if (ts->val_type == TEMP_VAL_MEM) { - reg = tcg_reg_alloc(s, s->tcg_target_available_regs[ts->type], + reg = tcg_reg_alloc(s, (TCGRegSet)s->tcg_target_available_regs[ts->type], s->reserved_regs); /* XXX: not correct if reading values from the stack */ tcg_out_ld(s, ts->type, reg, ts->mem_reg, ts->mem_offset); tcg_out_st(s, ts->type, reg, TCG_REG_CALL_STACK, stack_offset); } else if (ts->val_type == TEMP_VAL_CONST) { - reg = tcg_reg_alloc(s, s->tcg_target_available_regs[ts->type], + reg = tcg_reg_alloc(s, (TCGRegSet)s->tcg_target_available_regs[ts->type], s->reserved_regs); /* XXX: sign extend may be needed on some targets */ tcg_out_movi(s, ts->type, reg, ts->val); @@ -2572,7 +2631,7 @@ static inline int tcg_gen_code_common(TCGContext *s, } args += def->nb_args; next: - if (search_pc >= 0 && search_pc < tcg_current_code_size(s)) { + if (search_pc >= 0 && (size_t)search_pc < tcg_current_code_size(s)) { return op_index; } op_index++; diff --git a/qemu/tcg/tcg.h b/qemu/tcg/tcg.h index 64cc8867..54486e53 100644 --- a/qemu/tcg/tcg.h +++ b/qemu/tcg/tcg.h @@ -28,6 +28,7 @@ #include "qemu-common.h" #include "qemu/bitops.h" #include "tcg-target.h" +#include "exec/exec-all.h" #include "uc_priv.h" @@ -180,7 +181,7 @@ typedef struct TCGLabel { typedef struct TCGPool { struct TCGPool *next; int size; - uint8_t data[0] __attribute__ ((aligned)); + uint8_t QEMU_ALIGN(8, data[0]); } TCGPool; #define TCG_POOL_CHUNK_SIZE 32768 @@ -853,7 +854,7 @@ TCGv_i64 tcg_const_local_i64(TCGContext *s, int64_t val); static inline ptrdiff_t tcg_ptr_byte_diff(void *a, void *b) { - return a - b; + return (char*)a - (char*)b; } /** diff --git a/qemu/translate-all.c b/qemu/translate-all.c index 4f10c633..857db5b0 100644 --- a/qemu/translate-all.c +++ b/qemu/translate-all.c @@ -19,6 +19,7 @@ /* Modified for Unicorn Engine by Nguyen Anh Quynh, 2015 */ #ifdef _WIN32 +#include #include #else #include @@ -28,7 +29,7 @@ #include #include #include -#include +#include "platform.h" #include "config.h" @@ -43,7 +44,6 @@ #if __FreeBSD_version >= 700104 #define HAVE_KINFO_GETVMMAP #define sigqueue sigqueue_freebsd /* avoid redefinition */ -#include #include #include #define _KERNEL @@ -140,7 +140,7 @@ static void tb_clean_internal(struct uc_struct *uc, int i, void** lp) if (i == 0 || lp == 0) { return; } - tb_clean_internal(uc, i-1, (*lp) + ((0 >> (i * V_L2_BITS)) & (V_L2_SIZE - 1))); + tb_clean_internal(uc, i-1, (void*)(((char*)*lp) + ((0 >> (i * V_L2_BITS)) & (V_L2_SIZE - 1)))); if (lp && *lp) { g_free(*lp); } @@ -563,8 +563,7 @@ static inline void *split_cross_256mb(struct uc_struct *uc, void *buf1, size_t s #endif #ifdef USE_STATIC_CODE_GEN_BUFFER -static uint8_t static_code_gen_buffer[DEFAULT_CODE_GEN_BUFFER_SIZE] - __attribute__((aligned(CODE_GEN_ALIGN))); +static uint8_t QEMU_ALIGN(CODE_GEN_ALIGN, static_code_gen_buffer[DEFAULT_CODE_GEN_BUFFER_SIZE]); void free_code_gen_buffer(struct uc_struct *uc) { @@ -719,7 +718,7 @@ static inline void code_gen_alloc(struct uc_struct *uc, size_t tb_size) from TB's to the prologue are going to be in range. It also means that we don't need to mark (additional) portions of the data segment as executable. */ - tcg_ctx->code_gen_prologue = tcg_ctx->code_gen_buffer + + tcg_ctx->code_gen_prologue = (char*)tcg_ctx->code_gen_buffer + tcg_ctx->code_gen_buffer_size - 1024; tcg_ctx->code_gen_buffer_size -= 1024; @@ -765,7 +764,7 @@ static TranslationBlock *tb_alloc(struct uc_struct *uc, target_ulong pc) TCGContext *tcg_ctx = uc->tcg_ctx; if (tcg_ctx->tb_ctx.nb_tbs >= tcg_ctx->code_gen_max_blocks || - (tcg_ctx->code_gen_ptr - tcg_ctx->code_gen_buffer) >= + (size_t)(((char*)tcg_ctx->code_gen_ptr - (char*)tcg_ctx->code_gen_buffer)) >= tcg_ctx->code_gen_buffer_max_size) { return NULL; } @@ -849,7 +848,7 @@ void tb_flush(CPUArchState *env1) ((unsigned long)(tcg_ctx->code_gen_ptr - tcg_ctx->code_gen_buffer)) / tcg_ctx->tb_ctx.nb_tbs : 0); #endif - if ((unsigned long)(tcg_ctx->code_gen_ptr - tcg_ctx->code_gen_buffer) + if ((unsigned long)((char*)tcg_ctx->code_gen_ptr - (char*)tcg_ctx->code_gen_buffer) > tcg_ctx->code_gen_buffer_size) { cpu_abort(cpu, "Internal error: code buffer overflow\n"); } @@ -972,7 +971,7 @@ static inline void tb_jmp_remove(TranslationBlock *tb, int n) another TB */ static inline void tb_reset_jump(TranslationBlock *tb, int n) { - tb_set_jmp_target(tb, n, (uintptr_t)(tb->tc_ptr + tb->tb_next_offset[n])); + tb_set_jmp_target(tb, n, (uintptr_t)((char*)tb->tc_ptr + tb->tb_next_offset[n])); } /* invalidate one TB */ @@ -1521,8 +1520,8 @@ void tb_invalidate_phys_addr(AddressSpace *as, hwaddr addr) || memory_region_is_romd(mr))) { return; } - ram_addr = (memory_region_get_ram_addr(mr) & TARGET_PAGE_MASK) - + addr; + ram_addr = (ram_addr_t)((memory_region_get_ram_addr(mr) & TARGET_PAGE_MASK) + + addr); tb_invalidate_phys_page_range(as->uc, ram_addr, ram_addr + 1, 0); } #endif /* TARGET_HAS_ICE && !defined(CONFIG_USER_ONLY) */ @@ -1604,7 +1603,7 @@ void cpu_io_recompile(CPUState *cpu, uintptr_t retaddr) tb_phys_invalidate(cpu->uc, tb, -1); /* FIXME: In theory this could raise an exception. In practice we have already translated the block once so it's probably ok. */ - tb_gen_code(cpu, pc, cs_base, flags, cflags); + tb_gen_code(cpu, pc, cs_base, (int)flags, cflags); /* TODO: If env->pc != tb->pc (i.e. the faulting instruction was not the first in the TB) then we end up generating a whole new TB and repeating the fault, which is horribly inefficient. diff --git a/qemu/unicorn_common.h b/qemu/unicorn_common.h index bd8b5f6c..8dcbb3e5 100644 --- a/qemu/unicorn_common.h +++ b/qemu/unicorn_common.h @@ -25,6 +25,7 @@ void free_code_gen_buffer(struct uc_struct *uc); /** Freeing common resources */ static void release_common(void *t) { + TCGPool *po, *to; TCGContext *s = (TCGContext *)t; #if TCG_TARGET_REG_BITS == 32 int i; @@ -36,7 +37,6 @@ static void release_common(void *t) g_free(def->sorted_args); g_free(s->tcg_op_defs); - TCGPool *po, *to; for (po = s->pool_first; po; po = to) { to = po->next; g_free(po); diff --git a/qemu/util/cutils.c b/qemu/util/cutils.c index 1b67e0d0..0272f467 100644 --- a/qemu/util/cutils.c +++ b/qemu/util/cutils.c @@ -122,11 +122,11 @@ int64_t strtosz_suffix_unit(const char *nptr, char **end, mul_required = 1; } c = *endptr; - mul = suffix_mul(c, unit); + mul = (double)suffix_mul(c, unit); if (mul >= 0) { endptr++; } else { - mul = suffix_mul(default_suffix, unit); + mul = (double)suffix_mul(default_suffix, unit); assert(mul >= 0); } if (mul == 1 && mul_required) { @@ -136,7 +136,7 @@ int64_t strtosz_suffix_unit(const char *nptr, char **end, retval = -ERANGE; goto fail; } - retval = val * mul; + retval = (int64_t)(val * mul); fail: if (end) { diff --git a/qemu/util/host-utils.c b/qemu/util/host-utils.c index 0fc560d6..88fa1714 100644 --- a/qemu/util/host-utils.c +++ b/qemu/util/host-utils.c @@ -24,7 +24,7 @@ */ #include -#include +#include "platform.h" #include "qemu/host-utils.h" #ifndef CONFIG_INT128 @@ -54,10 +54,10 @@ static inline void mul64(uint64_t *plow, uint64_t *phigh, rh.ll = (uint64_t)a0.l.high * b0.l.high; c = (uint64_t)rl.l.high + rm.l.low + rn.l.low; - rl.l.high = c; + rl.l.high = (uint32_t)c; c >>= 32; c = c + rm.l.high + rn.l.high + rh.l.low; - rh.l.low = c; + rh.l.low = (uint32_t)c; rh.l.high += (uint32_t)(c >> 32); *plow = rl.ll; diff --git a/qemu/util/oslib-posix.c b/qemu/util/oslib-posix.c index 47b73495..4e9410ac 100644 --- a/qemu/util/oslib-posix.c +++ b/qemu/util/oslib-posix.c @@ -39,8 +39,7 @@ #endif #define HUGETLBFS_MAGIC 0x958458f6 -#include -#include +#include "platform.h" #include "config-host.h" #include "sysemu/sysemu.h" diff --git a/qemu/util/oslib-win32.c b/qemu/util/oslib-win32.c index 26013620..0a07c18b 100644 --- a/qemu/util/oslib-win32.c +++ b/qemu/util/oslib-win32.c @@ -26,6 +26,7 @@ * THE SOFTWARE. * */ +#include #include #include diff --git a/qemu/util/qemu-error.c b/qemu/util/qemu-error.c index 06caa508..88f89b71 100644 --- a/qemu/util/qemu-error.c +++ b/qemu/util/qemu-error.c @@ -11,6 +11,8 @@ */ #include +#include +#include static const char *progname; @@ -42,6 +44,14 @@ static void error_print_loc(void) * Prepend the current location and append a newline. * It's wrong to call this in a QMP monitor. Use qerror_report() there. */ +#ifdef _MSC_VER +void error_vreport(const char *fmt, va_list ap) +{ + error_print_loc(); + vfprintf(stderr, fmt, ap); + fprintf(stderr, "\n"); +} +#else void error_vreport(const char *fmt, va_list ap) { GTimeVal tv; @@ -51,6 +61,7 @@ void error_vreport(const char *fmt, va_list ap) error_vprintf(fmt, ap); error_printf("\n"); } +#endif /* * Print an error message to current monitor if we have one, else to stderr. diff --git a/qemu/util/qemu-thread-posix.c b/qemu/util/qemu-thread-posix.c index cc6cf46e..b211c875 100644 --- a/qemu/util/qemu-thread-posix.c +++ b/qemu/util/qemu-thread-posix.c @@ -15,11 +15,9 @@ #include #include #include -#include +#include "platform.h" #include #include -#include -#include #ifdef __linux__ #include #include diff --git a/qemu/util/qemu-timer-common.c b/qemu/util/qemu-timer-common.c index 95e0847c..803b1fab 100644 --- a/qemu/util/qemu-timer-common.c +++ b/qemu/util/qemu-timer-common.c @@ -30,7 +30,7 @@ int64_t clock_freq; -static void __attribute__((constructor)) init_get_clock(void) +INITIALIZER(init_get_clock) { LARGE_INTEGER freq; int ret; @@ -46,7 +46,7 @@ static void __attribute__((constructor)) init_get_clock(void) int use_rt_clock; -static void __attribute__((constructor)) init_get_clock(void) +INITIALIZER(init_get_clock) { use_rt_clock = 0; #ifdef CLOCK_MONOTONIC diff --git a/qemu/vl.c b/qemu/vl.c index 5a923fe3..f6c68b47 100644 --- a/qemu/vl.c +++ b/qemu/vl.c @@ -75,7 +75,7 @@ MachineClass *find_default_machine(struct uc_struct *uc, int arch) return mc; } -__attribute__ ((visibility ("default"))) +DEFAULT_VISIBILITY int machine_initialize(struct uc_struct *uc) { MachineClass *machine_class; @@ -142,12 +142,11 @@ void qemu_register_machine(struct uc_struct *uc, QEMUMachine *m, const char *typ void (*init)(struct uc_struct *uc, ObjectClass *oc, void *data)) { char *name = g_strconcat(m->name, TYPE_MACHINE_SUFFIX, NULL); - TypeInfo ti = { - .name = name, - .parent = type_machine, - .class_init = init, - .class_data = (void *)m, - }; + TypeInfo ti = {0}; + ti.name = name; + ti.parent = type_machine; + ti.class_init = init; + ti.class_data = (void *)m; if (init == NULL) ti.class_init = machine_class_init; diff --git a/samples/mem_apis.c b/samples/mem_apis.c index dc1c2481..4680da70 100644 --- a/samples/mem_apis.c +++ b/samples/mem_apis.c @@ -38,8 +38,8 @@ // posix specific includes #else // _MSC_VER -#include -#include +#include "platform.h" +#include "platform.h" #include #endif // _MSC_VER diff --git a/samples/sample_arm.c b/samples/sample_arm.c index fc3570ec..0b1366a0 100644 --- a/samples/sample_arm.c +++ b/samples/sample_arm.c @@ -21,8 +21,8 @@ // posix specific #else // _MSC_VER -#include -#include +#include "platform.h" +#include "platform.h" #include #endif // _MSC_VER diff --git a/samples/sample_arm64.c b/samples/sample_arm64.c index 785708d0..e0abc87e 100644 --- a/samples/sample_arm64.c +++ b/samples/sample_arm64.c @@ -21,8 +21,8 @@ // posix specific #else // _MSC_VER -#include -#include +#include "platform.h" +#include "platform.h" #include #endif // _MSC_VER diff --git a/samples/sample_batch_reg.c b/samples/sample_batch_reg.c index 90684d75..2009738d 100644 --- a/samples/sample_batch_reg.c +++ b/samples/sample_batch_reg.c @@ -1,5 +1,4 @@ -#include -#include +#include "platform.h" #include #include #include diff --git a/samples/sample_m68k.c b/samples/sample_m68k.c index 4bbf1cce..61fbb146 100644 --- a/samples/sample_m68k.c +++ b/samples/sample_m68k.c @@ -21,8 +21,8 @@ // posix specific #else // _MSC_VER -#include -#include +#include "platform.h" +#include "platform.h" #include #endif // _MSC_VER diff --git a/samples/sample_mips.c b/samples/sample_mips.c index 994047c2..0c074c72 100644 --- a/samples/sample_mips.c +++ b/samples/sample_mips.c @@ -21,8 +21,8 @@ // posix specific #else // _MSC_VER -#include -#include +#include "platform.h" +#include "platform.h" #include #endif // _MSC_VER diff --git a/samples/sample_sparc.c b/samples/sample_sparc.c index 649a6dec..aa80edbb 100644 --- a/samples/sample_sparc.c +++ b/samples/sample_sparc.c @@ -21,8 +21,8 @@ // posix specific #else // _MSC_VER -#include -#include +#include "platform.h" +#include "platform.h" #include #endif // _MSC_VER diff --git a/samples/sample_x86.c b/samples/sample_x86.c index 079ca7d6..ca4309f7 100644 --- a/samples/sample_x86.c +++ b/samples/sample_x86.c @@ -21,8 +21,8 @@ // posix specific #else // _MSC_VER -#include -#include +#include "platform.h" +#include "platform.h" #include #endif // _MSC_VER diff --git a/samples/sample_x86_32_gdt_and_seg_regs.c b/samples/sample_x86_32_gdt_and_seg_regs.c index 7e1e260b..794ee99d 100644 --- a/samples/sample_x86_32_gdt_and_seg_regs.c +++ b/samples/sample_x86_32_gdt_and_seg_regs.c @@ -20,11 +20,11 @@ Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. */ #include -#include +#include "platform.h" #include #include #include -#include +#include "platform.h" #pragma pack(push, 1) struct SegmentDescriptor { diff --git a/samples/shellcode.c b/samples/shellcode.c index ee706a6e..c9f34cd8 100644 --- a/samples/shellcode.c +++ b/samples/shellcode.c @@ -21,8 +21,8 @@ // posix specific #else // _MSC_VER -#include -#include +#include "platform.h" +#include "platform.h" #include #endif // _MSC_VER diff --git a/tests/regress/block_test.c b/tests/regress/block_test.c index 979d989f..7071d674 100644 --- a/tests/regress/block_test.c +++ b/tests/regress/block_test.c @@ -1,9 +1,8 @@ #include -#include -#include +#include "platform.h" #include #include -#include +#include "platform.h" #include diff --git a/tests/regress/eflags_noset.c b/tests/regress/eflags_noset.c index 80afb495..0914436a 100644 --- a/tests/regress/eflags_noset.c +++ b/tests/regress/eflags_noset.c @@ -1,7 +1,6 @@ #include #include -#include -#include +#include "platform.h" #include #include diff --git a/tests/regress/eflags_nosync.c b/tests/regress/eflags_nosync.c index 433dcfbc..bf3dc729 100644 --- a/tests/regress/eflags_nosync.c +++ b/tests/regress/eflags_nosync.c @@ -1,4 +1,4 @@ -#include +#include "platform.h" #include #include #include diff --git a/tests/regress/emu_clear_errors.c b/tests/regress/emu_clear_errors.c index bed3965d..4ee08654 100644 --- a/tests/regress/emu_clear_errors.c +++ b/tests/regress/emu_clear_errors.c @@ -1,9 +1,8 @@ #include -#include -#include +#include "platform.h" #include #include -#include +#include "platform.h" #include diff --git a/tests/regress/emu_stop_in_hook_overrun.c b/tests/regress/emu_stop_in_hook_overrun.c index 2336fc4b..ea419ca6 100644 --- a/tests/regress/emu_stop_in_hook_overrun.c +++ b/tests/regress/emu_stop_in_hook_overrun.c @@ -22,8 +22,8 @@ Test for uc_emu_stop() in code hook not always stopping the emu at the current i // posix specific #else // _MSC_VER -#include -#include +#include "platform.h" +#include "platform.h" #include #include "pthread.h" #endif // _MSC_VER diff --git a/tests/regress/hook_extrainvoke.c b/tests/regress/hook_extrainvoke.c index 174257c9..5281361c 100644 --- a/tests/regress/hook_extrainvoke.c +++ b/tests/regress/hook_extrainvoke.c @@ -1,6 +1,6 @@ #include #include -#include +#include "platform.h" #include diff --git a/tests/regress/invalid_read_in_cpu_tb_exec.c b/tests/regress/invalid_read_in_cpu_tb_exec.c index 755b7180..b621fdf9 100644 --- a/tests/regress/invalid_read_in_cpu_tb_exec.c +++ b/tests/regress/invalid_read_in_cpu_tb_exec.c @@ -1,4 +1,4 @@ -#include +#include "platform.h" #include static void hook_block(uc_engine *uc, uint64_t address, uint32_t size, void *user_data) { diff --git a/tests/regress/mem_64_c.c b/tests/regress/mem_64_c.c index 137e6561..e78b1af2 100644 --- a/tests/regress/mem_64_c.c +++ b/tests/regress/mem_64_c.c @@ -1,5 +1,5 @@ #include -#include +#include "platform.h" #include uint64_t starts[] = {0x10000000, 0x110004000ll}; diff --git a/tests/regress/mem_double_unmap.c b/tests/regress/mem_double_unmap.c index e7203ab8..6eae6e28 100644 --- a/tests/regress/mem_double_unmap.c +++ b/tests/regress/mem_double_unmap.c @@ -1,7 +1,7 @@ #define __STDC_FORMAT_MACROS -#include +#include "platform.h" #include -#include +#include "platform.h" #include #include #include diff --git a/tests/regress/mem_exec.c b/tests/regress/mem_exec.c index 8be1dab3..546aab0d 100644 --- a/tests/regress/mem_exec.c +++ b/tests/regress/mem_exec.c @@ -19,9 +19,9 @@ */ #define __STDC_FORMAT_MACROS -#include +#include "platform.h" #include -#include +#include "platform.h" #include #include #include diff --git a/tests/regress/mem_fuzz.c b/tests/regress/mem_fuzz.c index c62d74c0..43d02f91 100644 --- a/tests/regress/mem_fuzz.c +++ b/tests/regress/mem_fuzz.c @@ -1,7 +1,7 @@ #define __STDC_FORMAT_MACROS -#include +#include "platform.h" #include -#include +#include "platform.h" #include #include #include diff --git a/tests/regress/mem_nofree.c b/tests/regress/mem_nofree.c index 12b620f7..8008c3d8 100644 --- a/tests/regress/mem_nofree.c +++ b/tests/regress/mem_nofree.c @@ -1,7 +1,6 @@ #include #include -#include -#include +#include "platform.h" #include diff --git a/tests/regress/mem_protect.c b/tests/regress/mem_protect.c index 3f1ec820..fe916af1 100644 --- a/tests/regress/mem_protect.c +++ b/tests/regress/mem_protect.c @@ -19,9 +19,9 @@ */ #define __STDC_FORMAT_MACROS -#include +#include "platform.h" #include -#include +#include "platform.h" #include #include #include diff --git a/tests/regress/mem_unmap.c b/tests/regress/mem_unmap.c index 17997870..8aa2c60a 100644 --- a/tests/regress/mem_unmap.c +++ b/tests/regress/mem_unmap.c @@ -20,9 +20,9 @@ */ #define __STDC_FORMAT_MACROS -#include +#include "platform.h" #include -#include +#include "platform.h" #include #include #include diff --git a/tests/regress/memleak_arm.c b/tests/regress/memleak_arm.c index 21430795..91d1e16d 100644 --- a/tests/regress/memleak_arm.c +++ b/tests/regress/memleak_arm.c @@ -21,8 +21,8 @@ // posix specific #else // _MSC_VER -#include -#include +#include "platform.h" +#include "platform.h" #include #endif // _MSC_VER diff --git a/tests/regress/memleak_arm64.c b/tests/regress/memleak_arm64.c index e9b43c0e..f3eeb1ce 100644 --- a/tests/regress/memleak_arm64.c +++ b/tests/regress/memleak_arm64.c @@ -21,8 +21,8 @@ // posix specific #else // _MSC_VER -#include -#include +#include "platform.h" +#include "platform.h" #include #endif // _MSC_VER diff --git a/tests/regress/memleak_m68k.c b/tests/regress/memleak_m68k.c index 8504daf1..6ddd2612 100644 --- a/tests/regress/memleak_m68k.c +++ b/tests/regress/memleak_m68k.c @@ -21,8 +21,8 @@ // posix specific #else // _MSC_VER -#include -#include +#include "platform.h" +#include "platform.h" #include #endif // _MSC_VER diff --git a/tests/regress/memleak_mips.c b/tests/regress/memleak_mips.c index e82a301b..91866d4b 100644 --- a/tests/regress/memleak_mips.c +++ b/tests/regress/memleak_mips.c @@ -21,8 +21,8 @@ // posix specific #else // _MSC_VER -#include -#include +#include "platform.h" +#include "platform.h" #include #endif // _MSC_VER diff --git a/tests/regress/memleak_sparc.c b/tests/regress/memleak_sparc.c index 1493d24e..c45f71fd 100644 --- a/tests/regress/memleak_sparc.c +++ b/tests/regress/memleak_sparc.c @@ -21,8 +21,8 @@ // posix specific #else // _MSC_VER -#include -#include +#include "platform.h" +#include "platform.h" #include #endif // _MSC_VER diff --git a/tests/regress/memleak_x86.c b/tests/regress/memleak_x86.c index 737f7305..14bc116b 100644 --- a/tests/regress/memleak_x86.c +++ b/tests/regress/memleak_x86.c @@ -21,8 +21,8 @@ // posix specific #else // _MSC_VER -#include -#include +#include "platform.h" +#include "platform.h" #include #endif // _MSC_VER diff --git a/tests/regress/mips_branch_likely_issue.c b/tests/regress/mips_branch_likely_issue.c index 75926692..ee0323ce 100644 --- a/tests/regress/mips_branch_likely_issue.c +++ b/tests/regress/mips_branch_likely_issue.c @@ -22,8 +22,8 @@ // posix specific #else // _MSC_VER -#include -#include +#include "platform.h" +#include "platform.h" #include #include "pthread.h" #endif // _MSC_VER diff --git a/tests/regress/mips_delay_slot_code_hook.c b/tests/regress/mips_delay_slot_code_hook.c index 1feca5c1..6164ae34 100644 --- a/tests/regress/mips_delay_slot_code_hook.c +++ b/tests/regress/mips_delay_slot_code_hook.c @@ -27,8 +27,8 @@ but that the code hook is just not occurring. // posix specific #else // _MSC_VER -#include -#include +#include "platform.h" +#include "platform.h" #include #endif // _MSC_VER diff --git a/tests/regress/nr_mem_test.c b/tests/regress/nr_mem_test.c index 40ffa39f..55edc733 100644 --- a/tests/regress/nr_mem_test.c +++ b/tests/regress/nr_mem_test.c @@ -18,9 +18,9 @@ Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. */ -#include +#include "platform.h" #include -#include +#include "platform.h" #include diff --git a/tests/regress/rep_movsb.c b/tests/regress/rep_movsb.c index 86594978..8ce997a7 100644 --- a/tests/regress/rep_movsb.c +++ b/tests/regress/rep_movsb.c @@ -20,9 +20,9 @@ Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. */ #define __STDC_FORMAT_MACROS -#include +#include "platform.h" #include -#include +#include "platform.h" #include #include #include diff --git a/tests/regress/ro_mem_test.c b/tests/regress/ro_mem_test.c index b5b26393..f1117a4d 100644 --- a/tests/regress/ro_mem_test.c +++ b/tests/regress/ro_mem_test.c @@ -18,9 +18,9 @@ Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. */ -#include +#include "platform.h" #include -#include +#include "platform.h" #include diff --git a/tests/regress/rw_hookstack.c b/tests/regress/rw_hookstack.c index 3d7eacaa..84a03c67 100644 --- a/tests/regress/rw_hookstack.c +++ b/tests/regress/rw_hookstack.c @@ -1,8 +1,6 @@ #include #include -#include -#include -#include +#include "platform.h" #include #define ADDRESS 0x1000000 diff --git a/tests/regress/threaded_emu_start.c b/tests/regress/threaded_emu_start.c index b75261c4..2d3692be 100644 --- a/tests/regress/threaded_emu_start.c +++ b/tests/regress/threaded_emu_start.c @@ -33,8 +33,8 @@ background. // posix specific #else // _MSC_VER -#include -#include +#include "platform.h" +#include "platform.h" #include #include "pthread.h" #endif // _MSC_VER diff --git a/tests/regress/timeout_segfault.c b/tests/regress/timeout_segfault.c index 54b04db0..07cbb41d 100644 --- a/tests/regress/timeout_segfault.c +++ b/tests/regress/timeout_segfault.c @@ -9,7 +9,7 @@ call to uc_emu_start(). See issue #78 for more details: https://github.com/unicorn-engine/unicorn/issues/78 */ -#include +#include "platform.h" #include diff --git a/tests/unit/test_gdt_idt_x86.c b/tests/unit/test_gdt_idt_x86.c index 5344d7a5..f3a906c2 100644 --- a/tests/unit/test_gdt_idt_x86.c +++ b/tests/unit/test_gdt_idt_x86.c @@ -1,9 +1,9 @@ #include -#include +#include "platform.h" #include #include #include -#include +#include "platform.h" /** * Assert that err matches expect diff --git a/tests/unit/test_hang.c b/tests/unit/test_hang.c index 16a61d4f..8183dbf2 100644 --- a/tests/unit/test_hang.c +++ b/tests/unit/test_hang.c @@ -5,7 +5,7 @@ #include "unicorn_test.h" #include -#include +#include "platform.h" uint64_t trunc_page(uint64_t addr) { diff --git a/tests/unit/test_hookcounts.c b/tests/unit/test_hookcounts.c index e744f142..127be64e 100644 --- a/tests/unit/test_hookcounts.c +++ b/tests/unit/test_hookcounts.c @@ -4,7 +4,7 @@ // emulation by counts of instruction code // #include "unicorn_test.h" -#include +#include "platform.h" #define DEBUG 1 diff --git a/tests/unit/test_mem_high.c b/tests/unit/test_mem_high.c index c8e58288..b0c9f9cd 100644 --- a/tests/unit/test_mem_high.c +++ b/tests/unit/test_mem_high.c @@ -7,7 +7,7 @@ #include "unicorn_test.h" #include #include -#include +#include "platform.h" /* Called before every test to set up a new instance */ static int setup(void **state) diff --git a/tests/unit/test_multihook.c b/tests/unit/test_multihook.c index c131481d..8eef231a 100644 --- a/tests/unit/test_multihook.c +++ b/tests/unit/test_multihook.c @@ -1,5 +1,5 @@ #include "unicorn_test.h" -#include +#include "platform.h" #define OK(x) uc_assert_success(x) diff --git a/tests/unit/test_pc_change.c b/tests/unit/test_pc_change.c index c2ec73a8..a77e7441 100644 --- a/tests/unit/test_pc_change.c +++ b/tests/unit/test_pc_change.c @@ -1,6 +1,6 @@ // Test PC change during the callback. by Nguyen Anh Quynh, 2016 #include "unicorn_test.h" -#include +#include "platform.h" #define OK(x) uc_assert_success(x) diff --git a/tests/unit/test_tb_x86.c b/tests/unit/test_tb_x86.c index 16534528..77cf9260 100644 --- a/tests/unit/test_tb_x86.c +++ b/tests/unit/test_tb_x86.c @@ -8,7 +8,7 @@ #include #include #include -#include +#include "platform.h" #define RIP_NEXT_TO_THE_SELFMODIFY_OPCODE (1) diff --git a/tests/unit/test_x86.c b/tests/unit/test_x86.c index 1c451fcf..adfdbf2c 100644 --- a/tests/unit/test_x86.c +++ b/tests/unit/test_x86.c @@ -1,5 +1,5 @@ #include "unicorn_test.h" -#include +#include "platform.h" #define OK(x) uc_assert_success(x) diff --git a/tests/unit/test_x86_rip_bug.c b/tests/unit/test_x86_rip_bug.c index 31e0d708..38a2c25d 100644 --- a/tests/unit/test_x86_rip_bug.c +++ b/tests/unit/test_x86_rip_bug.c @@ -1,5 +1,5 @@ -#include -#include +#include "platform.h" +#include "platform.h" #include #include "unicorn_test.h" diff --git a/tests/unit/test_x86_shl_enter_leave.c b/tests/unit/test_x86_shl_enter_leave.c index f7fe9ad3..65c73c12 100644 --- a/tests/unit/test_x86_shl_enter_leave.c +++ b/tests/unit/test_x86_shl_enter_leave.c @@ -1,6 +1,5 @@ -#include +#include "platform.h" #include -#include #include "unicorn_test.h" diff --git a/tests/unit/test_x86_soft_paging.c b/tests/unit/test_x86_soft_paging.c index ffba0155..1722fd8c 100644 --- a/tests/unit/test_x86_soft_paging.c +++ b/tests/unit/test_x86_soft_paging.c @@ -1,5 +1,5 @@ #include "unicorn_test.h" -#include +#include "platform.h" /* Two tests here for software paging diff --git a/uc.c b/uc.c index 46b019cc..d7d6becc 100644 --- a/uc.c +++ b/uc.c @@ -400,7 +400,7 @@ static bool check_mem_area(uc_engine *uc, uint64_t address, size_t size) while(count < size) { MemoryRegion *mr = memory_mapping(uc, address); if (mr) { - len = MIN(size - count, mr->end - address); + len = (size_t)MIN(size - count, mr->end - address); count += len; address += len; } else // this address is not mapped in yet @@ -428,7 +428,7 @@ uc_err uc_mem_read(uc_engine *uc, uint64_t address, void *_bytes, size_t size) while(count < size) { MemoryRegion *mr = memory_mapping(uc, address); if (mr) { - len = MIN(size - count, mr->end - address); + len = (size_t)MIN(size - count, mr->end - address); if (uc->read_mem(&uc->as, address, bytes, len) == false) break; count += len; @@ -466,7 +466,7 @@ uc_err uc_mem_write(uc_engine *uc, uint64_t address, const void *_bytes, size_t // but this is not the program accessing memory, so temporarily mark writable uc->readonly_mem(mr, false); - len = MIN(size - count, mr->end - address); + len = (size_t)MIN(size - count, mr->end - address); if (uc->write_mem(&uc->as, address, bytes, len) == false) break; @@ -498,7 +498,7 @@ static void *_timeout_fn(void *arg) // perhaps emulation is even done before timeout? if (uc->emulation_done) break; - } while(get_clock() - current_time < uc->timeout); + } while((uint64_t)(get_clock() - current_time) < uc->timeout); // timeout before emulation is done? if (!uc->emulation_done) { @@ -746,9 +746,9 @@ uc_err uc_mem_map_ptr(uc_engine *uc, uint64_t address, size_t size, uint32_t per // Generally used in prepartion for splitting a MemoryRegion. static uint8_t *copy_region(struct uc_struct *uc, MemoryRegion *mr) { - uint8_t *block = (uint8_t *)g_malloc0(int128_get64(mr->size)); + uint8_t *block = (uint8_t *)g_malloc0((size_t)int128_get64(mr->size)); if (block != NULL) { - uc_err err = uc_mem_read(uc, mr->addr, block, int128_get64(mr->size)); + uc_err err = uc_mem_read(uc, mr->addr, block, (size_t)int128_get64(mr->size)); if (err != UC_ERR_OK) { free(block); block = NULL; @@ -806,7 +806,7 @@ static bool split_region(struct uc_struct *uc, MemoryRegion *mr, uint64_t addres end = mr->end; // unmap this region first, then do split it later - if (uc_mem_unmap(uc, mr->addr, int128_get64(mr->size)) != UC_ERR_OK) + if (uc_mem_unmap(uc, mr->addr, (size_t)int128_get64(mr->size)) != UC_ERR_OK) goto error; /* overlapping cases @@ -897,7 +897,7 @@ uc_err uc_mem_protect(struct uc_struct *uc, uint64_t address, size_t size, uint3 count = 0; while(count < size) { mr = memory_mapping(uc, addr); - len = MIN(size - count, mr->end - addr); + len = (size_t)MIN(size - count, mr->end - addr); if (!split_region(uc, mr, addr, len, false)) return UC_ERR_NOMEM; @@ -954,7 +954,7 @@ uc_err uc_mem_unmap(struct uc_struct *uc, uint64_t address, size_t size) count = 0; while(count < size) { mr = memory_mapping(uc, addr); - len = MIN(size - count, mr->end - addr); + len = (size_t)MIN(size - count, mr->end - addr); if (!split_region(uc, mr, addr, len, true)) return UC_ERR_NOMEM; @@ -1097,7 +1097,7 @@ void helper_uc_tracecode(int32_t size, uc_hook_type type, void *handle, int64_t while (cur != NULL && !uc->stop_request) { hook = (struct hook *)cur->data; - if (HOOK_BOUND_CHECK(hook, address)) { + if (HOOK_BOUND_CHECK(hook, (uint64_t)address)) { ((uc_cb_hookcode_t)hook->callback)(uc, address, size, hook->user_data); } cur = cur->next;