diff --git a/qemu/aarch64.h b/qemu/aarch64.h index 09bb21b2..2eb00e39 100644 --- a/qemu/aarch64.h +++ b/qemu/aarch64.h @@ -3415,6 +3415,7 @@ #define fp_exception_el fp_exception_el_aarch64 #define gen_a64_set_pc_im gen_a64_set_pc_im_aarch64 #define gen_cmtst_i64 gen_cmtst_i64_aarch64 +#define get_phys_addr get_phys_addr_aarch64 #define pmu_init pmu_init_aarch64 #define helper_advsimd_acge_f16 helper_advsimd_acge_f16_aarch64 #define helper_advsimd_acgt_f16 helper_advsimd_acgt_f16_aarch64 diff --git a/qemu/aarch64eb.h b/qemu/aarch64eb.h index 089728a2..2e09de9d 100644 --- a/qemu/aarch64eb.h +++ b/qemu/aarch64eb.h @@ -3415,6 +3415,7 @@ #define fp_exception_el fp_exception_el_aarch64eb #define gen_a64_set_pc_im gen_a64_set_pc_im_aarch64eb #define gen_cmtst_i64 gen_cmtst_i64_aarch64eb +#define get_phys_addr get_phys_addr_aarch64eb #define pmu_init pmu_init_aarch64eb #define helper_advsimd_acge_f16 helper_advsimd_acge_f16_aarch64eb #define helper_advsimd_acgt_f16 helper_advsimd_acgt_f16_aarch64eb diff --git a/qemu/arm.h b/qemu/arm.h index ec003465..d498ec4e 100644 --- a/qemu/arm.h +++ b/qemu/arm.h @@ -3400,6 +3400,7 @@ #define cpu_mmu_index cpu_mmu_index_arm #define fp_exception_el fp_exception_el_arm #define gen_cmtst_i64 gen_cmtst_i64_arm +#define get_phys_addr get_phys_addr_arm #define helper_fjcvtzs helper_fjcvtzs_arm #define helper_vjcvt helper_vjcvt_arm #define pmu_init pmu_init_arm diff --git a/qemu/armeb.h b/qemu/armeb.h index f09aee7c..2e631bc9 100644 --- a/qemu/armeb.h +++ b/qemu/armeb.h @@ -3400,6 +3400,7 @@ #define cpu_mmu_index cpu_mmu_index_armeb #define fp_exception_el fp_exception_el_armeb #define gen_cmtst_i64 gen_cmtst_i64_armeb +#define get_phys_addr get_phys_addr_armeb #define helper_fjcvtzs helper_fjcvtzs_armeb #define helper_vjcvt helper_vjcvt_armeb #define pmu_init pmu_init_armeb diff --git a/qemu/header_gen.py b/qemu/header_gen.py index 758b0f3b..26a56a74 100644 --- a/qemu/header_gen.py +++ b/qemu/header_gen.py @@ -3409,6 +3409,7 @@ arm_symbols = ( 'cpu_mmu_index', 'fp_exception_el', 'gen_cmtst_i64', + 'get_phys_addr', 'helper_fjcvtzs', 'helper_vjcvt', 'pmu_init', @@ -3470,6 +3471,7 @@ aarch64_symbols = ( 'fp_exception_el', 'gen_a64_set_pc_im', 'gen_cmtst_i64', + 'get_phys_addr', 'pmu_init', 'helper_advsimd_acge_f16', 'helper_advsimd_acgt_f16', diff --git a/qemu/target/arm/helper.c b/qemu/target/arm/helper.c index a612d719..7acc520a 100644 --- a/qemu/target/arm/helper.c +++ b/qemu/target/arm/helper.c @@ -24,17 +24,6 @@ #define ARM_CPU_FREQ 1000000000 /* FIXME: 1 GHz, should be configurable */ #ifndef CONFIG_USER_ONLY -/* Cacheability and shareability attributes for a memory access */ -typedef struct ARMCacheAttrs { - unsigned int attrs:8; /* as in the MAIR register encoding */ - unsigned int shareability:2; /* as in the SH field of the VMSAv8-64 PTEs */ -} ARMCacheAttrs; - -static bool get_phys_addr(CPUARMState *env, target_ulong address, - MMUAccessType access_type, ARMMMUIdx mmu_idx, - hwaddr *phys_ptr, MemTxAttrs *attrs, int *prot, - target_ulong *page_size, - ARMMMUFaultInfo *fi, ARMCacheAttrs *cacheattrs); static bool get_phys_addr_lpae(CPUARMState *env, target_ulong address, MMUAccessType access_type, ARMMMUIdx mmu_idx, @@ -12487,11 +12476,11 @@ static ARMCacheAttrs combine_cacheattrs(ARMCacheAttrs s1, ARMCacheAttrs s2) * @fi: set to fault info if the translation fails * @cacheattrs: (if non-NULL) set to the cacheability/shareability attributes */ -static bool get_phys_addr(CPUARMState *env, target_ulong address, - MMUAccessType access_type, ARMMMUIdx mmu_idx, - hwaddr *phys_ptr, MemTxAttrs *attrs, int *prot, - target_ulong *page_size, - ARMMMUFaultInfo *fi, ARMCacheAttrs *cacheattrs) +bool get_phys_addr(CPUARMState *env, target_ulong address, + MMUAccessType access_type, ARMMMUIdx mmu_idx, + hwaddr *phys_ptr, MemTxAttrs *attrs, int *prot, + target_ulong *page_size, + ARMMMUFaultInfo *fi, ARMCacheAttrs *cacheattrs) { if (mmu_idx == ARMMMUIdx_S12NSE0 || mmu_idx == ARMMMUIdx_S12NSE1) { /* diff --git a/qemu/target/arm/internals.h b/qemu/target/arm/internals.h index a88c356f..afa3b23c 100644 --- a/qemu/target/arm/internals.h +++ b/qemu/target/arm/internals.h @@ -987,4 +987,20 @@ static inline int exception_target_el(CPUARMState *env) return target_el; } +#ifndef CONFIG_USER_ONLY + +/* Cacheability and shareability attributes for a memory access */ +typedef struct ARMCacheAttrs { + unsigned int attrs:8; /* as in the MAIR register encoding */ + unsigned int shareability:2; /* as in the SH field of the VMSAv8-64 PTEs */ +} ARMCacheAttrs; + +bool get_phys_addr(CPUARMState *env, target_ulong address, + MMUAccessType access_type, ARMMMUIdx mmu_idx, + hwaddr *phys_ptr, MemTxAttrs *attrs, int *prot, + target_ulong *page_size, + ARMMMUFaultInfo *fi, ARMCacheAttrs *cacheattrs); + +#endif /* !CONFIG_USER_ONLY */ + #endif