From 1b6cac4e7e79f03de2fa8f5ad1b000663a5e3eb5 Mon Sep 17 00:00:00 2001 From: Richard Henderson Date: Sat, 19 May 2018 23:23:06 -0400 Subject: [PATCH] target/arm: Remove floatX_maybe_silence_nan from conversions This is now handled properly by the generic softfloat code. Backports commit a9d173dc603af74102c24c1c92d479ba580bbf07 from qemu --- qemu/target/arm/helper-a64.c | 1 - qemu/target/arm/helper.c | 12 ++---------- 2 files changed, 2 insertions(+), 11 deletions(-) diff --git a/qemu/target/arm/helper-a64.c b/qemu/target/arm/helper-a64.c index 5fda8993..ead86122 100644 --- a/qemu/target/arm/helper-a64.c +++ b/qemu/target/arm/helper-a64.c @@ -464,7 +464,6 @@ float32 HELPER(fcvtx_f64_to_f32)(float64 a, CPUARMState *env) set_float_rounding_mode(float_round_to_zero, &tstat); set_float_exception_flags(0, &tstat); r = float64_to_float32(a, &tstat); - r = float32_maybe_silence_nan(r, &tstat); exflags = get_float_exception_flags(&tstat); if (exflags & float_flag_inexact) { r = make_float32(float32_val(r) | 1); diff --git a/qemu/target/arm/helper.c b/qemu/target/arm/helper.c index 32b0534b..96b838c0 100644 --- a/qemu/target/arm/helper.c +++ b/qemu/target/arm/helper.c @@ -10604,20 +10604,12 @@ FLOAT_CONVS(ui, d, 64, u) /* floating point conversion */ float64 VFP_HELPER(fcvtd, s)(float32 x, CPUARMState *env) { - float64 r = float32_to_float64(x, &env->vfp.fp_status); - /* ARM requires that S<->D conversion of any kind of NaN generates - * a quiet NaN by forcing the most significant frac bit to 1. - */ - return float64_maybe_silence_nan(r, &env->vfp.fp_status); + return float32_to_float64(x, &env->vfp.fp_status); } float32 VFP_HELPER(fcvts, d)(float64 x, CPUARMState *env) { - float32 r = float64_to_float32(x, &env->vfp.fp_status); - /* ARM requires that S<->D conversion of any kind of NaN generates - * a quiet NaN by forcing the most significant frac bit to 1. - */ - return float32_maybe_silence_nan(r, &env->vfp.fp_status); + return float64_to_float32(x, &env->vfp.fp_status); } /* VFP3 fixed point conversion. */