diff --git a/qemu/target/arm/helper.c b/qemu/target/arm/helper.c
index ef785425..51a7cb06 100644
--- a/qemu/target/arm/helper.c
+++ b/qemu/target/arm/helper.c
@@ -3836,25 +3836,25 @@ static void zcr_write(CPUARMState *env, const ARMCPRegInfo *ri,
 }
 
 static const ARMCPRegInfo zcr_el1_reginfo = {
-    "ZCR_EL1", 0,1,2, 3,0,0, ARM_CP_STATE_AA64, ARM_CP_64BIT,
+    "ZCR_EL1", 0,1,2, 3,0,0, ARM_CP_STATE_AA64, 0,
     PL1_RW, 0, NULL, 0, offsetof(CPUARMState, vfp.zcr_el[1]), {0, 0},
     zcr_access, NULL, zcr_write, NULL, raw_write
 };
 
 static const ARMCPRegInfo zcr_el2_reginfo = {
-    "ZCR_EL2", 0,1,2, 3,4,0, ARM_CP_STATE_AA64, ARM_CP_64BIT,
+    "ZCR_EL2", 0,1,2, 3,4,0, ARM_CP_STATE_AA64, 0,
     PL2_RW, 0, NULL, 0, offsetof(CPUARMState, vfp.zcr_el[2]), {0, 0},
     zcr_access, NULL, zcr_write, NULL, raw_write
 };
 
 static const ARMCPRegInfo zcr_no_el2_reginfo = {
-    "ZCR_EL2", 0,1,2, 3,4,0, ARM_CP_STATE_AA64, ARM_CP_64BIT,
+    "ZCR_EL2", 0,1,2, 3,4,0, ARM_CP_STATE_AA64, 0,
     PL2_RW, 0, NULL, 0, 0, {0, 0},
     NULL, arm_cp_read_zero, arm_cp_write_ignore
 };
 
 static const ARMCPRegInfo zcr_el3_reginfo = {
-    "ZCR_EL3", 0,1,2, 3,6,0, ARM_CP_STATE_AA64, ARM_CP_64BIT,
+    "ZCR_EL3", 0,1,2, 3,6,0, ARM_CP_STATE_AA64, 0,
     PL3_RW, 0, NULL, 0, offsetof(CPUARMState, vfp.zcr_el[3]), {0, 0},
     zcr_access, NULL, zcr_write, NULL, raw_write
 };