From 1c7f2083da60dd4398d7818e734f59beb834717b Mon Sep 17 00:00:00 2001 From: Yiting Wang Date: Sat, 21 Mar 2020 12:18:51 -0400 Subject: [PATCH] riscv: Set xPIE to 1 after xRET When executing an xRET instruction, supposing xPP holds the value y, xIE is set to xPIE; the privilege mode is changed to y; xPIE is set to 1. But QEMU sets xPIE to 0 incorrectly. Backports commit a37f21c27d3e2342c2080aafd4cfe7e949612428 from qemu --- qemu/target/riscv/op_helper.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/qemu/target/riscv/op_helper.c b/qemu/target/riscv/op_helper.c index 95d5bd19..eecdb32a 100644 --- a/qemu/target/riscv/op_helper.c +++ b/qemu/target/riscv/op_helper.c @@ -92,7 +92,7 @@ target_ulong helper_sret(CPURISCVState *env, target_ulong cpu_pc_deb) env->priv_ver >= PRIV_VERSION_1_10_0 ? MSTATUS_SIE : MSTATUS_UIE << prev_priv, get_field(mstatus, MSTATUS_SPIE)); - mstatus = set_field(mstatus, MSTATUS_SPIE, 0); + mstatus = set_field(mstatus, MSTATUS_SPIE, 1); mstatus = set_field(mstatus, MSTATUS_SPP, PRV_U); riscv_cpu_set_mode(env, prev_priv); env->mstatus = mstatus; @@ -117,7 +117,7 @@ target_ulong helper_mret(CPURISCVState *env, target_ulong cpu_pc_deb) env->priv_ver >= PRIV_VERSION_1_10_0 ? MSTATUS_MIE : MSTATUS_UIE << prev_priv, get_field(mstatus, MSTATUS_MPIE)); - mstatus = set_field(mstatus, MSTATUS_MPIE, 0); + mstatus = set_field(mstatus, MSTATUS_MPIE, 1); mstatus = set_field(mstatus, MSTATUS_MPP, PRV_U); riscv_cpu_set_mode(env, prev_priv); env->mstatus = mstatus;