From 1da5d669a767d8d4270986433f7c293e3ac45d2c Mon Sep 17 00:00:00 2001 From: Paolo Bonzini Date: Wed, 3 Mar 2021 19:09:11 -0500 Subject: [PATCH] target/i386: fix operand order for PDEP and PEXT For PDEP and PEXT, the mask is provided in the memory (mod+r/m) operand, and therefore is loaded in s->T0 by gen_ldst_modrm. The source is provided in the second source operand (VEX.vvvv) and therefore is loaded in s->T1. Fix the order in which they are passed to the helpers. Backports 75b208c28316095c4685e8596ceb9e3f656592e2 --- qemu/target/i386/translate.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/qemu/target/i386/translate.c b/qemu/target/i386/translate.c index 390905bb..0c98e3d3 100644 --- a/qemu/target/i386/translate.c +++ b/qemu/target/i386/translate.c @@ -4380,14 +4380,14 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b, } ot = mo_64_32(s->dflag); gen_ldst_modrm(env, s, modrm, ot, OR_TMP0, 0); - /* Note that by zero-extending the mask operand, we + /* Note that by zero-extending the source operand, we automatically handle zero-extending the result. */ if (ot == MO_64) { tcg_gen_mov_tl(tcg_ctx, s->T1, cpu_regs[s->vex_v]); } else { tcg_gen_ext32u_tl(tcg_ctx, s->T1, cpu_regs[s->vex_v]); } - gen_helper_pdep(tcg_ctx, cpu_regs[reg], s->T0, s->T1); + gen_helper_pdep(tcg_ctx, cpu_regs[reg], s->T1, s->T0); break; case 0x2f5: /* pext Gy, By, Ey */ @@ -4398,14 +4398,14 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b, } ot = mo_64_32(s->dflag); gen_ldst_modrm(env, s, modrm, ot, OR_TMP0, 0); - /* Note that by zero-extending the mask operand, we + /* Note that by zero-extending the source operand, we automatically handle zero-extending the result. */ if (ot == MO_64) { tcg_gen_mov_tl(tcg_ctx, s->T1, cpu_regs[s->vex_v]); } else { tcg_gen_ext32u_tl(tcg_ctx, s->T1, cpu_regs[s->vex_v]); } - gen_helper_pext(tcg_ctx, cpu_regs[reg], s->T0, s->T1); + gen_helper_pext(tcg_ctx, cpu_regs[reg], s->T1, s->T0); break; case 0x1f6: /* adcx Gy, Ey */