From 1e17cbc52c174074f1b96aae8a16ef15aaca5960 Mon Sep 17 00:00:00 2001 From: Alistair Francis Date: Sun, 22 Mar 2020 01:44:53 -0400 Subject: [PATCH] target/riscv: Remove the hret instruction The hret instruction does not exist in the new spec versions, so remove it from QEMU. Backports commit 0736febb2d0e1bb503ca07091c16a16e78480366 from qemu --- qemu/target/riscv/insn32.decode | 1 - qemu/target/riscv/insn_trans/trans_privileged.inc.c | 5 ----- 2 files changed, 6 deletions(-) diff --git a/qemu/target/riscv/insn32.decode b/qemu/target/riscv/insn32.decode index cfd9ca6d..b883672e 100644 --- a/qemu/target/riscv/insn32.decode +++ b/qemu/target/riscv/insn32.decode @@ -75,7 +75,6 @@ ecall 000000000000 00000 000 00000 1110011 ebreak 000000000001 00000 000 00000 1110011 uret 0000000 00010 00000 000 00000 1110011 sret 0001000 00010 00000 000 00000 1110011 -hret 0010000 00010 00000 000 00000 1110011 mret 0011000 00010 00000 000 00000 1110011 wfi 0001000 00101 00000 000 00000 1110011 hfence_gvma 0110001 ..... ..... 000 00000 1110011 @hfence_gvma diff --git a/qemu/target/riscv/insn_trans/trans_privileged.inc.c b/qemu/target/riscv/insn_trans/trans_privileged.inc.c index a419ddb0..f68379a8 100644 --- a/qemu/target/riscv/insn_trans/trans_privileged.inc.c +++ b/qemu/target/riscv/insn_trans/trans_privileged.inc.c @@ -59,11 +59,6 @@ static bool trans_sret(DisasContext *ctx, arg_sret *a) #endif } -static bool trans_hret(DisasContext *ctx, arg_hret *a) -{ - return false; -} - static bool trans_mret(DisasContext *ctx, arg_mret *a) { #ifndef CONFIG_USER_ONLY