From 204a4dc1d3b476ac87f536edb46b41950e588d6b Mon Sep 17 00:00:00 2001 From: Artyom Tarasenko Date: Thu, 1 Mar 2018 20:43:45 -0500 Subject: [PATCH] target-sparc: implement UltraSPARC-T1 Strand status ASR Backports commit b8e31b3cc6315bc5c6ec686c363c088c4fb1d0ea from qemu --- qemu/target-sparc/translate.c | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/qemu/target-sparc/translate.c b/qemu/target-sparc/translate.c index bfcd3330..27486900 100644 --- a/qemu/target-sparc/translate.c +++ b/qemu/target-sparc/translate.c @@ -3631,6 +3631,17 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn, bool hook_ins case 0x19: /* System tick compare */ gen_store_gpr(dc, rd, tcg_ctx->cpu_stick_cmpr); break; + case 0x1a: /* UltraSPARC-T1 Strand status */ + /* XXX HYPV check maybe not enough, UA2005 & UA2007 describe + * this ASR as impl. dep + */ + CHECK_IU_FEATURE(dc, HYPV); + { + TCGv t = gen_dest_gpr(dc, rd); + tcg_gen_movi_tl(tcg_ctx, t, 1UL); + gen_store_gpr(dc, rd, t); + } + break; case 0x10: /* Performance Control */ case 0x11: /* Performance Instrumentation Counter */ case 0x12: /* Dispatch Control */