From 2141c777f1e8b5338be8b44f6f40e8c5881695ef Mon Sep 17 00:00:00 2001 From: Pranith Kumar Date: Sat, 3 Mar 2018 22:04:08 -0500 Subject: [PATCH] util/cacheinfo: Fix warning generated by clang Clang generates the following warning on aarch64 host: CC util/cacheinfo.o /home/pranith/qemu/util/cacheinfo.c:121:48: warning: value size does not match register size specified by the constraint and modifier [-Wasm-operand-widths] asm volatile("mrs\t%0, ctr_el0" : "=r"(ctr)); ^ /home/pranith/qemu/util/cacheinfo.c:121:28: note: use constraint modifier "w" asm volatile("mrs\t%0, ctr_el0" : "=r"(ctr)); ^~ %w0 Constraint modifier 'w' is not (yet?) accepted by gcc. Fix this by increasing the ctr size. Backports commit 2ae96c157ab3155baf6595c08cf5d3fe3c023a60 from qemu --- qemu/util/cacheinfo.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/qemu/util/cacheinfo.c b/qemu/util/cacheinfo.c index e274d027..77f622f9 100644 --- a/qemu/util/cacheinfo.c +++ b/qemu/util/cacheinfo.c @@ -110,7 +110,7 @@ static void sys_cache_info(int *isize, int *dsize) static void arch_cache_info(int *isize, int *dsize) { if (*isize == 0 || *dsize == 0) { - unsigned ctr; + unsigned long ctr; /* The real cache geometry is in CCSIDR_EL1/CLIDR_EL1/CSSELR_EL1, but (at least under Linux) these are marked protected by the