From cb5bf645153d2a4a4d77628d02ff81e47af8d298 Mon Sep 17 00:00:00 2001 From: Merry Date: Tue, 15 Feb 2022 17:49:32 +0000 Subject: [PATCH] Fix build on aarch64 --- qemu/aarch64.h | 1 + qemu/aarch64eb.h | 1 + qemu/arm.h | 1 + qemu/armeb.h | 1 + qemu/configure | 2 +- qemu/header_gen.py | 1 + qemu/m68k.h | 1 + qemu/mips.h | 1 + qemu/mips64.h | 1 + qemu/mips64el.h | 1 + qemu/mipsel.h | 1 + qemu/sparc.h | 1 + qemu/sparc64.h | 1 + qemu/tcg/aarch64/tcg-target.inc.c | 54 +++++++++---------- .../{tcg-target-opc.h => tcg-target.opc.h} | 0 qemu/x86_64.h | 1 + 16 files changed, 41 insertions(+), 28 deletions(-) rename qemu/tcg/aarch64/{tcg-target-opc.h => tcg-target.opc.h} (100%) diff --git a/qemu/aarch64.h b/qemu/aarch64.h index ae03adeb..9c179b9b 100644 --- a/qemu/aarch64.h +++ b/qemu/aarch64.h @@ -2941,6 +2941,7 @@ #define tb_phys_invalidate tb_phys_invalidate_aarch64 #define tb_reset_jump tb_reset_jump_aarch64 #define tb_set_jmp_target tb_set_jmp_target_aarch64 +#define tb_target_set_jmp_target tb_target_set_jmp_target_aarch64 #define tcg_accel_class_init tcg_accel_class_init_aarch64 #define tcg_accel_type tcg_accel_type_aarch64 #define tcg_add_param_i32 tcg_add_param_i32_aarch64 diff --git a/qemu/aarch64eb.h b/qemu/aarch64eb.h index 669b3b8b..d4965d71 100644 --- a/qemu/aarch64eb.h +++ b/qemu/aarch64eb.h @@ -2941,6 +2941,7 @@ #define tb_phys_invalidate tb_phys_invalidate_aarch64eb #define tb_reset_jump tb_reset_jump_aarch64eb #define tb_set_jmp_target tb_set_jmp_target_aarch64eb +#define tb_target_set_jmp_target tb_target_set_jmp_target_aarch64eb #define tcg_accel_class_init tcg_accel_class_init_aarch64eb #define tcg_accel_type tcg_accel_type_aarch64eb #define tcg_add_param_i32 tcg_add_param_i32_aarch64eb diff --git a/qemu/arm.h b/qemu/arm.h index bbafb73e..fd788fa6 100644 --- a/qemu/arm.h +++ b/qemu/arm.h @@ -2941,6 +2941,7 @@ #define tb_phys_invalidate tb_phys_invalidate_arm #define tb_reset_jump tb_reset_jump_arm #define tb_set_jmp_target tb_set_jmp_target_arm +#define tb_target_set_jmp_target tb_target_set_jmp_target_arm #define tcg_accel_class_init tcg_accel_class_init_arm #define tcg_accel_type tcg_accel_type_arm #define tcg_add_param_i32 tcg_add_param_i32_arm diff --git a/qemu/armeb.h b/qemu/armeb.h index ac184593..c4510a86 100644 --- a/qemu/armeb.h +++ b/qemu/armeb.h @@ -2941,6 +2941,7 @@ #define tb_phys_invalidate tb_phys_invalidate_armeb #define tb_reset_jump tb_reset_jump_armeb #define tb_set_jmp_target tb_set_jmp_target_armeb +#define tb_target_set_jmp_target tb_target_set_jmp_target_armeb #define tcg_accel_class_init tcg_accel_class_init_armeb #define tcg_accel_type tcg_accel_type_armeb #define tcg_add_param_i32 tcg_add_param_i32_armeb diff --git a/qemu/configure b/qemu/configure index 0eac0ac7..14e93462 100755 --- a/qemu/configure +++ b/qemu/configure @@ -1528,7 +1528,7 @@ elif test "$ARCH" = "ppc64" ; then elif test "$ARCH" = "riscv32" || test "$ARCH" = "riscv64" ; then QEMU_INCLUDES="-I\$(SRC_PATH)/tcg/riscv $QEMU_INCLUDES" else - QEMU_INCLUDES="-I\$(SRC_PATH)/tcg/\$(ARCH) $QEMU_INCLUDES" + QEMU_INCLUDES="-I\$(SRC_PATH)/tcg/$ARCH $QEMU_INCLUDES" fi QEMU_INCLUDES="-I\$(SRC_PATH)/tcg $QEMU_INCLUDES" diff --git a/qemu/header_gen.py b/qemu/header_gen.py index 3b6724f6..86214e8a 100644 --- a/qemu/header_gen.py +++ b/qemu/header_gen.py @@ -2947,6 +2947,7 @@ symbols = ( 'tb_phys_invalidate', 'tb_reset_jump', 'tb_set_jmp_target', + 'tb_target_set_jmp_target', 'tcg_accel_class_init', 'tcg_accel_type', 'tcg_add_param_i32', diff --git a/qemu/m68k.h b/qemu/m68k.h index 2ddb1e42..8441f7e6 100644 --- a/qemu/m68k.h +++ b/qemu/m68k.h @@ -2941,6 +2941,7 @@ #define tb_phys_invalidate tb_phys_invalidate_m68k #define tb_reset_jump tb_reset_jump_m68k #define tb_set_jmp_target tb_set_jmp_target_m68k +#define tb_target_set_jmp_target tb_target_set_jmp_target_m68k #define tcg_accel_class_init tcg_accel_class_init_m68k #define tcg_accel_type tcg_accel_type_m68k #define tcg_add_param_i32 tcg_add_param_i32_m68k diff --git a/qemu/mips.h b/qemu/mips.h index 5abc0ff5..83eaec35 100644 --- a/qemu/mips.h +++ b/qemu/mips.h @@ -2941,6 +2941,7 @@ #define tb_phys_invalidate tb_phys_invalidate_mips #define tb_reset_jump tb_reset_jump_mips #define tb_set_jmp_target tb_set_jmp_target_mips +#define tb_target_set_jmp_target tb_target_set_jmp_target_mips #define tcg_accel_class_init tcg_accel_class_init_mips #define tcg_accel_type tcg_accel_type_mips #define tcg_add_param_i32 tcg_add_param_i32_mips diff --git a/qemu/mips64.h b/qemu/mips64.h index 040d29b5..7a54b649 100644 --- a/qemu/mips64.h +++ b/qemu/mips64.h @@ -2941,6 +2941,7 @@ #define tb_phys_invalidate tb_phys_invalidate_mips64 #define tb_reset_jump tb_reset_jump_mips64 #define tb_set_jmp_target tb_set_jmp_target_mips64 +#define tb_target_set_jmp_target tb_target_set_jmp_target_mips64 #define tcg_accel_class_init tcg_accel_class_init_mips64 #define tcg_accel_type tcg_accel_type_mips64 #define tcg_add_param_i32 tcg_add_param_i32_mips64 diff --git a/qemu/mips64el.h b/qemu/mips64el.h index c0c5fb9f..152b1d39 100644 --- a/qemu/mips64el.h +++ b/qemu/mips64el.h @@ -2941,6 +2941,7 @@ #define tb_phys_invalidate tb_phys_invalidate_mips64el #define tb_reset_jump tb_reset_jump_mips64el #define tb_set_jmp_target tb_set_jmp_target_mips64el +#define tb_target_set_jmp_target tb_target_set_jmp_target_mips64el #define tcg_accel_class_init tcg_accel_class_init_mips64el #define tcg_accel_type tcg_accel_type_mips64el #define tcg_add_param_i32 tcg_add_param_i32_mips64el diff --git a/qemu/mipsel.h b/qemu/mipsel.h index 0e4f4217..09a41e1e 100644 --- a/qemu/mipsel.h +++ b/qemu/mipsel.h @@ -2941,6 +2941,7 @@ #define tb_phys_invalidate tb_phys_invalidate_mipsel #define tb_reset_jump tb_reset_jump_mipsel #define tb_set_jmp_target tb_set_jmp_target_mipsel +#define tb_target_set_jmp_target tb_target_set_jmp_target_mipsel #define tcg_accel_class_init tcg_accel_class_init_mipsel #define tcg_accel_type tcg_accel_type_mipsel #define tcg_add_param_i32 tcg_add_param_i32_mipsel diff --git a/qemu/sparc.h b/qemu/sparc.h index a2c78c82..aafca127 100644 --- a/qemu/sparc.h +++ b/qemu/sparc.h @@ -2941,6 +2941,7 @@ #define tb_phys_invalidate tb_phys_invalidate_sparc #define tb_reset_jump tb_reset_jump_sparc #define tb_set_jmp_target tb_set_jmp_target_sparc +#define tb_target_set_jmp_target tb_target_set_jmp_target_sparc #define tcg_accel_class_init tcg_accel_class_init_sparc #define tcg_accel_type tcg_accel_type_sparc #define tcg_add_param_i32 tcg_add_param_i32_sparc diff --git a/qemu/sparc64.h b/qemu/sparc64.h index 84e8f61e..c75032be 100644 --- a/qemu/sparc64.h +++ b/qemu/sparc64.h @@ -2941,6 +2941,7 @@ #define tb_phys_invalidate tb_phys_invalidate_sparc64 #define tb_reset_jump tb_reset_jump_sparc64 #define tb_set_jmp_target tb_set_jmp_target_sparc64 +#define tb_target_set_jmp_target tb_target_set_jmp_target_sparc64 #define tcg_accel_class_init tcg_accel_class_init_sparc64 #define tcg_accel_type tcg_accel_type_sparc64 #define tcg_add_param_i32 tcg_add_param_i32_sparc64 diff --git a/qemu/tcg/aarch64/tcg-target.inc.c b/qemu/tcg/aarch64/tcg-target.inc.c index 0afc86b9..42ef58c2 100644 --- a/qemu/tcg/aarch64/tcg-target.inc.c +++ b/qemu/tcg/aarch64/tcg-target.inc.c @@ -1871,7 +1871,7 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, { /* 99% of the time, we can signal the use of extension registers by looking to see if the opcode handles 64-bit data. */ - TCGType ext = (tcg_op_defs[opc].flags & TCG_OPF_64BIT) != 0; + TCGType ext = (s->tcg_op_defs[opc].flags & TCG_OPF_64BIT) != 0; /* Hoist the loads of the most common arguments. */ TCGArg a0 = args[0]; @@ -1922,7 +1922,7 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, break; case INDEX_op_br: - tcg_out_goto_label(s, arg_label(a0)); + tcg_out_goto_label(s, arg_label(s, a0)); break; case INDEX_op_ld8u_i32: @@ -2154,7 +2154,7 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, a1 = (int32_t)a1; /* FALLTHRU */ case INDEX_op_brcond_i64: - tcg_out_brcond(s, ext, a2, a0, a1, const_args[1], arg_label(args[3])); + tcg_out_brcond(s, ext, a2, a0, a1, const_args[1], arg_label(s, args[3])); break; case INDEX_op_setcond_i32: @@ -2835,31 +2835,31 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op) static void tcg_target_init(TCGContext *s) { - tcg_target_available_regs[TCG_TYPE_I32] = 0xffffffffu; - tcg_target_available_regs[TCG_TYPE_I64] = 0xffffffffu; - tcg_target_available_regs[TCG_TYPE_V64] = 0xffffffff00000000ull; - tcg_target_available_regs[TCG_TYPE_V128] = 0xffffffff00000000ull; + s->tcg_target_available_regs[TCG_TYPE_I32] = 0xffffffffu; + s->tcg_target_available_regs[TCG_TYPE_I64] = 0xffffffffu; + s->tcg_target_available_regs[TCG_TYPE_V64] = 0xffffffff00000000ull; + s->tcg_target_available_regs[TCG_TYPE_V128] = 0xffffffff00000000ull; - tcg_target_call_clobber_regs = -1ull; - tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_X19); - tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_X20); - tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_X21); - tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_X22); - tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_X23); - tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_X24); - tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_X25); - tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_X26); - tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_X27); - tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_X28); - tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_X29); - tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_V8); - tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_V9); - tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_V10); - tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_V11); - tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_V12); - tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_V13); - tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_V14); - tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_V15); + s->tcg_target_call_clobber_regs = -1ull; + tcg_regset_reset_reg(s->tcg_target_call_clobber_regs, TCG_REG_X19); + tcg_regset_reset_reg(s->tcg_target_call_clobber_regs, TCG_REG_X20); + tcg_regset_reset_reg(s->tcg_target_call_clobber_regs, TCG_REG_X21); + tcg_regset_reset_reg(s->tcg_target_call_clobber_regs, TCG_REG_X22); + tcg_regset_reset_reg(s->tcg_target_call_clobber_regs, TCG_REG_X23); + tcg_regset_reset_reg(s->tcg_target_call_clobber_regs, TCG_REG_X24); + tcg_regset_reset_reg(s->tcg_target_call_clobber_regs, TCG_REG_X25); + tcg_regset_reset_reg(s->tcg_target_call_clobber_regs, TCG_REG_X26); + tcg_regset_reset_reg(s->tcg_target_call_clobber_regs, TCG_REG_X27); + tcg_regset_reset_reg(s->tcg_target_call_clobber_regs, TCG_REG_X28); + tcg_regset_reset_reg(s->tcg_target_call_clobber_regs, TCG_REG_X29); + tcg_regset_reset_reg(s->tcg_target_call_clobber_regs, TCG_REG_V8); + tcg_regset_reset_reg(s->tcg_target_call_clobber_regs, TCG_REG_V9); + tcg_regset_reset_reg(s->tcg_target_call_clobber_regs, TCG_REG_V10); + tcg_regset_reset_reg(s->tcg_target_call_clobber_regs, TCG_REG_V11); + tcg_regset_reset_reg(s->tcg_target_call_clobber_regs, TCG_REG_V12); + tcg_regset_reset_reg(s->tcg_target_call_clobber_regs, TCG_REG_V13); + tcg_regset_reset_reg(s->tcg_target_call_clobber_regs, TCG_REG_V14); + tcg_regset_reset_reg(s->tcg_target_call_clobber_regs, TCG_REG_V15); s->reserved_regs = 0; tcg_regset_set_reg(s->reserved_regs, TCG_REG_SP); diff --git a/qemu/tcg/aarch64/tcg-target-opc.h b/qemu/tcg/aarch64/tcg-target.opc.h similarity index 100% rename from qemu/tcg/aarch64/tcg-target-opc.h rename to qemu/tcg/aarch64/tcg-target.opc.h diff --git a/qemu/x86_64.h b/qemu/x86_64.h index 5a30a8c2..8f756c59 100644 --- a/qemu/x86_64.h +++ b/qemu/x86_64.h @@ -2941,6 +2941,7 @@ #define tb_phys_invalidate tb_phys_invalidate_x86_64 #define tb_reset_jump tb_reset_jump_x86_64 #define tb_set_jmp_target tb_set_jmp_target_x86_64 +#define tb_target_set_jmp_target tb_target_set_jmp_target_x86_64 #define tcg_accel_class_init tcg_accel_class_init_x86_64 #define tcg_accel_type tcg_accel_type_x86_64 #define tcg_add_param_i32 tcg_add_param_i32_x86_64