From 2389a5468c2fc0f8c96fa57186b7800305ac1f87 Mon Sep 17 00:00:00 2001 From: Stefan Markovic Date: Mon, 27 Aug 2018 04:15:22 -0400 Subject: [PATCH] target/mips: Prevent switching mode related to Config3 ISA bit for nanoMIPS Only if Config3.ISA is 3 (microMIPS), the mode should be switched in cpu_state_reset(). Config3.ISA is 1 for nanoMIPS processors, and no mode change should happen. Backports commit 0bbc0396809f6caaaf96863dafe738e94f9b73ea from qemu --- qemu/target/mips/translate.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/qemu/target/mips/translate.c b/qemu/target/mips/translate.c index 6e6231a7..c7f22b1e 100644 --- a/qemu/target/mips/translate.c +++ b/qemu/target/mips/translate.c @@ -21986,8 +21986,8 @@ void cpu_state_reset(CPUMIPSState *env) env->CP0_Status |= (1 << CP0St_FR); } - if (env->CP0_Config3 & (1 << CP0C3_ISA)) { - /* microMIPS on reset when Config3.ISA == {1, 3} */ + if (env->CP0_Config3 & (1 << CP0C3_ISA) & (1 << (CP0C3_ISA + 1))) { + /* microMIPS on reset when Config3.ISA is 3 */ env->hflags |= MIPS_HFLAG_M16; }