From 23dc2fb4a2905f195a37a5b8b9a8045b8f82a397 Mon Sep 17 00:00:00 2001
From: Lioncash <mathew1800@gmail.com>
Date: Sun, 7 Mar 2021 13:03:51 -0500
Subject: [PATCH] target/riscv: Enable vector extensions

---
 qemu/target/riscv/cpu.c | 5 +++++
 qemu/target/riscv/cpu.h | 5 ++++-
 2 files changed, 9 insertions(+), 1 deletion(-)

diff --git a/qemu/target/riscv/cpu.c b/qemu/target/riscv/cpu.c
index d5a94fb9..0c4b3163 100644
--- a/qemu/target/riscv/cpu.c
+++ b/qemu/target/riscv/cpu.c
@@ -308,6 +308,11 @@ static void riscv_cpu_reset(CPUState *cs)
     cs->exception_index = EXCP_NONE;
     env->load_res = -1;
     set_default_nan_mode(1, &env->fp_status);
+
+    // Unicorn: Allow vector operations.
+    cpu->cfg.ext_v = true;
+    cpu->cfg.elen = 64;
+    cpu->cfg.vlen = 128;
 }
 
 // Unicorn: if'd out
diff --git a/qemu/target/riscv/cpu.h b/qemu/target/riscv/cpu.h
index 9ce5f70e..ea3ede80 100644
--- a/qemu/target/riscv/cpu.h
+++ b/qemu/target/riscv/cpu.h
@@ -97,7 +97,7 @@ typedef struct CPURISCVState CPURISCVState;
 
 #include "pmp.h"
 
-#define RV_VLEN_MAX 512
+#define RV_VLEN_MAX 256
 
 FIELD(VTYPE, VLMUL, 0, 2)
 FIELD(VTYPE, VSEW, 2, 3)
@@ -287,8 +287,11 @@ typedef struct RISCVCPU {
     CPURISCVState env;
 
     struct {
+        bool ext_v;
+
         bool ext_ifencei;
         bool ext_icsr;
+        char *vext_spec;
         uint16_t vlen;
         uint16_t elen;
     } cfg;