From 25a077695881120f8f9ae15126963213d75b5430 Mon Sep 17 00:00:00 2001
From: Yongbok Kim <yongbok.kim@imgtec.com>
Date: Wed, 14 Feb 2018 21:01:29 -0500
Subject: [PATCH] target-mips: update mips32r5-generic into P5600

As full specification of P5600 is available, mips32r5-generic should
be renamed to P5600 and corrected as its intention.
Correct PRid and detail of configuration.
Features which are not currently supported are described as FIXME.

Fix Config.MM bit location

Backports commit aff2bc6dc6d839caf6df0900437cc2cc9e180605 from qemu
---
 qemu/target-mips/cpu.h            |  2 +-
 qemu/target-mips/translate_init.c | 53 +++++++++++++++++--------------
 2 files changed, 31 insertions(+), 24 deletions(-)

diff --git a/qemu/target-mips/cpu.h b/qemu/target-mips/cpu.h
index a8f69fc9..05a456b1 100644
--- a/qemu/target-mips/cpu.h
+++ b/qemu/target-mips/cpu.h
@@ -396,7 +396,7 @@ struct CPUMIPSState {
 #define CP0C0_K23  28
 #define CP0C0_KU   25
 #define CP0C0_MDU  20
-#define CP0C0_MM   17
+#define CP0C0_MM   18
 #define CP0C0_BM   16
 #define CP0C0_BE   15
 #define CP0C0_AT   13
diff --git a/qemu/target-mips/translate_init.c b/qemu/target-mips/translate_init.c
index 4ebdb0d2..5f454b96 100644
--- a/qemu/target-mips/translate_init.c
+++ b/qemu/target-mips/translate_init.c
@@ -489,43 +489,50 @@ static const mips_def_t mips_defs[] =
         MMU_TYPE_R4000,
     },
     {
-        /* A generic CPU providing MIPS32 Release 5 features.
-           FIXME: Eventually this should be replaced by a real CPU model. */
-        "mips32r5-generic",
-        0x00019700,
-        MIPS_CONFIG0 | (0x1 << CP0C0_AR) |
+        /* FIXME:
+         * Config3: CMGCR, SC, PW, VZ, CTXTC, CDMM, TL
+         * Config4: MMUExtDef
+         * Config5: EVA, MRP
+         * FIR(FCR0): Has2008
+         * */
+        "P5600",
+        0x0001A800,
+        MIPS_CONFIG0 | (1 << CP0C0_MM) | (1 << CP0C0_AR) |
                     (MMU_TYPE_R4000 << CP0C0_MT),
-        MIPS_CONFIG1 | (1 << CP0C1_FP) | (15 << CP0C1_MMU) |
-                       (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) |
-                       (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) |
-                       (1 << CP0C1_CA),
+        MIPS_CONFIG1 | (0x3F << CP0C1_MMU) |
+                       (2 << CP0C1_IS) | (4 << CP0C1_IL) | (3 << CP0C1_IA) |
+                       (2 << CP0C1_DS) | (4 << CP0C1_DL) | (3 << CP0C1_DA) |
+                       (1 << CP0C1_PC) | (1 << CP0C1_FP),
         MIPS_CONFIG2,
-        MIPS_CONFIG3 | (1U << CP0C3_M) | (1 << CP0C3_MSAP) | (1 << CP0C3_LPA),
-        MIPS_CONFIG4 | (1U << CP0C4_M),
+        MIPS_CONFIG3 | (1U << CP0C3_M) | (1 << CP0C3_MSAP) |
+                       (1 << CP0C3_BP) | (1 << CP0C3_BI) | (1 << CP0C3_ULRI) |
+                       (1 << CP0C3_RXI) | (1 << CP0C3_LPA) | (1 << CP0C3_VInt),
+        MIPS_CONFIG4 | (1U << CP0C4_M) | (2 << CP0C4_IE) |
+                       (0x1c << CP0C4_KScrExist),
+        0,
+        MIPS_CONFIG5 | (1 << CP0C5_MVH) | (1 << CP0C5_LLB),
+        (1 << CP0C5_K) | (1 << CP0C5_CV) |
+                         (1 << CP0C5_MSAEn) | (1 << CP0C5_UFE) |
+                         (1 << CP0C5_FRE) | (1 << CP0C5_UFR),
         0,
-        MIPS_CONFIG5 | (1 << CP0C5_UFR) | (1 << CP0C5_LLB) | (1 << CP0C5_MVH),
-        (0 << CP0C5_M) | (1 << CP0C5_K) |
-                                  (1 << CP0C5_CV) | (0 << CP0C5_EVA) |
-                                  (1 << CP0C5_MSAEn) | (1 << CP0C5_UFR) |
-                                  (0 << CP0C5_NFExists),
         0,
         0,
         0,
-        4,
         32,
         2,
-        0x3778FF1F,
+        0x3C68FF1F,
         0,
         0,
-        (1 << FCR0_UFRP) | (1 << FCR0_F64) | (1 << FCR0_L) |
-                    (1 << FCR0_W) | (1 << FCR0_D) | (1 << FCR0_S) |
-                    (0x93 << FCR0_PRID),
+        (1 << FCR0_FREP) | (1 << FCR0_UFRP) | (1 << FCR0_F64) |
+                           (1 << FCR0_L) | (1 << FCR0_W) | (1 << FCR0_D) |
+                           (1 << FCR0_S) | (0x03 << FCR0_PRID),
         0,
         32,
         40,
         0,0, 0,0, 0,0, 0,0, 0,0,
-        (1 << CP0PG_ELPA), 0,
-        CPU_MIPS32R5 | ASE_MIPS16 | ASE_MSA,
+        (1U << CP0PG_RIE) | (1 << CP0PG_XIE) | (1 << CP0PG_ELPA) | (1 << CP0PG_IEC),
+        0,
+        CPU_MIPS32R5 | ASE_MSA,
         MMU_TYPE_R4000,
     },
     {