From 270808e22e3bb4e2f6e8fd58480fe210df0b8c1e Mon Sep 17 00:00:00 2001 From: Alistair Francis Date: Sun, 22 Mar 2020 01:51:39 -0400 Subject: [PATCH] target/riscv: Mark both sstatus and msstatus_hs as dirty Mark both sstatus and vsstatus as dirty (3). Backports commit 45b4dc8b403aa5473ec015336adf7d14d88e85c5 from qemu --- qemu/target/riscv/translate.c | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/qemu/target/riscv/translate.c b/qemu/target/riscv/translate.c index 0460d8f7..f5f157b0 100644 --- a/qemu/target/riscv/translate.c +++ b/qemu/target/riscv/translate.c @@ -42,6 +42,7 @@ typedef struct DisasContext { /* pc_succ_insn points to the instruction following base.pc_next */ target_ulong pc_succ_insn; target_ulong priv_ver; + bool virt_enabled; uint32_t opcode; uint32_t mstatus_fs; uint32_t misa; @@ -418,6 +419,12 @@ static void mark_fs_dirty(DisasContext *ctx) tcg_gen_ld_tl(tcg_ctx, tmp, tcg_ctx->cpu_env, offsetof(CPURISCVState, mstatus)); tcg_gen_ori_tl(tcg_ctx, tmp, tmp, MSTATUS_FS | MSTATUS_SD); tcg_gen_st_tl(tcg_ctx, tmp, tcg_ctx->cpu_env, offsetof(CPURISCVState, mstatus)); + + if (ctx->virt_enabled) { + tcg_gen_ld_tl(tcg_ctx, tmp, tcg_ctx->cpu_env, offsetof(CPURISCVState, mstatus_hs)); + tcg_gen_ori_tl(tcg_ctx, tmp, tmp, MSTATUS_FS | MSTATUS_SD); + tcg_gen_st_tl(tcg_ctx, tmp, tcg_ctx->cpu_env, offsetof(CPURISCVState, mstatus_hs)); + } tcg_temp_free(tcg_ctx, tmp); } #else @@ -772,6 +779,11 @@ static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs) ctx->mem_idx = ctx->base.tb->flags & TB_FLAGS_MMU_MASK; ctx->mstatus_fs = ctx->base.tb->flags & TB_FLAGS_MSTATUS_FS; ctx->priv_ver = env->priv_ver; +#if !defined(CONFIG_USER_ONLY) + ctx->virt_enabled = riscv_cpu_virt_enabled(env); +#else + ctx->virt_enabled = false; +#endif ctx->misa = env->misa; ctx->frm = -1; /* unknown rounding mode */ ctx->ext_ifencei = cpu->cfg.ext_ifencei;