diff --git a/qemu/target-arm/helper.c b/qemu/target-arm/helper.c
index 2f72c7ef..e9b22a15 100644
--- a/qemu/target-arm/helper.c
+++ b/qemu/target-arm/helper.c
@@ -929,6 +929,9 @@ static const ARMCPRegInfo v7_cp_reginfo[] = {
     { "PMOVSR", 15,9,12, 0,0,3, 0,
       0, PL0_RW, 0, NULL, 0, offsetof(CPUARMState, cp15.c9_pmovsr), {0, 0},
       pmreg_access, NULL, pmovsr_write, NULL, raw_write },
+    { "PMOVSCLR_EL0", 0,9,12, 3,3,3, ARM_CP_STATE_AA64, ARM_CP_ALIAS,
+      PL0_RW, 0, NULL, 0, offsetof(CPUARMState, cp15.c9_pmovsr), {0, 0},
+      pmreg_access, NULL, pmovsr_write, NULL, raw_write },
     /* Unimplemented so WI. */
     { "PMSWINC", 15,9,12, 0,0,4, 0,
       ARM_CP_NOP, PL0_W, 0, NULL, 0, 0, {0, 0},
@@ -966,6 +969,9 @@ static const ARMCPRegInfo v7_cp_reginfo[] = {
     { "PMINTENCLR", 15,9,14, 0,0,2, 0,
       ARM_CP_ALIAS, PL1_RW, 0, NULL, 0, offsetof(CPUARMState, cp15.c9_pminten), {0, 0},
       NULL, NULL, pmintenclr_write, },
+    { "PMINTENCLR_EL1", 0,9,14, 3,0,2, ARM_CP_STATE_AA64, ARM_CP_ALIAS,
+      PL1_RW, 0, NULL, 0, offsetof(CPUARMState, cp15.c9_pminten), {0, 0},
+      NULL, NULL, pmintenclr_write },
     { "CCSIDR", 0,0,0, 3,1,0, ARM_CP_STATE_BOTH,
       ARM_CP_NO_RAW, PL1_R, 0, NULL, 0, 0, {0, 0},
       NULL, ccsidr_read, },