From 2a968bb547a434410d802c0f375b974cf1e60116 Mon Sep 17 00:00:00 2001
From: Leon Alrae <leon.alrae@imgtec.com>
Date: Thu, 15 Feb 2018 16:30:43 -0500
Subject: [PATCH] target-mips: correct MTC0 instruction on MIPS64

MTC0 on a 64-bit processor should move entire 64-bit GPR content to CP0
register.

Backports commit d54a299b83a07642c85a22bfe19b69ca4def9ec4 from qemu
---
 qemu/target-mips/translate.c | 19 +++++++------------
 1 file changed, 7 insertions(+), 12 deletions(-)

diff --git a/qemu/target-mips/translate.c b/qemu/target-mips/translate.c
index ed92220a..f1b0a5e1 100644
--- a/qemu/target-mips/translate.c
+++ b/qemu/target-mips/translate.c
@@ -4831,13 +4831,6 @@ static inline void gen_mtc0_store32 (DisasContext *ctx, TCGv arg, target_ulong o
     tcg_temp_free_i32(tcg_ctx, t0);
 }
 
-static inline void gen_mtc0_store64 (DisasContext *ctx, TCGv arg, target_ulong off)
-{
-    TCGContext *tcg_ctx = ctx->uc->tcg_ctx;
-    tcg_gen_ext32s_tl(tcg_ctx, arg, arg);
-    tcg_gen_st_tl(tcg_ctx, arg, tcg_ctx->cpu_env, off);
-}
-
 static void gen_mfhc0(DisasContext *ctx, TCGv arg, int reg, int sel)
 {
     TCGContext *s = ctx->uc->tcg_ctx;
@@ -5701,12 +5694,14 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
             break;
         case 5:
             CP0_CHECK(ctx->insn_flags & ASE_MT);
-            gen_mtc0_store64(ctx, arg, offsetof(CPUMIPSState, CP0_VPESchedule));
+            tcg_gen_st_tl(tcg_ctx, arg, tcg_ctx->cpu_env,
+                          offsetof(CPUMIPSState, CP0_VPESchedule));
             rn = "VPESchedule";
             break;
         case 6:
             CP0_CHECK(ctx->insn_flags & ASE_MT);
-            gen_mtc0_store64(ctx, arg, offsetof(CPUMIPSState, CP0_VPEScheFBack));
+            tcg_gen_st_tl(tcg_ctx, arg, tcg_ctx->cpu_env,
+                          offsetof(CPUMIPSState, CP0_VPEScheFBack));
             rn = "VPEScheFBack";
             break;
         case 7:
@@ -5955,7 +5950,7 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
     case 14:
         switch (sel) {
         case 0:
-            gen_mtc0_store64(ctx, arg, offsetof(CPUMIPSState, CP0_EPC));
+            tcg_gen_st_tl(tcg_ctx, arg, tcg_ctx->cpu_env, offsetof(CPUMIPSState, CP0_EPC));
             rn = "EPC";
             break;
         default:
@@ -6128,7 +6123,7 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
         switch (sel) {
         case 0:
             /* EJTAG support */
-            gen_mtc0_store64(ctx, arg, offsetof(CPUMIPSState, CP0_DEPC));
+            tcg_gen_st_tl(tcg_ctx, arg, tcg_ctx->cpu_env, offsetof(CPUMIPSState, CP0_DEPC));
             rn = "DEPC";
             break;
         default:
@@ -6231,7 +6226,7 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
     case 30:
         switch (sel) {
         case 0:
-            gen_mtc0_store64(ctx, arg, offsetof(CPUMIPSState, CP0_ErrorEPC));
+            tcg_gen_st_tl(tcg_ctx, arg, tcg_ctx->cpu_env, offsetof(CPUMIPSState, CP0_ErrorEPC));
             rn = "ErrorEPC";
             break;
         default: