From 2c091e5fb8dc6c32d81de3dc47c3daa524c02e72 Mon Sep 17 00:00:00 2001 From: Richard Henderson Date: Sun, 11 Feb 2018 15:13:29 -0500 Subject: [PATCH] target-arm: Add condexec state to insn_start Backports commit 52e971d9ff67e340ac2a86bd67e14bd31c7991e0 from qemu --- qemu/target-arm/cpu.h | 1 + qemu/target-arm/translate-a64.c | 2 +- qemu/target-arm/translate.c | 3 ++- 3 files changed, 4 insertions(+), 2 deletions(-) diff --git a/qemu/target-arm/cpu.h b/qemu/target-arm/cpu.h index bd073c9b..bc1bd45a 100644 --- a/qemu/target-arm/cpu.h +++ b/qemu/target-arm/cpu.h @@ -102,6 +102,7 @@ typedef uint32_t ARMReadCPFunc(void *opaque, int cp_info, struct arm_boot_info; #define NB_MMU_MODES 4 +#define TARGET_INSN_START_EXTRA_WORDS 1 /* We currently assume float and double are IEEE single and double precision respectively. diff --git a/qemu/target-arm/translate-a64.c b/qemu/target-arm/translate-a64.c index adde3896..75e1df2d 100644 --- a/qemu/target-arm/translate-a64.c +++ b/qemu/target-arm/translate-a64.c @@ -11279,7 +11279,7 @@ void gen_intermediate_code_internal_a64(ARMCPU *cpu, tcg_ctx->gen_opc_instr_start[lj] = 1; //tcg_ctx->gen_opc_icount[lj] = num_insns; } - tcg_gen_insn_start(tcg_ctx, dc->pc); + tcg_gen_insn_start(tcg_ctx, dc->pc, 0); num_insns++; //if (num_insns == max_insns && (tb->cflags & CF_LAST_IO)) { diff --git a/qemu/target-arm/translate.c b/qemu/target-arm/translate.c index 4c6af1b4..d1f25df2 100644 --- a/qemu/target-arm/translate.c +++ b/qemu/target-arm/translate.c @@ -11477,7 +11477,8 @@ static inline void gen_intermediate_code_internal(ARMCPU *cpu, tcg_ctx->gen_opc_instr_start[lj] = 1; //tcg_ctx->gen_opc_icount[lj] = num_insns; } - tcg_gen_insn_start(tcg_ctx, dc->pc); + tcg_gen_insn_start(tcg_ctx, dc->pc, + (dc->condexec_cond << 4) | (dc->condexec_mask >> 1)); num_insns++; //if (num_insns == max_insns && (tb->cflags & CF_LAST_IO)) {