From 2cf34e1b5507b6fd1430436d1c6ed6c3369e7937 Mon Sep 17 00:00:00 2001 From: Richard Henderson <rth@twiddle.net> Date: Thu, 1 Mar 2018 15:53:35 -0500 Subject: [PATCH] tcg: Add clz and ctz opcodes Backports commit 0e28d0063bbd9e59a981ea2d20f82f30c5d956a8 from qemu --- qemu/aarch64.h | 12 +++ qemu/aarch64eb.h | 12 +++ qemu/arm.h | 12 +++ qemu/armeb.h | 12 +++ qemu/header_gen.py | 12 +++ qemu/m68k.h | 12 +++ qemu/mips.h | 12 +++ qemu/mips64.h | 12 +++ qemu/mips64el.h | 12 +++ qemu/mipsel.h | 12 +++ qemu/powerpc.h | 12 +++ qemu/sparc.h | 12 +++ qemu/sparc64.h | 12 +++ qemu/tcg-runtime.c | 20 +++++ qemu/tcg/README | 8 ++ qemu/tcg/aarch64/tcg-target.h | 4 + qemu/tcg/arm/tcg-target.h | 2 + qemu/tcg/i386/tcg-target.h | 4 + qemu/tcg/mips/tcg-target.h | 2 + qemu/tcg/optimize.c | 36 +++++++++ qemu/tcg/ppc/tcg-target.h | 4 + qemu/tcg/s390/tcg-target.h | 4 + qemu/tcg/sparc/tcg-target.h | 4 + qemu/tcg/tcg-op.c | 143 ++++++++++++++++++++++++++++++++++ qemu/tcg/tcg-op.h | 16 ++++ qemu/tcg/tcg-opc.h | 4 + qemu/tcg/tcg-runtime.h | 5 ++ qemu/tcg/tcg.h | 4 +- qemu/x86_64.h | 12 +++ 29 files changed, 427 insertions(+), 1 deletion(-) diff --git a/qemu/aarch64.h b/qemu/aarch64.h index a9096713..adee44d1 100644 --- a/qemu/aarch64.h +++ b/qemu/aarch64.h @@ -1566,6 +1566,10 @@ #define helper_be_stw_mmu helper_be_stw_mmu_aarch64 #define helper_clear_pstate_ss helper_clear_pstate_ss_aarch64 #define helper_clz_arm helper_clz_arm_aarch64 +#define helper_clz_i32 helper_clz_i32_aarch64 +#define helper_clz_i64 helper_clz_i64_aarch64 +#define helper_ctz_i32 helper_ctz_i32_aarch64 +#define helper_ctz_i64 helper_ctz_i64_aarch64 #define helper_cpsr_read helper_cpsr_read_aarch64 #define helper_cpsr_write helper_cpsr_write_aarch64 #define helper_cpsr_write_eret helper_cpsr_write_eret_aarch64 @@ -3007,6 +3011,14 @@ #define tcg_gen_bswap32_i64 tcg_gen_bswap32_i64_aarch64 #define tcg_gen_bswap64_i64 tcg_gen_bswap64_i64_aarch64 #define tcg_gen_callN tcg_gen_callN_aarch64 +#define tcg_gen_clz_i32 tcg_gen_clz_i32_aarch64 +#define tcg_gen_clz_i64 tcg_gen_clz_i64_aarch64 +#define tcg_gen_clzi_i32 tcg_gen_clzi_i32_aarch64 +#define tcg_gen_clzi_i64 tcg_gen_clzi_i64_aarch64 +#define tcg_gen_ctz_i32 tcg_gen_ctz_i32_aarch64 +#define tcg_gen_ctz_i64 tcg_gen_ctz_i64_aarch64 +#define tcg_gen_ctzi_i32 tcg_gen_ctzi_i32_aarch64 +#define tcg_gen_ctzi_i64 tcg_gen_ctzi_i64_aarch64 #define tcg_gen_code tcg_gen_code_aarch64 #define tcg_gen_concat_i32_i64 tcg_gen_concat_i32_i64_aarch64 #define tcg_gen_deposit_i32 tcg_gen_deposit_i32_aarch64 diff --git a/qemu/aarch64eb.h b/qemu/aarch64eb.h index d15170b0..18ce3abd 100644 --- a/qemu/aarch64eb.h +++ b/qemu/aarch64eb.h @@ -1566,6 +1566,10 @@ #define helper_be_stw_mmu helper_be_stw_mmu_aarch64eb #define helper_clear_pstate_ss helper_clear_pstate_ss_aarch64eb #define helper_clz_arm helper_clz_arm_aarch64eb +#define helper_clz_i32 helper_clz_i32_aarch64eb +#define helper_clz_i64 helper_clz_i64_aarch64eb +#define helper_ctz_i32 helper_ctz_i32_aarch64eb +#define helper_ctz_i64 helper_ctz_i64_aarch64eb #define helper_cpsr_read helper_cpsr_read_aarch64eb #define helper_cpsr_write helper_cpsr_write_aarch64eb #define helper_cpsr_write_eret helper_cpsr_write_eret_aarch64eb @@ -3007,6 +3011,14 @@ #define tcg_gen_bswap32_i64 tcg_gen_bswap32_i64_aarch64eb #define tcg_gen_bswap64_i64 tcg_gen_bswap64_i64_aarch64eb #define tcg_gen_callN tcg_gen_callN_aarch64eb +#define tcg_gen_clz_i32 tcg_gen_clz_i32_aarch64eb +#define tcg_gen_clz_i64 tcg_gen_clz_i64_aarch64eb +#define tcg_gen_clzi_i32 tcg_gen_clzi_i32_aarch64eb +#define tcg_gen_clzi_i64 tcg_gen_clzi_i64_aarch64eb +#define tcg_gen_ctz_i32 tcg_gen_ctz_i32_aarch64eb +#define tcg_gen_ctz_i64 tcg_gen_ctz_i64_aarch64eb +#define tcg_gen_ctzi_i32 tcg_gen_ctzi_i32_aarch64eb +#define tcg_gen_ctzi_i64 tcg_gen_ctzi_i64_aarch64eb #define tcg_gen_code tcg_gen_code_aarch64eb #define tcg_gen_concat_i32_i64 tcg_gen_concat_i32_i64_aarch64eb #define tcg_gen_deposit_i32 tcg_gen_deposit_i32_aarch64eb diff --git a/qemu/arm.h b/qemu/arm.h index c2a170d6..1a836fc4 100644 --- a/qemu/arm.h +++ b/qemu/arm.h @@ -1566,6 +1566,10 @@ #define helper_be_stw_mmu helper_be_stw_mmu_arm #define helper_clear_pstate_ss helper_clear_pstate_ss_arm #define helper_clz_arm helper_clz_arm_arm +#define helper_clz_i32 helper_clz_i32_arm +#define helper_clz_i64 helper_clz_i64_arm +#define helper_ctz_i32 helper_ctz_i32_arm +#define helper_ctz_i64 helper_ctz_i64_arm #define helper_cpsr_read helper_cpsr_read_arm #define helper_cpsr_write helper_cpsr_write_arm #define helper_cpsr_write_eret helper_cpsr_write_eret_arm @@ -3007,6 +3011,14 @@ #define tcg_gen_bswap32_i64 tcg_gen_bswap32_i64_arm #define tcg_gen_bswap64_i64 tcg_gen_bswap64_i64_arm #define tcg_gen_callN tcg_gen_callN_arm +#define tcg_gen_clz_i32 tcg_gen_clz_i32_arm +#define tcg_gen_clz_i64 tcg_gen_clz_i64_arm +#define tcg_gen_clzi_i32 tcg_gen_clzi_i32_arm +#define tcg_gen_clzi_i64 tcg_gen_clzi_i64_arm +#define tcg_gen_ctz_i32 tcg_gen_ctz_i32_arm +#define tcg_gen_ctz_i64 tcg_gen_ctz_i64_arm +#define tcg_gen_ctzi_i32 tcg_gen_ctzi_i32_arm +#define tcg_gen_ctzi_i64 tcg_gen_ctzi_i64_arm #define tcg_gen_code tcg_gen_code_arm #define tcg_gen_concat_i32_i64 tcg_gen_concat_i32_i64_arm #define tcg_gen_deposit_i32 tcg_gen_deposit_i32_arm diff --git a/qemu/armeb.h b/qemu/armeb.h index 12d4b980..9dcde04a 100644 --- a/qemu/armeb.h +++ b/qemu/armeb.h @@ -1566,6 +1566,10 @@ #define helper_be_stw_mmu helper_be_stw_mmu_armeb #define helper_clear_pstate_ss helper_clear_pstate_ss_armeb #define helper_clz_arm helper_clz_arm_armeb +#define helper_clz_i32 helper_clz_i32_armeb +#define helper_clz_i64 helper_clz_i64_armeb +#define helper_ctz_i32 helper_ctz_i32_armeb +#define helper_ctz_i64 helper_ctz_i64_armeb #define helper_cpsr_read helper_cpsr_read_armeb #define helper_cpsr_write helper_cpsr_write_armeb #define helper_cpsr_write_eret helper_cpsr_write_eret_armeb @@ -3007,6 +3011,14 @@ #define tcg_gen_bswap32_i64 tcg_gen_bswap32_i64_armeb #define tcg_gen_bswap64_i64 tcg_gen_bswap64_i64_armeb #define tcg_gen_callN tcg_gen_callN_armeb +#define tcg_gen_clz_i32 tcg_gen_clz_i32_armeb +#define tcg_gen_clz_i64 tcg_gen_clz_i64_armeb +#define tcg_gen_clzi_i32 tcg_gen_clzi_i32_armeb +#define tcg_gen_clzi_i64 tcg_gen_clzi_i64_armeb +#define tcg_gen_ctz_i32 tcg_gen_ctz_i32_armeb +#define tcg_gen_ctz_i64 tcg_gen_ctz_i64_armeb +#define tcg_gen_ctzi_i32 tcg_gen_ctzi_i32_armeb +#define tcg_gen_ctzi_i64 tcg_gen_ctzi_i64_armeb #define tcg_gen_code tcg_gen_code_armeb #define tcg_gen_concat_i32_i64 tcg_gen_concat_i32_i64_armeb #define tcg_gen_deposit_i32 tcg_gen_deposit_i32_armeb diff --git a/qemu/header_gen.py b/qemu/header_gen.py index 77bbd45c..02890485 100644 --- a/qemu/header_gen.py +++ b/qemu/header_gen.py @@ -1572,6 +1572,10 @@ symbols = ( 'helper_be_stw_mmu', 'helper_clear_pstate_ss', 'helper_clz_arm', + 'helper_clz_i32', + 'helper_clz_i64', + 'helper_ctz_i32', + 'helper_ctz_i64', 'helper_cpsr_read', 'helper_cpsr_write', 'helper_cpsr_write_eret', @@ -3013,6 +3017,14 @@ symbols = ( 'tcg_gen_bswap32_i64', 'tcg_gen_bswap64_i64', 'tcg_gen_callN', + 'tcg_gen_clz_i32', + 'tcg_gen_clz_i64', + 'tcg_gen_clzi_i32', + 'tcg_gen_clzi_i64', + 'tcg_gen_ctz_i32', + 'tcg_gen_ctz_i64', + 'tcg_gen_ctzi_i32', + 'tcg_gen_ctzi_i64', 'tcg_gen_code', 'tcg_gen_concat_i32_i64', 'tcg_gen_deposit_i32', diff --git a/qemu/m68k.h b/qemu/m68k.h index 83032ea0..09e11be2 100644 --- a/qemu/m68k.h +++ b/qemu/m68k.h @@ -1566,6 +1566,10 @@ #define helper_be_stw_mmu helper_be_stw_mmu_m68k #define helper_clear_pstate_ss helper_clear_pstate_ss_m68k #define helper_clz_arm helper_clz_arm_m68k +#define helper_clz_i32 helper_clz_i32_m68k +#define helper_clz_i64 helper_clz_i64_m68k +#define helper_ctz_i32 helper_ctz_i32_m68k +#define helper_ctz_i64 helper_ctz_i64_m68k #define helper_cpsr_read helper_cpsr_read_m68k #define helper_cpsr_write helper_cpsr_write_m68k #define helper_cpsr_write_eret helper_cpsr_write_eret_m68k @@ -3007,6 +3011,14 @@ #define tcg_gen_bswap32_i64 tcg_gen_bswap32_i64_m68k #define tcg_gen_bswap64_i64 tcg_gen_bswap64_i64_m68k #define tcg_gen_callN tcg_gen_callN_m68k +#define tcg_gen_clz_i32 tcg_gen_clz_i32_m68k +#define tcg_gen_clz_i64 tcg_gen_clz_i64_m68k +#define tcg_gen_clzi_i32 tcg_gen_clzi_i32_m68k +#define tcg_gen_clzi_i64 tcg_gen_clzi_i64_m68k +#define tcg_gen_ctz_i32 tcg_gen_ctz_i32_m68k +#define tcg_gen_ctz_i64 tcg_gen_ctz_i64_m68k +#define tcg_gen_ctzi_i32 tcg_gen_ctzi_i32_m68k +#define tcg_gen_ctzi_i64 tcg_gen_ctzi_i64_m68k #define tcg_gen_code tcg_gen_code_m68k #define tcg_gen_concat_i32_i64 tcg_gen_concat_i32_i64_m68k #define tcg_gen_deposit_i32 tcg_gen_deposit_i32_m68k diff --git a/qemu/mips.h b/qemu/mips.h index 7d81c2de..e47bbb1d 100644 --- a/qemu/mips.h +++ b/qemu/mips.h @@ -1566,6 +1566,10 @@ #define helper_be_stw_mmu helper_be_stw_mmu_mips #define helper_clear_pstate_ss helper_clear_pstate_ss_mips #define helper_clz_arm helper_clz_arm_mips +#define helper_clz_i32 helper_clz_i32_mips +#define helper_clz_i64 helper_clz_i64_mips +#define helper_ctz_i32 helper_ctz_i32_mips +#define helper_ctz_i64 helper_ctz_i64_mips #define helper_cpsr_read helper_cpsr_read_mips #define helper_cpsr_write helper_cpsr_write_mips #define helper_cpsr_write_eret helper_cpsr_write_eret_mips @@ -3007,6 +3011,14 @@ #define tcg_gen_bswap32_i64 tcg_gen_bswap32_i64_mips #define tcg_gen_bswap64_i64 tcg_gen_bswap64_i64_mips #define tcg_gen_callN tcg_gen_callN_mips +#define tcg_gen_clz_i32 tcg_gen_clz_i32_mips +#define tcg_gen_clz_i64 tcg_gen_clz_i64_mips +#define tcg_gen_clzi_i32 tcg_gen_clzi_i32_mips +#define tcg_gen_clzi_i64 tcg_gen_clzi_i64_mips +#define tcg_gen_ctz_i32 tcg_gen_ctz_i32_mips +#define tcg_gen_ctz_i64 tcg_gen_ctz_i64_mips +#define tcg_gen_ctzi_i32 tcg_gen_ctzi_i32_mips +#define tcg_gen_ctzi_i64 tcg_gen_ctzi_i64_mips #define tcg_gen_code tcg_gen_code_mips #define tcg_gen_concat_i32_i64 tcg_gen_concat_i32_i64_mips #define tcg_gen_deposit_i32 tcg_gen_deposit_i32_mips diff --git a/qemu/mips64.h b/qemu/mips64.h index ecd20397..9632c027 100644 --- a/qemu/mips64.h +++ b/qemu/mips64.h @@ -1566,6 +1566,10 @@ #define helper_be_stw_mmu helper_be_stw_mmu_mips64 #define helper_clear_pstate_ss helper_clear_pstate_ss_mips64 #define helper_clz_arm helper_clz_arm_mips64 +#define helper_clz_i32 helper_clz_i32_mips64 +#define helper_clz_i64 helper_clz_i64_mips64 +#define helper_ctz_i32 helper_ctz_i32_mips64 +#define helper_ctz_i64 helper_ctz_i64_mips64 #define helper_cpsr_read helper_cpsr_read_mips64 #define helper_cpsr_write helper_cpsr_write_mips64 #define helper_cpsr_write_eret helper_cpsr_write_eret_mips64 @@ -3007,6 +3011,14 @@ #define tcg_gen_bswap32_i64 tcg_gen_bswap32_i64_mips64 #define tcg_gen_bswap64_i64 tcg_gen_bswap64_i64_mips64 #define tcg_gen_callN tcg_gen_callN_mips64 +#define tcg_gen_clz_i32 tcg_gen_clz_i32_mips64 +#define tcg_gen_clz_i64 tcg_gen_clz_i64_mips64 +#define tcg_gen_clzi_i32 tcg_gen_clzi_i32_mips64 +#define tcg_gen_clzi_i64 tcg_gen_clzi_i64_mips64 +#define tcg_gen_ctz_i32 tcg_gen_ctz_i32_mips64 +#define tcg_gen_ctz_i64 tcg_gen_ctz_i64_mips64 +#define tcg_gen_ctzi_i32 tcg_gen_ctzi_i32_mips64 +#define tcg_gen_ctzi_i64 tcg_gen_ctzi_i64_mips64 #define tcg_gen_code tcg_gen_code_mips64 #define tcg_gen_concat_i32_i64 tcg_gen_concat_i32_i64_mips64 #define tcg_gen_deposit_i32 tcg_gen_deposit_i32_mips64 diff --git a/qemu/mips64el.h b/qemu/mips64el.h index e985dba5..40ae05f9 100644 --- a/qemu/mips64el.h +++ b/qemu/mips64el.h @@ -1566,6 +1566,10 @@ #define helper_be_stw_mmu helper_be_stw_mmu_mips64el #define helper_clear_pstate_ss helper_clear_pstate_ss_mips64el #define helper_clz_arm helper_clz_arm_mips64el +#define helper_clz_i32 helper_clz_i32_mips64el +#define helper_clz_i64 helper_clz_i64_mips64el +#define helper_ctz_i32 helper_ctz_i32_mips64el +#define helper_ctz_i64 helper_ctz_i64_mips64el #define helper_cpsr_read helper_cpsr_read_mips64el #define helper_cpsr_write helper_cpsr_write_mips64el #define helper_cpsr_write_eret helper_cpsr_write_eret_mips64el @@ -3007,6 +3011,14 @@ #define tcg_gen_bswap32_i64 tcg_gen_bswap32_i64_mips64el #define tcg_gen_bswap64_i64 tcg_gen_bswap64_i64_mips64el #define tcg_gen_callN tcg_gen_callN_mips64el +#define tcg_gen_clz_i32 tcg_gen_clz_i32_mips64el +#define tcg_gen_clz_i64 tcg_gen_clz_i64_mips64el +#define tcg_gen_clzi_i32 tcg_gen_clzi_i32_mips64el +#define tcg_gen_clzi_i64 tcg_gen_clzi_i64_mips64el +#define tcg_gen_ctz_i32 tcg_gen_ctz_i32_mips64el +#define tcg_gen_ctz_i64 tcg_gen_ctz_i64_mips64el +#define tcg_gen_ctzi_i32 tcg_gen_ctzi_i32_mips64el +#define tcg_gen_ctzi_i64 tcg_gen_ctzi_i64_mips64el #define tcg_gen_code tcg_gen_code_mips64el #define tcg_gen_concat_i32_i64 tcg_gen_concat_i32_i64_mips64el #define tcg_gen_deposit_i32 tcg_gen_deposit_i32_mips64el diff --git a/qemu/mipsel.h b/qemu/mipsel.h index 923af6c9..d56d4d6f 100644 --- a/qemu/mipsel.h +++ b/qemu/mipsel.h @@ -1566,6 +1566,10 @@ #define helper_be_stw_mmu helper_be_stw_mmu_mipsel #define helper_clear_pstate_ss helper_clear_pstate_ss_mipsel #define helper_clz_arm helper_clz_arm_mipsel +#define helper_clz_i32 helper_clz_i32_mipsel +#define helper_clz_i64 helper_clz_i64_mipsel +#define helper_ctz_i32 helper_ctz_i32_mipsel +#define helper_ctz_i64 helper_ctz_i64_mipsel #define helper_cpsr_read helper_cpsr_read_mipsel #define helper_cpsr_write helper_cpsr_write_mipsel #define helper_cpsr_write_eret helper_cpsr_write_eret_mipsel @@ -3007,6 +3011,14 @@ #define tcg_gen_bswap32_i64 tcg_gen_bswap32_i64_mipsel #define tcg_gen_bswap64_i64 tcg_gen_bswap64_i64_mipsel #define tcg_gen_callN tcg_gen_callN_mipsel +#define tcg_gen_clz_i32 tcg_gen_clz_i32_mipsel +#define tcg_gen_clz_i64 tcg_gen_clz_i64_mipsel +#define tcg_gen_clzi_i32 tcg_gen_clzi_i32_mipsel +#define tcg_gen_clzi_i64 tcg_gen_clzi_i64_mipsel +#define tcg_gen_ctz_i32 tcg_gen_ctz_i32_mipsel +#define tcg_gen_ctz_i64 tcg_gen_ctz_i64_mipsel +#define tcg_gen_ctzi_i32 tcg_gen_ctzi_i32_mipsel +#define tcg_gen_ctzi_i64 tcg_gen_ctzi_i64_mipsel #define tcg_gen_code tcg_gen_code_mipsel #define tcg_gen_concat_i32_i64 tcg_gen_concat_i32_i64_mipsel #define tcg_gen_deposit_i32 tcg_gen_deposit_i32_mipsel diff --git a/qemu/powerpc.h b/qemu/powerpc.h index ca3f560c..53ceb5cf 100644 --- a/qemu/powerpc.h +++ b/qemu/powerpc.h @@ -1566,6 +1566,10 @@ #define helper_be_stw_mmu helper_be_stw_mmu_powerpc #define helper_clear_pstate_ss helper_clear_pstate_ss_powerpc #define helper_clz_arm helper_clz_arm_powerpc +#define helper_clz_i32 helper_clz_i32_powerpc +#define helper_clz_i64 helper_clz_i64_powerpc +#define helper_ctz_i32 helper_ctz_i32_powerpc +#define helper_ctz_i64 helper_ctz_i64_powerpc #define helper_cpsr_read helper_cpsr_read_powerpc #define helper_cpsr_write helper_cpsr_write_powerpc #define helper_cpsr_write_eret helper_cpsr_write_eret_powerpc @@ -3007,6 +3011,14 @@ #define tcg_gen_bswap32_i64 tcg_gen_bswap32_i64_powerpc #define tcg_gen_bswap64_i64 tcg_gen_bswap64_i64_powerpc #define tcg_gen_callN tcg_gen_callN_powerpc +#define tcg_gen_clz_i32 tcg_gen_clz_i32_powerpc +#define tcg_gen_clz_i64 tcg_gen_clz_i64_powerpc +#define tcg_gen_clzi_i32 tcg_gen_clzi_i32_powerpc +#define tcg_gen_clzi_i64 tcg_gen_clzi_i64_powerpc +#define tcg_gen_ctz_i32 tcg_gen_ctz_i32_powerpc +#define tcg_gen_ctz_i64 tcg_gen_ctz_i64_powerpc +#define tcg_gen_ctzi_i32 tcg_gen_ctzi_i32_powerpc +#define tcg_gen_ctzi_i64 tcg_gen_ctzi_i64_powerpc #define tcg_gen_code tcg_gen_code_powerpc #define tcg_gen_concat_i32_i64 tcg_gen_concat_i32_i64_powerpc #define tcg_gen_deposit_i32 tcg_gen_deposit_i32_powerpc diff --git a/qemu/sparc.h b/qemu/sparc.h index 8fcc76fb..d37f4560 100644 --- a/qemu/sparc.h +++ b/qemu/sparc.h @@ -1566,6 +1566,10 @@ #define helper_be_stw_mmu helper_be_stw_mmu_sparc #define helper_clear_pstate_ss helper_clear_pstate_ss_sparc #define helper_clz_arm helper_clz_arm_sparc +#define helper_clz_i32 helper_clz_i32_sparc +#define helper_clz_i64 helper_clz_i64_sparc +#define helper_ctz_i32 helper_ctz_i32_sparc +#define helper_ctz_i64 helper_ctz_i64_sparc #define helper_cpsr_read helper_cpsr_read_sparc #define helper_cpsr_write helper_cpsr_write_sparc #define helper_cpsr_write_eret helper_cpsr_write_eret_sparc @@ -3007,6 +3011,14 @@ #define tcg_gen_bswap32_i64 tcg_gen_bswap32_i64_sparc #define tcg_gen_bswap64_i64 tcg_gen_bswap64_i64_sparc #define tcg_gen_callN tcg_gen_callN_sparc +#define tcg_gen_clz_i32 tcg_gen_clz_i32_sparc +#define tcg_gen_clz_i64 tcg_gen_clz_i64_sparc +#define tcg_gen_clzi_i32 tcg_gen_clzi_i32_sparc +#define tcg_gen_clzi_i64 tcg_gen_clzi_i64_sparc +#define tcg_gen_ctz_i32 tcg_gen_ctz_i32_sparc +#define tcg_gen_ctz_i64 tcg_gen_ctz_i64_sparc +#define tcg_gen_ctzi_i32 tcg_gen_ctzi_i32_sparc +#define tcg_gen_ctzi_i64 tcg_gen_ctzi_i64_sparc #define tcg_gen_code tcg_gen_code_sparc #define tcg_gen_concat_i32_i64 tcg_gen_concat_i32_i64_sparc #define tcg_gen_deposit_i32 tcg_gen_deposit_i32_sparc diff --git a/qemu/sparc64.h b/qemu/sparc64.h index 615b4509..0951e6f1 100644 --- a/qemu/sparc64.h +++ b/qemu/sparc64.h @@ -1566,6 +1566,10 @@ #define helper_be_stw_mmu helper_be_stw_mmu_sparc64 #define helper_clear_pstate_ss helper_clear_pstate_ss_sparc64 #define helper_clz_arm helper_clz_arm_sparc64 +#define helper_clz_i32 helper_clz_i32_sparc64 +#define helper_clz_i64 helper_clz_i64_sparc64 +#define helper_ctz_i32 helper_ctz_i32_sparc64 +#define helper_ctz_i64 helper_ctz_i64_sparc64 #define helper_cpsr_read helper_cpsr_read_sparc64 #define helper_cpsr_write helper_cpsr_write_sparc64 #define helper_cpsr_write_eret helper_cpsr_write_eret_sparc64 @@ -3007,6 +3011,14 @@ #define tcg_gen_bswap32_i64 tcg_gen_bswap32_i64_sparc64 #define tcg_gen_bswap64_i64 tcg_gen_bswap64_i64_sparc64 #define tcg_gen_callN tcg_gen_callN_sparc64 +#define tcg_gen_clz_i32 tcg_gen_clz_i32_sparc64 +#define tcg_gen_clz_i64 tcg_gen_clz_i64_sparc64 +#define tcg_gen_clzi_i32 tcg_gen_clzi_i32_sparc64 +#define tcg_gen_clzi_i64 tcg_gen_clzi_i64_sparc64 +#define tcg_gen_ctz_i32 tcg_gen_ctz_i32_sparc64 +#define tcg_gen_ctz_i64 tcg_gen_ctz_i64_sparc64 +#define tcg_gen_ctzi_i32 tcg_gen_ctzi_i32_sparc64 +#define tcg_gen_ctzi_i64 tcg_gen_ctzi_i64_sparc64 #define tcg_gen_code tcg_gen_code_sparc64 #define tcg_gen_concat_i32_i64 tcg_gen_concat_i32_i64_sparc64 #define tcg_gen_deposit_i32 tcg_gen_deposit_i32_sparc64 diff --git a/qemu/tcg-runtime.c b/qemu/tcg-runtime.c index 1cfc6030..e424f861 100644 --- a/qemu/tcg-runtime.c +++ b/qemu/tcg-runtime.c @@ -102,6 +102,26 @@ int64_t HELPER(mulsh_i64)(int64_t arg1, int64_t arg2) return h; } +uint32_t HELPER(clz_i32)(uint32_t arg, uint32_t zero_val) +{ + return arg ? clz32(arg) : zero_val; +} + +uint32_t HELPER(ctz_i32)(uint32_t arg, uint32_t zero_val) +{ + return arg ? ctz32(arg) : zero_val; +} + +uint64_t HELPER(clz_i64)(uint64_t arg, uint64_t zero_val) +{ + return arg ? clz64(arg) : zero_val; +} + +uint64_t HELPER(ctz_i64)(uint64_t arg, uint64_t zero_val) +{ + return arg ? ctz64(arg) : zero_val; +} + void HELPER(exit_atomic)(CPUArchState *env) { cpu_loop_exit_atomic(ENV_GET_CPU(env), GETPC()); diff --git a/qemu/tcg/README b/qemu/tcg/README index b0dc630f..0d419b44 100644 --- a/qemu/tcg/README +++ b/qemu/tcg/README @@ -241,6 +241,14 @@ t0=~(t1|t2) t0=t1|~t2 +* clz_i32/i64 t0, t1, t2 + +t0 = t1 ? clz(t1) : t2 + +* ctz_i32/i64 t0, t1, t2 + +t0 = t1 ? ctz(t1) : t2 + ********* Shifts/Rotates * shl_i32/i64 t0, t1, t2 diff --git a/qemu/tcg/aarch64/tcg-target.h b/qemu/tcg/aarch64/tcg-target.h index 4a74bd8d..976f4931 100644 --- a/qemu/tcg/aarch64/tcg-target.h +++ b/qemu/tcg/aarch64/tcg-target.h @@ -62,6 +62,8 @@ typedef enum { #define TCG_TARGET_HAS_eqv_i32 1 #define TCG_TARGET_HAS_nand_i32 0 #define TCG_TARGET_HAS_nor_i32 0 +#define TCG_TARGET_HAS_clz_i32 0 +#define TCG_TARGET_HAS_ctz_i32 0 #define TCG_TARGET_HAS_deposit_i32 1 #define TCG_TARGET_HAS_extract_i32 1 #define TCG_TARGET_HAS_sextract_i32 1 @@ -94,6 +96,8 @@ typedef enum { #define TCG_TARGET_HAS_eqv_i64 1 #define TCG_TARGET_HAS_nand_i64 0 #define TCG_TARGET_HAS_nor_i64 0 +#define TCG_TARGET_HAS_clz_i64 0 +#define TCG_TARGET_HAS_ctz_i64 0 #define TCG_TARGET_HAS_deposit_i64 1 #define TCG_TARGET_HAS_extract_i64 1 #define TCG_TARGET_HAS_sextract_i64 1 diff --git a/qemu/tcg/arm/tcg-target.h b/qemu/tcg/arm/tcg-target.h index cad25144..4189ee8c 100644 --- a/qemu/tcg/arm/tcg-target.h +++ b/qemu/tcg/arm/tcg-target.h @@ -111,6 +111,8 @@ extern bool use_idiv_instructions_rt; #define TCG_TARGET_HAS_eqv_i32 0 #define TCG_TARGET_HAS_nand_i32 0 #define TCG_TARGET_HAS_nor_i32 0 +#define TCG_TARGET_HAS_clz_i32 0 +#define TCG_TARGET_HAS_ctz_i32 0 #define TCG_TARGET_HAS_deposit_i32 use_armv7_instructions #define TCG_TARGET_HAS_extract_i32 use_armv7_instructions #define TCG_TARGET_HAS_sextract_i32 use_armv7_instructions diff --git a/qemu/tcg/i386/tcg-target.h b/qemu/tcg/i386/tcg-target.h index 9f517b89..b8c77e86 100644 --- a/qemu/tcg/i386/tcg-target.h +++ b/qemu/tcg/i386/tcg-target.h @@ -93,6 +93,8 @@ extern bool have_bmi1; #define TCG_TARGET_HAS_eqv_i32 0 #define TCG_TARGET_HAS_nand_i32 0 #define TCG_TARGET_HAS_nor_i32 0 +#define TCG_TARGET_HAS_clz_i32 0 +#define TCG_TARGET_HAS_ctz_i32 0 #define TCG_TARGET_HAS_deposit_i32 1 #define TCG_TARGET_HAS_extract_i32 1 #define TCG_TARGET_HAS_sextract_i32 1 @@ -125,6 +127,8 @@ extern bool have_bmi1; #define TCG_TARGET_HAS_eqv_i64 0 #define TCG_TARGET_HAS_nand_i64 0 #define TCG_TARGET_HAS_nor_i64 0 +#define TCG_TARGET_HAS_clz_i64 0 +#define TCG_TARGET_HAS_ctz_i64 0 #define TCG_TARGET_HAS_deposit_i64 1 #define TCG_TARGET_HAS_extract_i64 1 #define TCG_TARGET_HAS_sextract_i64 0 diff --git a/qemu/tcg/mips/tcg-target.h b/qemu/tcg/mips/tcg-target.h index 92d203ac..06988cf2 100644 --- a/qemu/tcg/mips/tcg-target.h +++ b/qemu/tcg/mips/tcg-target.h @@ -121,6 +121,8 @@ extern bool use_mips32r2_instructions; #define TCG_TARGET_HAS_rem_i32 1 #define TCG_TARGET_HAS_not_i32 1 #define TCG_TARGET_HAS_nor_i32 1 +#define TCG_TARGET_HAS_clz_i32 0 +#define TCG_TARGET_HAS_ctz_i32 0 #define TCG_TARGET_HAS_andc_i32 0 #define TCG_TARGET_HAS_orc_i32 0 #define TCG_TARGET_HAS_eqv_i32 0 diff --git a/qemu/tcg/optimize.c b/qemu/tcg/optimize.c index ba5d4499..9bebff30 100644 --- a/qemu/tcg/optimize.c +++ b/qemu/tcg/optimize.c @@ -300,6 +300,18 @@ static TCGArg do_constant_folding_2(TCGOpcode op, TCGArg x, TCGArg y) CASE_OP_32_64(nor): return ~(x | y); + case INDEX_op_clz_i32: + return (uint32_t)x ? clz32(x) : y; + + case INDEX_op_clz_i64: + return x ? clz64(x) : y; + + case INDEX_op_ctz_i32: + return (uint32_t)x ? ctz32(x) : y; + + case INDEX_op_ctz_i64: + return x ? ctz64(x) : y; + CASE_OP_32_64(ext8s): return (int8_t)x; @@ -907,6 +919,16 @@ void tcg_optimize(TCGContext *s) mask = temps[args[1]].mask | temps[args[2]].mask; break; + case INDEX_op_clz_i32: + case INDEX_op_ctz_i32: + mask = temps[args[2]].mask | 31; + break; + + case INDEX_op_clz_i64: + case INDEX_op_ctz_i64: + mask = temps[args[2]].mask | 63; + break; + CASE_OP_32_64(setcond): case INDEX_op_setcond2_i32: mask = 1; @@ -1063,6 +1085,20 @@ void tcg_optimize(TCGContext *s) } goto do_default; + CASE_OP_32_64(clz): + CASE_OP_32_64(ctz): + if (temp_is_const(s, args[1])) { + TCGArg v = temps[args[1]].val; + if (v != 0) { + tmp = do_constant_folding(s, opc, v, 0); + tcg_opt_gen_movi(s, op, args, args[0], tmp); + } else { + tcg_opt_gen_mov(s, op, args, args[0], args[2]); + } + break; + } + goto do_default; + CASE_OP_32_64(deposit): if (temp_is_const(s, args[1]) && temp_is_const(s, args[2])) { tmp = (TCGArg)deposit64(temps[args[1]].val, args[3], args[4], diff --git a/qemu/tcg/ppc/tcg-target.h b/qemu/tcg/ppc/tcg-target.h index b42c57a7..698a5990 100644 --- a/qemu/tcg/ppc/tcg-target.h +++ b/qemu/tcg/ppc/tcg-target.h @@ -68,6 +68,8 @@ typedef enum { #define TCG_TARGET_HAS_eqv_i32 1 #define TCG_TARGET_HAS_nand_i32 1 #define TCG_TARGET_HAS_nor_i32 1 +#define TCG_TARGET_HAS_clz_i32 0 +#define TCG_TARGET_HAS_ctz_i32 0 #define TCG_TARGET_HAS_deposit_i32 1 #define TCG_TARGET_HAS_extract_i32 1 #define TCG_TARGET_HAS_sextract_i32 0 @@ -101,6 +103,8 @@ typedef enum { #define TCG_TARGET_HAS_eqv_i64 1 #define TCG_TARGET_HAS_nand_i64 1 #define TCG_TARGET_HAS_nor_i64 1 +#define TCG_TARGET_HAS_clz_i64 0 +#define TCG_TARGET_HAS_ctz_i64 0 #define TCG_TARGET_HAS_deposit_i64 1 #define TCG_TARGET_HAS_extract_i64 1 #define TCG_TARGET_HAS_sextract_i64 0 diff --git a/qemu/tcg/s390/tcg-target.h b/qemu/tcg/s390/tcg-target.h index e9ac12e5..3ac2dc98 100644 --- a/qemu/tcg/s390/tcg-target.h +++ b/qemu/tcg/s390/tcg-target.h @@ -77,6 +77,8 @@ extern uint64_t s390_facilities; #define TCG_TARGET_HAS_eqv_i32 0 #define TCG_TARGET_HAS_nand_i32 0 #define TCG_TARGET_HAS_nor_i32 0 +#define TCG_TARGET_HAS_clz_i32 0 +#define TCG_TARGET_HAS_ctz_i32 0 #define TCG_TARGET_HAS_deposit_i32 (s390_facilities & FACILITY_GEN_INST_EXT) #define TCG_TARGET_HAS_extract_i32 (s390_facilities & FACILITY_GEN_INST_EXT) #define TCG_TARGET_HAS_sextract_i32 0 @@ -108,6 +110,8 @@ extern uint64_t s390_facilities; #define TCG_TARGET_HAS_eqv_i64 0 #define TCG_TARGET_HAS_nand_i64 0 #define TCG_TARGET_HAS_nor_i64 0 +#define TCG_TARGET_HAS_clz_i64 0 +#define TCG_TARGET_HAS_ctz_i64 0 #define TCG_TARGET_HAS_deposit_i64 (s390_facilities & FACILITY_GEN_INST_EXT) #define TCG_TARGET_HAS_extract_i64 (s390_facilities & FACILITY_GEN_INST_EXT) #define TCG_TARGET_HAS_sextract_i64 0 diff --git a/qemu/tcg/sparc/tcg-target.h b/qemu/tcg/sparc/tcg-target.h index 880eb466..5afd4440 100644 --- a/qemu/tcg/sparc/tcg-target.h +++ b/qemu/tcg/sparc/tcg-target.h @@ -110,6 +110,8 @@ extern bool use_vis3_instructions; #define TCG_TARGET_HAS_eqv_i32 0 #define TCG_TARGET_HAS_nand_i32 0 #define TCG_TARGET_HAS_nor_i32 0 +#define TCG_TARGET_HAS_clz_i32 0 +#define TCG_TARGET_HAS_ctz_i32 0 #define TCG_TARGET_HAS_deposit_i32 0 #define TCG_TARGET_HAS_extract_i32 0 #define TCG_TARGET_HAS_sextract_i32 0 @@ -142,6 +144,8 @@ extern bool use_vis3_instructions; #define TCG_TARGET_HAS_eqv_i64 0 #define TCG_TARGET_HAS_nand_i64 0 #define TCG_TARGET_HAS_nor_i64 0 +#define TCG_TARGET_HAS_clz_i64 0 +#define TCG_TARGET_HAS_ctz_i64 0 #define TCG_TARGET_HAS_deposit_i64 0 #define TCG_TARGET_HAS_extract_i64 0 #define TCG_TARGET_HAS_sextract_i64 0 diff --git a/qemu/tcg/tcg-op.c b/qemu/tcg/tcg-op.c index f8b6bcbe..82059b74 100644 --- a/qemu/tcg/tcg-op.c +++ b/qemu/tcg/tcg-op.c @@ -456,6 +456,85 @@ void tcg_gen_orc_i32(TCGContext *s, TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) } } +void tcg_gen_clz_i32(TCGContext *s, TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) +{ + if (TCG_TARGET_HAS_clz_i32) { + tcg_gen_op3_i32(s, INDEX_op_clz_i32, ret, arg1, arg2); + } else if (TCG_TARGET_HAS_clz_i64) { + TCGv_i64 t1 = tcg_temp_new_i64(s); + TCGv_i64 t2 = tcg_temp_new_i64(s); + tcg_gen_extu_i32_i64(s, t1, arg1); + tcg_gen_extu_i32_i64(s, t2, arg2); + tcg_gen_addi_i64(s, t2, t2, 32); + tcg_gen_clz_i64(s, t1, t1, t2); + tcg_gen_extrl_i64_i32(s, ret, t1); + tcg_temp_free_i64(s, t1); + tcg_temp_free_i64(s, t2); + tcg_gen_subi_i32(s, ret, ret, 32); + } else { + gen_helper_clz_i32(s, ret, arg1, arg2); + } +} + +void tcg_gen_clzi_i32(TCGContext *s, TCGv_i32 ret, TCGv_i32 arg1, uint32_t arg2) +{ + TCGv_i32 t = tcg_const_i32(s, arg2); + tcg_gen_clz_i32(s, ret, arg1, t); + tcg_temp_free_i32(s, t); +} + +void tcg_gen_ctz_i32(TCGContext *s, TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) +{ + if (TCG_TARGET_HAS_ctz_i32) { + tcg_gen_op3_i32(s, INDEX_op_ctz_i32, ret, arg1, arg2); + } else if (TCG_TARGET_HAS_ctz_i64) { + TCGv_i64 t1 = tcg_temp_new_i64(s); + TCGv_i64 t2 = tcg_temp_new_i64(s); + tcg_gen_extu_i32_i64(s, t1, arg1); + tcg_gen_extu_i32_i64(s, t2, arg2); + tcg_gen_ctz_i64(s, t1, t1, t2); + tcg_gen_extrl_i64_i32(s, ret, t1); + tcg_temp_free_i64(s, t1); + tcg_temp_free_i64(s, t2); + } else if (TCG_TARGET_HAS_clz_i32) { + TCGv_i32 t1 = tcg_temp_new_i32(s); + TCGv_i32 t2 = tcg_temp_new_i32(s); + tcg_gen_neg_i32(s, t1, arg1); + tcg_gen_xori_i32(s, t2, arg2, 31); + tcg_gen_and_i32(s, t1, t1, arg1); + tcg_gen_clz_i32(s, ret, t1, t2); + tcg_temp_free_i32(s, t1); + tcg_temp_free_i32(s, t2); + tcg_gen_xori_i32(s, ret, ret, 31); + } else if (TCG_TARGET_HAS_clz_i64) { + TCGv_i32 t1 = tcg_temp_new_i32(s); + TCGv_i32 t2 = tcg_temp_new_i32(s); + TCGv_i64 x1 = tcg_temp_new_i64(s); + TCGv_i64 x2 = tcg_temp_new_i64(s); + tcg_gen_neg_i32(s, t1, arg1); + tcg_gen_xori_i32(s, t2, arg2, 63); + tcg_gen_and_i32(s, t1, t1, arg1); + tcg_gen_extu_i32_i64(s, x1, t1); + tcg_gen_extu_i32_i64(s, x2, t2); + tcg_temp_free_i32(s, t1); + tcg_temp_free_i32(s, t2); + tcg_gen_clz_i64(s, x1, x1, x2); + tcg_gen_extrl_i64_i32(s, ret, x1); + tcg_temp_free_i64(s, x1); + tcg_temp_free_i64(s, x2); + tcg_gen_xori_i32(s, ret, ret, 63); + } else { + gen_helper_ctz_i32(s, ret, arg1, arg2); + } +} + +void tcg_gen_ctzi_i32(TCGContext *s, TCGv_i32 ret, TCGv_i32 arg1, uint32_t arg2) +{ + TCGv_i32 t = tcg_const_i32(s, arg2); + tcg_gen_ctz_i32(s, ret, arg1, t); + tcg_temp_free_i32(s, t); +} + void tcg_gen_rotl_i32(TCGContext *s, TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) { if (TCG_TARGET_HAS_rot_i32) { @@ -1709,6 +1788,70 @@ void tcg_gen_orc_i64(TCGContext *s, TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) } } +void tcg_gen_clz_i64(TCGContext *s, TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) +{ + if (TCG_TARGET_HAS_clz_i64) { + tcg_gen_op3_i64(s, INDEX_op_clz_i64, ret, arg1, arg2); + } else { + gen_helper_clz_i64(s, ret, arg1, arg2); + } +} + +void tcg_gen_clzi_i64(TCGContext *s, TCGv_i64 ret, TCGv_i64 arg1, uint64_t arg2) +{ + if (TCG_TARGET_REG_BITS == 32 + && TCG_TARGET_HAS_clz_i32 + && arg2 <= 0xffffffffu) { + TCGv_i32 t = tcg_const_i32(s, (uint32_t)arg2 - 32); + tcg_gen_clz_i32(s, t, TCGV_LOW(arg1), t); + tcg_gen_addi_i32(s, t, t, 32); + tcg_gen_clz_i32(s, TCGV_LOW(ret), TCGV_HIGH(arg1), t); + tcg_gen_movi_i32(s, TCGV_HIGH(ret), 0); + tcg_temp_free_i32(s, t); + } else { + TCGv_i64 t = tcg_const_i64(s, arg2); + tcg_gen_clz_i64(s, ret, arg1, t); + tcg_temp_free_i64(s, t); + } +} + +void tcg_gen_ctz_i64(TCGContext *s, TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) +{ + if (TCG_TARGET_HAS_ctz_i64) { + tcg_gen_op3_i64(s, INDEX_op_ctz_i64, ret, arg1, arg2); + } else if (TCG_TARGET_HAS_clz_i64) { + TCGv_i64 t1 = tcg_temp_new_i64(s); + TCGv_i64 t2 = tcg_temp_new_i64(s); + tcg_gen_neg_i64(s, t1, arg1); + tcg_gen_xori_i64(s, t2, arg2, 63); + tcg_gen_and_i64(s, t1, t1, arg1); + tcg_gen_clz_i64(s, ret, t1, t2); + tcg_temp_free_i64(s, t1); + tcg_temp_free_i64(s, t2); + tcg_gen_xori_i64(s, ret, ret, 63); + } else { + gen_helper_ctz_i64(s, ret, arg1, arg2); + } +} + +void tcg_gen_ctzi_i64(TCGContext *s, TCGv_i64 ret, TCGv_i64 arg1, uint64_t arg2) +{ + if (TCG_TARGET_REG_BITS == 32 + && TCG_TARGET_HAS_ctz_i32 + && arg2 <= 0xffffffffu) { + TCGv_i32 t32 = tcg_const_i32(s, (uint32_t)arg2 - 32); + tcg_gen_ctz_i32(s, t32, TCGV_HIGH(arg1), t32); + tcg_gen_addi_i32(s, t32, t32, 32); + tcg_gen_ctz_i32(s, TCGV_LOW(ret), TCGV_LOW(arg1), t32); + tcg_gen_movi_i32(s, TCGV_HIGH(ret), 0); + tcg_temp_free_i32(s, t32); + } else { + TCGv_i64 t64 = tcg_const_i64(s, arg2); + tcg_gen_ctz_i64(s, ret, arg1, t64); + tcg_temp_free_i64(s, t64); + } +} + void tcg_gen_rotl_i64(TCGContext *s, TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) { if (TCG_TARGET_HAS_rot_i64) { diff --git a/qemu/tcg/tcg-op.h b/qemu/tcg/tcg-op.h index 264e0912..1d9a0ab8 100644 --- a/qemu/tcg/tcg-op.h +++ b/qemu/tcg/tcg-op.h @@ -294,6 +294,10 @@ void tcg_gen_eqv_i32(TCGContext *s, TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2); void tcg_gen_nand_i32(TCGContext *s, TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2); void tcg_gen_nor_i32(TCGContext *s, TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2); void tcg_gen_orc_i32(TCGContext *s, TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2); +void tcg_gen_clz_i32(TCGContext *s, TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2); +void tcg_gen_ctz_i32(TCGContext *s, TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2); +void tcg_gen_clzi_i32(TCGContext *s, TCGv_i32 ret, TCGv_i32 arg1, uint32_t arg2); +void tcg_gen_ctzi_i32(TCGContext *s, TCGv_i32 ret, TCGv_i32 arg1, uint32_t arg2); void tcg_gen_rotl_i32(TCGContext *s, TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2); void tcg_gen_rotli_i32(TCGContext *s, TCGv_i32 ret, TCGv_i32 arg1, unsigned arg2); void tcg_gen_rotr_i32(TCGContext *s, TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2); @@ -469,6 +473,10 @@ void tcg_gen_eqv_i64(TCGContext *s, TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2); void tcg_gen_nand_i64(TCGContext *s, TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2); void tcg_gen_nor_i64(TCGContext *s, TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2); void tcg_gen_orc_i64(TCGContext *s, TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2); +void tcg_gen_clz_i64(TCGContext *s, TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2); +void tcg_gen_ctz_i64(TCGContext *s, TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2); +void tcg_gen_clzi_i64(TCGContext *s, TCGv_i64 ret, TCGv_i64 arg1, uint64_t arg2); +void tcg_gen_ctzi_i64(TCGContext *s, TCGv_i64 ret, TCGv_i64 arg1, uint64_t arg2); void tcg_gen_rotl_i64(TCGContext *s, TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2); void tcg_gen_rotli_i64(TCGContext *s, TCGv_i64 ret, TCGv_i64 arg1, unsigned arg2); void tcg_gen_rotr_i64(TCGContext *s, TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2); @@ -960,6 +968,10 @@ void tcg_gen_atomic_xor_fetch_i64(TCGContext *, TCGv_i64, TCGv, TCGv_i64, TCGArg #define tcg_gen_nand_tl tcg_gen_nand_i64 #define tcg_gen_nor_tl tcg_gen_nor_i64 #define tcg_gen_orc_tl tcg_gen_orc_i64 +#define tcg_gen_clz_tl tcg_gen_clz_i64 +#define tcg_gen_ctz_tl tcg_gen_ctz_i64 +#define tcg_gen_clzi_tl tcg_gen_clzi_i64 +#define tcg_gen_ctzi_tl tcg_gen_ctzi_i64 #define tcg_gen_rotl_tl tcg_gen_rotl_i64 #define tcg_gen_rotli_tl tcg_gen_rotli_i64 #define tcg_gen_rotr_tl tcg_gen_rotr_i64 @@ -1051,6 +1063,10 @@ void tcg_gen_atomic_xor_fetch_i64(TCGContext *, TCGv_i64, TCGv, TCGv_i64, TCGArg #define tcg_gen_nand_tl tcg_gen_nand_i32 #define tcg_gen_nor_tl tcg_gen_nor_i32 #define tcg_gen_orc_tl tcg_gen_orc_i32 +#define tcg_gen_clz_tl tcg_gen_clz_i32 +#define tcg_gen_ctz_tl tcg_gen_ctz_i32 +#define tcg_gen_clzi_tl tcg_gen_clzi_i32 +#define tcg_gen_ctzi_tl tcg_gen_ctzi_i32 #define tcg_gen_rotl_tl tcg_gen_rotl_i32 #define tcg_gen_rotli_tl tcg_gen_rotli_i32 #define tcg_gen_rotr_tl tcg_gen_rotr_i32 diff --git a/qemu/tcg/tcg-opc.h b/qemu/tcg/tcg-opc.h index 7f5b9dbf..a515317c 100644 --- a/qemu/tcg/tcg-opc.h +++ b/qemu/tcg/tcg-opc.h @@ -109,6 +109,8 @@ DEF(orc_i32, 1, 2, 0, IMPL(TCG_TARGET_HAS_orc_i32)) DEF(eqv_i32, 1, 2, 0, IMPL(TCG_TARGET_HAS_eqv_i32)) DEF(nand_i32, 1, 2, 0, IMPL(TCG_TARGET_HAS_nand_i32)) DEF(nor_i32, 1, 2, 0, IMPL(TCG_TARGET_HAS_nor_i32)) +DEF(clz_i32, 1, 2, 0, IMPL(TCG_TARGET_HAS_clz_i32)) +DEF(ctz_i32, 1, 2, 0, IMPL(TCG_TARGET_HAS_ctz_i32)) DEF(mov_i64, 1, 1, 0, TCG_OPF_64BIT | TCG_OPF_NOT_PRESENT) DEF(movi_i64, 1, 0, 1, TCG_OPF_64BIT | TCG_OPF_NOT_PRESENT) @@ -177,6 +179,8 @@ DEF(orc_i64, 1, 2, 0, IMPL64 | IMPL(TCG_TARGET_HAS_orc_i64)) DEF(eqv_i64, 1, 2, 0, IMPL64 | IMPL(TCG_TARGET_HAS_eqv_i64)) DEF(nand_i64, 1, 2, 0, IMPL64 | IMPL(TCG_TARGET_HAS_nand_i64)) DEF(nor_i64, 1, 2, 0, IMPL64 | IMPL(TCG_TARGET_HAS_nor_i64)) +DEF(clz_i64, 1, 2, 0, IMPL64 | IMPL(TCG_TARGET_HAS_clz_i64)) +DEF(ctz_i64, 1, 2, 0, IMPL64 | IMPL(TCG_TARGET_HAS_ctz_i64)) DEF(add2_i64, 2, 4, 0, IMPL64 | IMPL(TCG_TARGET_HAS_add2_i64)) DEF(sub2_i64, 2, 4, 0, IMPL64 | IMPL(TCG_TARGET_HAS_sub2_i64)) diff --git a/qemu/tcg/tcg-runtime.h b/qemu/tcg/tcg-runtime.h index 62f178df..494496f5 100644 --- a/qemu/tcg/tcg-runtime.h +++ b/qemu/tcg/tcg-runtime.h @@ -15,6 +15,11 @@ DEF_HELPER_FLAGS_2(sar_i64, TCG_CALL_NO_RWG_SE, s64, s64, s64) DEF_HELPER_FLAGS_2(mulsh_i64, TCG_CALL_NO_RWG_SE, s64, s64, s64) DEF_HELPER_FLAGS_2(muluh_i64, TCG_CALL_NO_RWG_SE, i64, i64, i64) +DEF_HELPER_FLAGS_2(clz_i32, TCG_CALL_NO_RWG_SE, i32, i32, i32) +DEF_HELPER_FLAGS_2(ctz_i32, TCG_CALL_NO_RWG_SE, i32, i32, i32) +DEF_HELPER_FLAGS_2(clz_i64, TCG_CALL_NO_RWG_SE, i64, i64, i64) +DEF_HELPER_FLAGS_2(ctz_i64, TCG_CALL_NO_RWG_SE, i64, i64, i64) + DEF_HELPER_FLAGS_1(exit_atomic, TCG_CALL_NO_WG, noreturn, env) #ifdef CONFIG_SOFTMMU diff --git a/qemu/tcg/tcg.h b/qemu/tcg/tcg.h index 828f0eb3..8d95ef9f 100644 --- a/qemu/tcg/tcg.h +++ b/qemu/tcg/tcg.h @@ -114,6 +114,8 @@ typedef uint64_t TCGRegSet; #define TCG_TARGET_HAS_eqv_i64 0 #define TCG_TARGET_HAS_nand_i64 0 #define TCG_TARGET_HAS_nor_i64 0 +#define TCG_TARGET_HAS_clz_i64 0 +#define TCG_TARGET_HAS_ctz_i64 0 #define TCG_TARGET_HAS_deposit_i64 0 #define TCG_TARGET_HAS_extract_i64 0 #define TCG_TARGET_HAS_sextract_i64 0 @@ -1012,7 +1014,7 @@ static inline bool tcg_op_buf_full(TCGContext *tcg_ctx) } // UNICORN: Added -#define TCG_OP_DEFS_TABLE_SIZE 129 +#define TCG_OP_DEFS_TABLE_SIZE 133 extern const TCGOpDef tcg_op_defs_org[TCG_OP_DEFS_TABLE_SIZE]; typedef struct TCGTargetOpDef { diff --git a/qemu/x86_64.h b/qemu/x86_64.h index 090865ac..919e4bd3 100644 --- a/qemu/x86_64.h +++ b/qemu/x86_64.h @@ -1566,6 +1566,10 @@ #define helper_be_stw_mmu helper_be_stw_mmu_x86_64 #define helper_clear_pstate_ss helper_clear_pstate_ss_x86_64 #define helper_clz_arm helper_clz_arm_x86_64 +#define helper_clz_i32 helper_clz_i32_x86_64 +#define helper_clz_i64 helper_clz_i64_x86_64 +#define helper_ctz_i32 helper_ctz_i32_x86_64 +#define helper_ctz_i64 helper_ctz_i64_x86_64 #define helper_cpsr_read helper_cpsr_read_x86_64 #define helper_cpsr_write helper_cpsr_write_x86_64 #define helper_cpsr_write_eret helper_cpsr_write_eret_x86_64 @@ -3007,6 +3011,14 @@ #define tcg_gen_bswap32_i64 tcg_gen_bswap32_i64_x86_64 #define tcg_gen_bswap64_i64 tcg_gen_bswap64_i64_x86_64 #define tcg_gen_callN tcg_gen_callN_x86_64 +#define tcg_gen_clz_i32 tcg_gen_clz_i32_x86_64 +#define tcg_gen_clz_i64 tcg_gen_clz_i64_x86_64 +#define tcg_gen_clzi_i32 tcg_gen_clzi_i32_x86_64 +#define tcg_gen_clzi_i64 tcg_gen_clzi_i64_x86_64 +#define tcg_gen_ctz_i32 tcg_gen_ctz_i32_x86_64 +#define tcg_gen_ctz_i64 tcg_gen_ctz_i64_x86_64 +#define tcg_gen_ctzi_i32 tcg_gen_ctzi_i32_x86_64 +#define tcg_gen_ctzi_i64 tcg_gen_ctzi_i64_x86_64 #define tcg_gen_code tcg_gen_code_x86_64 #define tcg_gen_concat_i32_i64 tcg_gen_concat_i32_i64_x86_64 #define tcg_gen_deposit_i32 tcg_gen_deposit_i32_x86_64