From 2ea6dfbd63c8c3105cfc451872322e2ea0bae589 Mon Sep 17 00:00:00 2001 From: Richard Henderson Date: Fri, 24 May 2019 18:21:10 -0400 Subject: [PATCH] tcg: Add support for vector compare select Perform a per-element conditional move. This combination operation is easier to implement on some host vector units than plain cmp+bitsel. Omit the usual gvec interface, as this is intended to be used by target-specific gvec expansion call-backs. Backports commit f75da2988eb2457fa23d006d573220c5c680ec4e from qemu --- qemu/aarch64.h | 1 + qemu/aarch64eb.h | 1 + qemu/arm.h | 1 + qemu/armeb.h | 1 + qemu/header_gen.py | 1 + qemu/m68k.h | 1 + qemu/mips.h | 1 + qemu/mips64.h | 1 + qemu/mips64el.h | 1 + qemu/mipsel.h | 1 + qemu/powerpc.h | 1 + qemu/riscv32.h | 1 + qemu/riscv64.h | 1 + qemu/sparc.h | 1 + qemu/sparc64.h | 1 + qemu/tcg/README | 7 +++++ qemu/tcg/aarch64/tcg-target.h | 1 + qemu/tcg/i386/tcg-target.h | 1 + qemu/tcg/tcg-op-vec.c | 59 +++++++++++++++++++++++++++++++++++ qemu/tcg/tcg-op.h | 2 ++ qemu/tcg/tcg-opc.h | 1 + qemu/tcg/tcg.c | 3 ++ qemu/tcg/tcg.h | 3 +- qemu/x86_64.h | 1 + 24 files changed, 92 insertions(+), 1 deletion(-) diff --git a/qemu/aarch64.h b/qemu/aarch64.h index eb61e821..09bb21b2 100644 --- a/qemu/aarch64.h +++ b/qemu/aarch64.h @@ -2805,6 +2805,7 @@ #define tcg_gen_clzi_i32 tcg_gen_clzi_i32_aarch64 #define tcg_gen_clzi_i64 tcg_gen_clzi_i64_aarch64 #define tcg_gen_cmp_vec tcg_gen_cmp_vec_aarch64 +#define tcg_gen_cmpsel_vec tcg_gen_cmpsel_vec_aarch64 #define tcg_gen_ctpop_i32 tcg_gen_ctpop_i32_aarch64 #define tcg_gen_ctpop_i64 tcg_gen_ctpop_i64_aarch64 #define tcg_gen_ctz_i32 tcg_gen_ctz_i32_aarch64 diff --git a/qemu/aarch64eb.h b/qemu/aarch64eb.h index 33159eee..089728a2 100644 --- a/qemu/aarch64eb.h +++ b/qemu/aarch64eb.h @@ -2805,6 +2805,7 @@ #define tcg_gen_clzi_i32 tcg_gen_clzi_i32_aarch64eb #define tcg_gen_clzi_i64 tcg_gen_clzi_i64_aarch64eb #define tcg_gen_cmp_vec tcg_gen_cmp_vec_aarch64eb +#define tcg_gen_cmpsel_vec tcg_gen_cmpsel_vec_aarch64eb #define tcg_gen_ctpop_i32 tcg_gen_ctpop_i32_aarch64eb #define tcg_gen_ctpop_i64 tcg_gen_ctpop_i64_aarch64eb #define tcg_gen_ctz_i32 tcg_gen_ctz_i32_aarch64eb diff --git a/qemu/arm.h b/qemu/arm.h index 5011e657..04d19e66 100644 --- a/qemu/arm.h +++ b/qemu/arm.h @@ -2805,6 +2805,7 @@ #define tcg_gen_clzi_i32 tcg_gen_clzi_i32_arm #define tcg_gen_clzi_i64 tcg_gen_clzi_i64_arm #define tcg_gen_cmp_vec tcg_gen_cmp_vec_arm +#define tcg_gen_cmpsel_vec tcg_gen_cmpsel_vec_arm #define tcg_gen_ctpop_i32 tcg_gen_ctpop_i32_arm #define tcg_gen_ctpop_i64 tcg_gen_ctpop_i64_arm #define tcg_gen_ctz_i32 tcg_gen_ctz_i32_arm diff --git a/qemu/armeb.h b/qemu/armeb.h index 99146012..95f4ef9b 100644 --- a/qemu/armeb.h +++ b/qemu/armeb.h @@ -2805,6 +2805,7 @@ #define tcg_gen_clzi_i32 tcg_gen_clzi_i32_armeb #define tcg_gen_clzi_i64 tcg_gen_clzi_i64_armeb #define tcg_gen_cmp_vec tcg_gen_cmp_vec_armeb +#define tcg_gen_cmpsel_vec tcg_gen_cmpsel_vec_armeb #define tcg_gen_ctpop_i32 tcg_gen_ctpop_i32_armeb #define tcg_gen_ctpop_i64 tcg_gen_ctpop_i64_armeb #define tcg_gen_ctz_i32 tcg_gen_ctz_i32_armeb diff --git a/qemu/header_gen.py b/qemu/header_gen.py index 81a96345..1bb7bc00 100644 --- a/qemu/header_gen.py +++ b/qemu/header_gen.py @@ -2811,6 +2811,7 @@ symbols = ( 'tcg_gen_clzi_i32', 'tcg_gen_clzi_i64', 'tcg_gen_cmp_vec', + 'tcg_gen_cmpsel_vec', 'tcg_gen_ctpop_i32', 'tcg_gen_ctpop_i64', 'tcg_gen_ctz_i32', diff --git a/qemu/m68k.h b/qemu/m68k.h index 3c2f5a96..8b110810 100644 --- a/qemu/m68k.h +++ b/qemu/m68k.h @@ -2805,6 +2805,7 @@ #define tcg_gen_clzi_i32 tcg_gen_clzi_i32_m68k #define tcg_gen_clzi_i64 tcg_gen_clzi_i64_m68k #define tcg_gen_cmp_vec tcg_gen_cmp_vec_m68k +#define tcg_gen_cmpsel_vec tcg_gen_cmpsel_vec_m68k #define tcg_gen_ctpop_i32 tcg_gen_ctpop_i32_m68k #define tcg_gen_ctpop_i64 tcg_gen_ctpop_i64_m68k #define tcg_gen_ctz_i32 tcg_gen_ctz_i32_m68k diff --git a/qemu/mips.h b/qemu/mips.h index 1631cfd7..81315fc4 100644 --- a/qemu/mips.h +++ b/qemu/mips.h @@ -2805,6 +2805,7 @@ #define tcg_gen_clzi_i32 tcg_gen_clzi_i32_mips #define tcg_gen_clzi_i64 tcg_gen_clzi_i64_mips #define tcg_gen_cmp_vec tcg_gen_cmp_vec_mips +#define tcg_gen_cmpsel_vec tcg_gen_cmpsel_vec_mips #define tcg_gen_ctpop_i32 tcg_gen_ctpop_i32_mips #define tcg_gen_ctpop_i64 tcg_gen_ctpop_i64_mips #define tcg_gen_ctz_i32 tcg_gen_ctz_i32_mips diff --git a/qemu/mips64.h b/qemu/mips64.h index 22d4c9f3..df955412 100644 --- a/qemu/mips64.h +++ b/qemu/mips64.h @@ -2805,6 +2805,7 @@ #define tcg_gen_clzi_i32 tcg_gen_clzi_i32_mips64 #define tcg_gen_clzi_i64 tcg_gen_clzi_i64_mips64 #define tcg_gen_cmp_vec tcg_gen_cmp_vec_mips64 +#define tcg_gen_cmpsel_vec tcg_gen_cmpsel_vec_mips64 #define tcg_gen_ctpop_i32 tcg_gen_ctpop_i32_mips64 #define tcg_gen_ctpop_i64 tcg_gen_ctpop_i64_mips64 #define tcg_gen_ctz_i32 tcg_gen_ctz_i32_mips64 diff --git a/qemu/mips64el.h b/qemu/mips64el.h index 8bb695b2..268d142b 100644 --- a/qemu/mips64el.h +++ b/qemu/mips64el.h @@ -2805,6 +2805,7 @@ #define tcg_gen_clzi_i32 tcg_gen_clzi_i32_mips64el #define tcg_gen_clzi_i64 tcg_gen_clzi_i64_mips64el #define tcg_gen_cmp_vec tcg_gen_cmp_vec_mips64el +#define tcg_gen_cmpsel_vec tcg_gen_cmpsel_vec_mips64el #define tcg_gen_ctpop_i32 tcg_gen_ctpop_i32_mips64el #define tcg_gen_ctpop_i64 tcg_gen_ctpop_i64_mips64el #define tcg_gen_ctz_i32 tcg_gen_ctz_i32_mips64el diff --git a/qemu/mipsel.h b/qemu/mipsel.h index 6a7580d8..c0a1f54d 100644 --- a/qemu/mipsel.h +++ b/qemu/mipsel.h @@ -2805,6 +2805,7 @@ #define tcg_gen_clzi_i32 tcg_gen_clzi_i32_mipsel #define tcg_gen_clzi_i64 tcg_gen_clzi_i64_mipsel #define tcg_gen_cmp_vec tcg_gen_cmp_vec_mipsel +#define tcg_gen_cmpsel_vec tcg_gen_cmpsel_vec_mipsel #define tcg_gen_ctpop_i32 tcg_gen_ctpop_i32_mipsel #define tcg_gen_ctpop_i64 tcg_gen_ctpop_i64_mipsel #define tcg_gen_ctz_i32 tcg_gen_ctz_i32_mipsel diff --git a/qemu/powerpc.h b/qemu/powerpc.h index 2f8a07c9..0d178c54 100644 --- a/qemu/powerpc.h +++ b/qemu/powerpc.h @@ -2805,6 +2805,7 @@ #define tcg_gen_clzi_i32 tcg_gen_clzi_i32_powerpc #define tcg_gen_clzi_i64 tcg_gen_clzi_i64_powerpc #define tcg_gen_cmp_vec tcg_gen_cmp_vec_powerpc +#define tcg_gen_cmpsel_vec tcg_gen_cmpsel_vec_powerpc #define tcg_gen_ctpop_i32 tcg_gen_ctpop_i32_powerpc #define tcg_gen_ctpop_i64 tcg_gen_ctpop_i64_powerpc #define tcg_gen_ctz_i32 tcg_gen_ctz_i32_powerpc diff --git a/qemu/riscv32.h b/qemu/riscv32.h index 40dbc5e3..00529ccd 100644 --- a/qemu/riscv32.h +++ b/qemu/riscv32.h @@ -2805,6 +2805,7 @@ #define tcg_gen_clzi_i32 tcg_gen_clzi_i32_riscv32 #define tcg_gen_clzi_i64 tcg_gen_clzi_i64_riscv32 #define tcg_gen_cmp_vec tcg_gen_cmp_vec_riscv32 +#define tcg_gen_cmpsel_vec tcg_gen_cmpsel_vec_riscv32 #define tcg_gen_ctpop_i32 tcg_gen_ctpop_i32_riscv32 #define tcg_gen_ctpop_i64 tcg_gen_ctpop_i64_riscv32 #define tcg_gen_ctz_i32 tcg_gen_ctz_i32_riscv32 diff --git a/qemu/riscv64.h b/qemu/riscv64.h index 919ef926..4b3c3759 100644 --- a/qemu/riscv64.h +++ b/qemu/riscv64.h @@ -2805,6 +2805,7 @@ #define tcg_gen_clzi_i32 tcg_gen_clzi_i32_riscv64 #define tcg_gen_clzi_i64 tcg_gen_clzi_i64_riscv64 #define tcg_gen_cmp_vec tcg_gen_cmp_vec_riscv64 +#define tcg_gen_cmpsel_vec tcg_gen_cmpsel_vec_riscv64 #define tcg_gen_ctpop_i32 tcg_gen_ctpop_i32_riscv64 #define tcg_gen_ctpop_i64 tcg_gen_ctpop_i64_riscv64 #define tcg_gen_ctz_i32 tcg_gen_ctz_i32_riscv64 diff --git a/qemu/sparc.h b/qemu/sparc.h index 5e54e27d..b4523031 100644 --- a/qemu/sparc.h +++ b/qemu/sparc.h @@ -2805,6 +2805,7 @@ #define tcg_gen_clzi_i32 tcg_gen_clzi_i32_sparc #define tcg_gen_clzi_i64 tcg_gen_clzi_i64_sparc #define tcg_gen_cmp_vec tcg_gen_cmp_vec_sparc +#define tcg_gen_cmpsel_vec tcg_gen_cmpsel_vec_sparc #define tcg_gen_ctpop_i32 tcg_gen_ctpop_i32_sparc #define tcg_gen_ctpop_i64 tcg_gen_ctpop_i64_sparc #define tcg_gen_ctz_i32 tcg_gen_ctz_i32_sparc diff --git a/qemu/sparc64.h b/qemu/sparc64.h index 0e130500..3592eaf9 100644 --- a/qemu/sparc64.h +++ b/qemu/sparc64.h @@ -2805,6 +2805,7 @@ #define tcg_gen_clzi_i32 tcg_gen_clzi_i32_sparc64 #define tcg_gen_clzi_i64 tcg_gen_clzi_i64_sparc64 #define tcg_gen_cmp_vec tcg_gen_cmp_vec_sparc64 +#define tcg_gen_cmpsel_vec tcg_gen_cmpsel_vec_sparc64 #define tcg_gen_ctpop_i32 tcg_gen_ctpop_i32_sparc64 #define tcg_gen_ctpop_i64 tcg_gen_ctpop_i64_sparc64 #define tcg_gen_ctz_i32 tcg_gen_ctz_i32_sparc64 diff --git a/qemu/tcg/README b/qemu/tcg/README index 2308b656..46c597dd 100644 --- a/qemu/tcg/README +++ b/qemu/tcg/README @@ -626,6 +626,13 @@ E.g. VECL=1 -> 64 << 1 -> v128, and VECE=2 -> 1 << 2 -> i32. Bitwise select, v0 = (v2 & v1) | (v3 & ~v1), across the entire vector. +* cmpsel_vec v0, c1, c2, v3, v4, cond + + Select elements based on comparison results: + for (i = 0; i < n; ++i) { + v0[i] = (c1[i] cond c2[i]) ? v3[i] : v4[i]. + } + ********* Note 1: Some shortcuts are defined when the last operand is known to be diff --git a/qemu/tcg/aarch64/tcg-target.h b/qemu/tcg/aarch64/tcg-target.h index 52ee6642..b4a9d36b 100644 --- a/qemu/tcg/aarch64/tcg-target.h +++ b/qemu/tcg/aarch64/tcg-target.h @@ -141,6 +141,7 @@ typedef enum { #define TCG_TARGET_HAS_sat_vec 1 #define TCG_TARGET_HAS_minmax_vec 1 #define TCG_TARGET_HAS_bitsel_vec 0 +#define TCG_TARGET_HAS_cmpsel_vec 0 #define TCG_TARGET_DEFAULT_MO (0) #define TCG_TARGET_HAS_MEMORY_BSWAP 1 diff --git a/qemu/tcg/i386/tcg-target.h b/qemu/tcg/i386/tcg-target.h index 15493ca5..850a69ed 100644 --- a/qemu/tcg/i386/tcg-target.h +++ b/qemu/tcg/i386/tcg-target.h @@ -224,6 +224,7 @@ extern bool have_avx2; #define TCG_TARGET_HAS_sat_vec 1 #define TCG_TARGET_HAS_minmax_vec 1 #define TCG_TARGET_HAS_bitsel_vec 0 +#define TCG_TARGET_HAS_cmpsel_vec 0 #define TCG_TARGET_deposit_i32_valid(ofs, len) \ (((ofs) == 0 && (len) == 8) || ((ofs) == 8 && (len) == 8) || \ diff --git a/qemu/tcg/tcg-op-vec.c b/qemu/tcg/tcg-op-vec.c index 85f0020e..f6e68b9a 100644 --- a/qemu/tcg/tcg-op-vec.c +++ b/qemu/tcg/tcg-op-vec.c @@ -120,6 +120,11 @@ bool tcg_can_emit_vecop_list(const TCGOpcode *list, continue; } break; + case INDEX_op_cmpsel_vec: + if (tcg_can_emit_vec_op(INDEX_op_cmp_vec, type, vece)) { + continue; + } + break; default: break; } @@ -160,6 +165,20 @@ void vec_gen_4(TCGContext *s, TCGOpcode opc, TCGType type, unsigned vece, op->args[3] = c; } +static void vec_gen_6(TCGContext *s, TCGOpcode opc, TCGType type, unsigned vece, TCGArg r, + TCGArg a, TCGArg b, TCGArg c, TCGArg d, TCGArg e) +{ + TCGOp *op = tcg_emit_op(s, opc); + TCGOP_VECL(op) = type - TCG_TYPE_V64; + TCGOP_VECE(op) = vece; + op->args[0] = r; + op->args[1] = a; + op->args[2] = b; + op->args[3] = c; + op->args[4] = d; + op->args[5] = e; +} + static void vec_gen_op2(TCGContext *s, TCGOpcode opc, unsigned vece, TCGv_vec r, TCGv_vec a) { TCGTemp *rt = tcgv_vec_temp(s, r); @@ -718,3 +737,43 @@ void tcg_gen_bitsel_vec(TCGContext *s, unsigned vece, TCGv_vec r, TCGv_vec a, tcg_temp_free_vec(s, t); } } + +void tcg_gen_cmpsel_vec(TCGContext *s, TCGCond cond, unsigned vece, TCGv_vec r, + TCGv_vec a, TCGv_vec b, TCGv_vec c, TCGv_vec d) +{ + TCGTemp *rt = tcgv_vec_temp(s, r); + TCGTemp *at = tcgv_vec_temp(s, a); + TCGTemp *bt = tcgv_vec_temp(s, b); + TCGTemp *ct = tcgv_vec_temp(s, c); + TCGTemp *dt = tcgv_vec_temp(s, d); + TCGArg ri = temp_arg(rt); + TCGArg ai = temp_arg(at); + TCGArg bi = temp_arg(bt); + TCGArg ci = temp_arg(ct); + TCGArg di = temp_arg(dt); + TCGType type = rt->base_type; + const TCGOpcode *hold_list; + int can; + + tcg_debug_assert(at->base_type >= type); + tcg_debug_assert(bt->base_type >= type); + tcg_debug_assert(ct->base_type >= type); + tcg_debug_assert(dt->base_type >= type); + + tcg_assert_listed_vecop(s, INDEX_op_cmpsel_vec); + hold_list = tcg_swap_vecop_list(s, NULL); + can = tcg_can_emit_vec_op(INDEX_op_cmpsel_vec, type, vece); + + if (can > 0) { + vec_gen_6(s, INDEX_op_cmpsel_vec, type, vece, ri, ai, bi, ci, di, cond); + } else if (can < 0) { + tcg_expand_vec_op(s, INDEX_op_cmpsel_vec, type, vece, + ri, ai, bi, ci, di, cond); + } else { + TCGv_vec t = tcg_temp_new_vec(s, type); + tcg_gen_cmp_vec(s, cond, vece, t, a, b); + tcg_gen_bitsel_vec(s, vece, r, t, c, d); + tcg_temp_free_vec(s, t); + } + tcg_swap_vecop_list(s, hold_list); +} diff --git a/qemu/tcg/tcg-op.h b/qemu/tcg/tcg-op.h index 00bd885d..da7137a2 100644 --- a/qemu/tcg/tcg-op.h +++ b/qemu/tcg/tcg-op.h @@ -1015,6 +1015,8 @@ void tcg_gen_cmp_vec(TCGContext *, TCGCond cond, unsigned vece, TCGv_vec r, void tcg_gen_bitsel_vec(TCGContext *, unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b, TCGv_vec c); +void tcg_gen_cmpsel_vec(TCGContext *, TCGCond cond, unsigned vece, TCGv_vec r, + TCGv_vec a, TCGv_vec b, TCGv_vec c, TCGv_vec d); void tcg_gen_ld_vec(TCGContext *, TCGv_vec r, TCGv_ptr base, TCGArg offset); void tcg_gen_st_vec(TCGContext *, TCGv_vec r, TCGv_ptr base, TCGArg offset); diff --git a/qemu/tcg/tcg-opc.h b/qemu/tcg/tcg-opc.h index 39a3ea7f..e1620fd4 100644 --- a/qemu/tcg/tcg-opc.h +++ b/qemu/tcg/tcg-opc.h @@ -262,6 +262,7 @@ DEF(sarv_vec, 1, 2, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_shv_vec)) DEF(cmp_vec, 1, 2, 1, IMPLVEC) DEF(bitsel_vec, 1, 3, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_bitsel_vec)) +DEF(cmpsel_vec, 1, 4, 1, IMPLVEC | IMPL(TCG_TARGET_HAS_cmpsel_vec)) DEF(last_generic, 0, 0, 0, TCG_OPF_NOT_PRESENT) diff --git a/qemu/tcg/tcg.c b/qemu/tcg/tcg.c index 274ac686..d66eafff 100644 --- a/qemu/tcg/tcg.c +++ b/qemu/tcg/tcg.c @@ -1090,6 +1090,8 @@ bool tcg_op_supported(TCGOpcode op) return have_vec && TCG_TARGET_HAS_minmax_vec; case INDEX_op_bitsel_vec: return have_vec && TCG_TARGET_HAS_bitsel_vec; + case INDEX_op_cmpsel_vec: + return have_vec && TCG_TARGET_HAS_cmpsel_vec; default: tcg_debug_assert(op > INDEX_op_last_generic && op < NB_OPS); @@ -1470,6 +1472,7 @@ static void tcg_dump_ops(TCGContext *s, bool have_prefs) case INDEX_op_setcond_i64: case INDEX_op_movcond_i64: case INDEX_op_cmp_vec: + case INDEX_op_cmpsel_vec: if (op->args[k] < ARRAY_SIZE(cond_name) && cond_name[op->args[k]]) { col += qemu_log(",%s", cond_name[op->args[k++]]); diff --git a/qemu/tcg/tcg.h b/qemu/tcg/tcg.h index dde1bf1a..953ba93b 100644 --- a/qemu/tcg/tcg.h +++ b/qemu/tcg/tcg.h @@ -191,6 +191,7 @@ typedef uint64_t TCGRegSet; #define TCG_TARGET_HAS_sat_vec 0 #define TCG_TARGET_HAS_minmax_vec 0 #define TCG_TARGET_HAS_bitsel_vec 0 +#define TCG_TARGET_HAS_cmpsel_vec 0 #else #define TCG_TARGET_MAYBE_vec 1 #endif @@ -1177,7 +1178,7 @@ static inline TCGv_ptr tcg_temp_local_new_ptr(TCGContext *s) } // UNICORN: Added -#define TCG_OP_DEFS_TABLE_SIZE 184 +#define TCG_OP_DEFS_TABLE_SIZE 185 extern const TCGOpDef tcg_op_defs_org[TCG_OP_DEFS_TABLE_SIZE]; typedef struct TCGTargetOpDef { diff --git a/qemu/x86_64.h b/qemu/x86_64.h index 6ed3784c..e3f9df3e 100644 --- a/qemu/x86_64.h +++ b/qemu/x86_64.h @@ -2805,6 +2805,7 @@ #define tcg_gen_clzi_i32 tcg_gen_clzi_i32_x86_64 #define tcg_gen_clzi_i64 tcg_gen_clzi_i64_x86_64 #define tcg_gen_cmp_vec tcg_gen_cmp_vec_x86_64 +#define tcg_gen_cmpsel_vec tcg_gen_cmpsel_vec_x86_64 #define tcg_gen_ctpop_i32 tcg_gen_ctpop_i32_x86_64 #define tcg_gen_ctpop_i64 tcg_gen_ctpop_i64_x86_64 #define tcg_gen_ctz_i32 tcg_gen_ctz_i32_x86_64