From 2f785b11d243500e32488d3f950e5401cdf96ee3 Mon Sep 17 00:00:00 2001
From: Lioncash <mathew1800@gmail.com>
Date: Wed, 21 Feb 2018 01:08:00 -0500
Subject: [PATCH] tcg: Make cpu_tbr a TCGv

Commit 5d4e1a1081d3f1ec2908ff0eaebe312389971ab4
allows making the type concrete
---
 qemu/target-sparc/translate.c | 11 +++++------
 qemu/target-sparc/unicorn.c   |  1 -
 qemu/tcg/tcg.h                |  2 +-
 3 files changed, 6 insertions(+), 8 deletions(-)

diff --git a/qemu/target-sparc/translate.c b/qemu/target-sparc/translate.c
index 437b263e..4133abe9 100644
--- a/qemu/target-sparc/translate.c
+++ b/qemu/target-sparc/translate.c
@@ -3020,7 +3020,7 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn, bool hook_ins
                     }
                     break;
                 case 5: // tba
-                    tcg_gen_mov_tl(tcg_ctx, cpu_tmp0, *(TCGv *)tcg_ctx->cpu_tbr);
+                    tcg_gen_mov_tl(tcg_ctx, cpu_tmp0, tcg_ctx->cpu_tbr);
                     break;
                 case 6: // pstate
                     tcg_gen_ld32s_tl(tcg_ctx, cpu_tmp0, tcg_ctx->cpu_env,
@@ -3087,7 +3087,7 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn, bool hook_ins
 #else
                 if (!supervisor(dc))
                     goto priv_insn;
-                gen_store_gpr(dc, rd, *(TCGv *)tcg_ctx->cpu_tbr);
+                gen_store_gpr(dc, rd, tcg_ctx->cpu_tbr);
 #endif
                 break;
 #endif
@@ -3968,7 +3968,7 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn, bool hook_ins
                                 }
                                 break;
                             case 5: // tba
-                                tcg_gen_mov_tl(tcg_ctx, *(TCGv *)tcg_ctx->cpu_tbr, cpu_tmp0);
+                                tcg_gen_mov_tl(tcg_ctx, tcg_ctx->cpu_tbr, cpu_tmp0);
                                 break;
                             case 6: // pstate
                                 save_state(dc);
@@ -4040,7 +4040,7 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn, bool hook_ins
 #ifndef TARGET_SPARC64
                             if (!supervisor(dc))
                                 goto priv_insn;
-                            tcg_gen_xor_tl(tcg_ctx, *(TCGv *)tcg_ctx->cpu_tbr, cpu_src1, cpu_src2);
+                            tcg_gen_xor_tl(tcg_ctx, tcg_ctx->cpu_tbr, cpu_src1, cpu_src2);
 #else
                             CHECK_IU_FEATURE(dc, HYPV);
                             if (!hypervisor(dc))
@@ -5616,8 +5616,7 @@ void gen_intermediate_code_init(CPUSPARCState *env)
 
     tcg_ctx->cpu_y = tcg_global_mem_new(tcg_ctx, tcg_ctx->cpu_env, offsetof(CPUSPARCState, y), "y");
 #ifndef CONFIG_USER_ONLY
-    tcg_ctx->cpu_tbr = g_malloc0(sizeof(TCGv));
-    *(TCGv *)tcg_ctx->cpu_tbr = tcg_global_mem_new(tcg_ctx, tcg_ctx->cpu_env, offsetof(CPUSPARCState, tbr),
+    tcg_ctx->cpu_tbr = tcg_global_mem_new(tcg_ctx, tcg_ctx->cpu_env, offsetof(CPUSPARCState, tbr),
             "tbr");
 #endif
 
diff --git a/qemu/target-sparc/unicorn.c b/qemu/target-sparc/unicorn.c
index 5c0f1cbf..44767768 100644
--- a/qemu/target-sparc/unicorn.c
+++ b/qemu/target-sparc/unicorn.c
@@ -42,7 +42,6 @@ void sparc_release(void *ctx)
     g_free(tcg_ctx->cpu_fsr);
     g_free(tcg_ctx->sparc_cpu_pc);
     g_free(tcg_ctx->cpu_npc);
-    g_free(tcg_ctx->cpu_tbr);
 
     for (i = 0; i < 32; i++) {
       g_free(tcg_ctx->cpu_regs_sparc[i]);
diff --git a/qemu/tcg/tcg.h b/qemu/tcg/tcg.h
index d8bfac77..d3d113d0 100644
--- a/qemu/tcg/tcg.h
+++ b/qemu/tcg/tcg.h
@@ -836,7 +836,7 @@ struct TCGContext {
     void *cpu_fsr, *sparc_cpu_pc, *cpu_npc;
     void *cpu_regs_sparc[32];
     TCGv cpu_y;
-    void *cpu_tbr;
+    TCGv cpu_tbr;
     void *cpu_cond;
     void *cpu_gsr;
     void *cpu_tick_cmpr, *cpu_stick_cmpr, *cpu_hstick_cmpr;