From 2f7cdaee7bce8bcc5c62fbe78104791a1a432131 Mon Sep 17 00:00:00 2001 From: LIU Zhiwei Date: Sun, 7 Mar 2021 12:27:07 -0500 Subject: [PATCH] target/riscv: vector iota instruction Backports 78d90cfe859c8f5bd7baa0d41a4b5126e08eac24 --- qemu/header_gen.py | 4 +++ qemu/riscv32.h | 4 +++ qemu/riscv64.h | 4 +++ qemu/target/riscv/helper.h | 5 ++++ qemu/target/riscv/insn32.decode | 1 + qemu/target/riscv/insn_trans/trans_rvv.inc.c | 29 ++++++++++++++++++++ qemu/target/riscv/vector_helper.c | 29 ++++++++++++++++++++ 7 files changed, 76 insertions(+) diff --git a/qemu/header_gen.py b/qemu/header_gen.py index 0c889f3b..5db81283 100644 --- a/qemu/header_gen.py +++ b/qemu/header_gen.py @@ -7263,6 +7263,10 @@ riscv_symbols = ( 'helper_vmsbf_m', 'helper_vmsif_m', 'helper_vmsof_m', + 'helper_viota_m_b', + 'helper_viota_m_h', + 'helper_viota_m_w', + 'helper_viota_m_d', 'pmp_hart_has_privs', 'pmpaddr_csr_read', 'pmpaddr_csr_write', diff --git a/qemu/riscv32.h b/qemu/riscv32.h index af3ef301..851105cb 100644 --- a/qemu/riscv32.h +++ b/qemu/riscv32.h @@ -4699,6 +4699,10 @@ #define helper_vmsbf_m helper_vmsbf_m_riscv32 #define helper_vmsif_m helper_vmsif_m_riscv32 #define helper_vmsof_m helper_vmsof_m_riscv32 +#define helper_viota_m_b helper_viota_m_b_riscv32 +#define helper_viota_m_h helper_viota_m_h_riscv32 +#define helper_viota_m_w helper_viota_m_w_riscv32 +#define helper_viota_m_d helper_viota_m_d_riscv32 #define pmp_hart_has_privs pmp_hart_has_privs_riscv32 #define pmpaddr_csr_read pmpaddr_csr_read_riscv32 #define pmpaddr_csr_write pmpaddr_csr_write_riscv32 diff --git a/qemu/riscv64.h b/qemu/riscv64.h index 5d277d5e..7a2ef5ff 100644 --- a/qemu/riscv64.h +++ b/qemu/riscv64.h @@ -4699,6 +4699,10 @@ #define helper_vmsbf_m helper_vmsbf_m_riscv64 #define helper_vmsif_m helper_vmsif_m_riscv64 #define helper_vmsof_m helper_vmsof_m_riscv64 +#define helper_viota_m_b helper_viota_m_b_riscv64 +#define helper_viota_m_h helper_viota_m_h_riscv64 +#define helper_viota_m_w helper_viota_m_w_riscv64 +#define helper_viota_m_d helper_viota_m_d_riscv64 #define pmp_hart_has_privs pmp_hart_has_privs_riscv64 #define pmpaddr_csr_read pmpaddr_csr_read_riscv64 #define pmpaddr_csr_write pmpaddr_csr_write_riscv64 diff --git a/qemu/target/riscv/helper.h b/qemu/target/riscv/helper.h index 9fc220ad..a2925743 100644 --- a/qemu/target/riscv/helper.h +++ b/qemu/target/riscv/helper.h @@ -1112,3 +1112,8 @@ DEF_HELPER_4(vmfirst_m, tl, ptr, ptr, env, i32) DEF_HELPER_5(vmsbf_m, void, ptr, ptr, ptr, env, i32) DEF_HELPER_5(vmsif_m, void, ptr, ptr, ptr, env, i32) DEF_HELPER_5(vmsof_m, void, ptr, ptr, ptr, env, i32) + +DEF_HELPER_5(viota_m_b, void, ptr, ptr, ptr, env, i32) +DEF_HELPER_5(viota_m_h, void, ptr, ptr, ptr, env, i32) +DEF_HELPER_5(viota_m_w, void, ptr, ptr, ptr, env, i32) +DEF_HELPER_5(viota_m_d, void, ptr, ptr, ptr, env, i32) diff --git a/qemu/target/riscv/insn32.decode b/qemu/target/riscv/insn32.decode index fab4a0b7..41552357 100644 --- a/qemu/target/riscv/insn32.decode +++ b/qemu/target/riscv/insn32.decode @@ -560,6 +560,7 @@ vmfirst_m 010101 . ..... ----- 010 ..... 1010111 @r2_vm vmsbf_m 010110 . ..... 00001 010 ..... 1010111 @r2_vm vmsif_m 010110 . ..... 00011 010 ..... 1010111 @r2_vm vmsof_m 010110 . ..... 00010 010 ..... 1010111 @r2_vm +viota_m 010110 . ..... 10000 010 ..... 1010111 @r2_vm vsetvli 0 ........... ..... 111 ..... 1010111 @r2_zimm vsetvl 1000000 ..... ..... 111 ..... 1010111 @r diff --git a/qemu/target/riscv/insn_trans/trans_rvv.inc.c b/qemu/target/riscv/insn_trans/trans_rvv.inc.c index 2c839ca7..8ca2dc86 100644 --- a/qemu/target/riscv/insn_trans/trans_rvv.inc.c +++ b/qemu/target/riscv/insn_trans/trans_rvv.inc.c @@ -2524,3 +2524,32 @@ static bool trans_##NAME(DisasContext *s, arg_rmr *a) \ GEN_M_TRANS(vmsbf_m) GEN_M_TRANS(vmsif_m) GEN_M_TRANS(vmsof_m) + +/* Vector Iota Instruction */ +static bool trans_viota_m(DisasContext *s, arg_viota_m *a) +{ + TCGContext *tcg_ctx = s->uc->tcg_ctx; + + if (vext_check_isa_ill(s) && + vext_check_reg(s, a->rd, false) && + vext_check_overlap_group(a->rd, 1 << s->lmul, a->rs2, 1) && + (a->vm != 0 || a->rd != 0)) { + uint32_t data = 0; + TCGLabel *over = gen_new_label(tcg_ctx); + tcg_gen_brcondi_tl(tcg_ctx, TCG_COND_EQ, tcg_ctx->cpu_vl_risc, 0, over); + + data = FIELD_DP32(data, VDATA, MLEN, s->mlen); + data = FIELD_DP32(data, VDATA, VM, a->vm); + data = FIELD_DP32(data, VDATA, LMUL, s->lmul); + static gen_helper_gvec_3_ptr * const fns[4] = { + gen_helper_viota_m_b, gen_helper_viota_m_h, + gen_helper_viota_m_w, gen_helper_viota_m_d, + }; + tcg_gen_gvec_3_ptr(tcg_ctx, vreg_ofs(s, a->rd), vreg_ofs(s, 0), + vreg_ofs(s, a->rs2), tcg_ctx->cpu_env, 0, + s->vlen / 8, data, fns[s->sew]); + gen_set_label(tcg_ctx, over); + return true; + } + return false; +} diff --git a/qemu/target/riscv/vector_helper.c b/qemu/target/riscv/vector_helper.c index 0603cf7f..489574f8 100644 --- a/qemu/target/riscv/vector_helper.c +++ b/qemu/target/riscv/vector_helper.c @@ -4620,3 +4620,32 @@ void HELPER(vmsof_m)(void *vd, void *v0, void *vs2, CPURISCVState *env, { vmsetm(vd, v0, vs2, env, desc, ONLY_FIRST); } + +/* Vector Iota Instruction */ +#define GEN_VEXT_VIOTA_M(NAME, ETYPE, H, CLEAR_FN) \ +void HELPER(NAME)(void *vd, void *v0, void *vs2, CPURISCVState *env, \ + uint32_t desc) \ +{ \ + uint32_t mlen = vext_mlen(desc); \ + uint32_t vlmax = env_archcpu(env)->cfg.vlen / mlen; \ + uint32_t vm = vext_vm(desc); \ + uint32_t vl = env->vl; \ + uint32_t sum = 0; \ + int i; \ + \ + for (i = 0; i < vl; i++) { \ + if (!vm && !vext_elem_mask(v0, mlen, i)) { \ + continue; \ + } \ + *((ETYPE *)vd + H(i)) = sum; \ + if (vext_elem_mask(vs2, mlen, i)) { \ + sum++; \ + } \ + } \ + CLEAR_FN(vd, vl, vl * sizeof(ETYPE), vlmax * sizeof(ETYPE)); \ +} + +GEN_VEXT_VIOTA_M(viota_m_b, uint8_t, H1, clearb) +GEN_VEXT_VIOTA_M(viota_m_h, uint16_t, H2, clearh) +GEN_VEXT_VIOTA_M(viota_m_w, uint32_t, H4, clearl) +GEN_VEXT_VIOTA_M(viota_m_d, uint64_t, H8, clearq)