From 3094e7927ea09eded8f5894c17084ed9abba42f7 Mon Sep 17 00:00:00 2001 From: Richard Henderson Date: Sun, 4 Mar 2018 23:48:45 -0500 Subject: [PATCH] tcg/arm: Fully convert tcg_target_op_def Backports commit 7536b82d28876d1ffe0359667b28c93d49386fa0 from qemu --- qemu/tcg/arm/tcg-target.inc.c | 173 ++++++++++++++++++---------------- 1 file changed, 92 insertions(+), 81 deletions(-) diff --git a/qemu/tcg/arm/tcg-target.inc.c b/qemu/tcg/arm/tcg-target.inc.c index 05269e08..cc87da7c 100644 --- a/qemu/tcg/arm/tcg-target.inc.c +++ b/qemu/tcg/arm/tcg-target.inc.c @@ -2060,91 +2060,102 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc, } } -static const TCGTargetOpDef arm_op_defs[] = { - { INDEX_op_exit_tb, { } }, - { INDEX_op_goto_tb, { } }, - { INDEX_op_br, { } }, - { INDEX_op_goto_ptr, { "r" } }, - - { INDEX_op_ld8u_i32, { "r", "r" } }, - { INDEX_op_ld8s_i32, { "r", "r" } }, - { INDEX_op_ld16u_i32, { "r", "r" } }, - { INDEX_op_ld16s_i32, { "r", "r" } }, - { INDEX_op_ld_i32, { "r", "r" } }, - { INDEX_op_st8_i32, { "r", "r" } }, - { INDEX_op_st16_i32, { "r", "r" } }, - { INDEX_op_st_i32, { "r", "r" } }, - - /* TODO: "r", "r", "ri" */ - { INDEX_op_add_i32, { "r", "r", "rIN" } }, - { INDEX_op_sub_i32, { "r", "rI", "rIN" } }, - { INDEX_op_mul_i32, { "r", "r", "r" } }, - { INDEX_op_mulu2_i32, { "r", "r", "r", "r" } }, - { INDEX_op_muls2_i32, { "r", "r", "r", "r" } }, - { INDEX_op_and_i32, { "r", "r", "rIK" } }, - { INDEX_op_andc_i32, { "r", "r", "rIK" } }, - { INDEX_op_or_i32, { "r", "r", "rI" } }, - { INDEX_op_xor_i32, { "r", "r", "rI" } }, - { INDEX_op_neg_i32, { "r", "r" } }, - { INDEX_op_not_i32, { "r", "r" } }, - - { INDEX_op_shl_i32, { "r", "r", "ri" } }, - { INDEX_op_shr_i32, { "r", "r", "ri" } }, - { INDEX_op_sar_i32, { "r", "r", "ri" } }, - { INDEX_op_rotl_i32, { "r", "r", "ri" } }, - { INDEX_op_rotr_i32, { "r", "r", "ri" } }, - { INDEX_op_clz_i32, { "r", "r", "rIK" } }, - { INDEX_op_ctz_i32, { "r", "r", "rIK" } }, - - { INDEX_op_brcond_i32, { "r", "rIN" } }, - { INDEX_op_setcond_i32, { "r", "r", "rIN" } }, - { INDEX_op_movcond_i32, { "r", "r", "rIN", "rIK", "0" } }, - - { INDEX_op_add2_i32, { "r", "r", "r", "r", "rIN", "rIK" } }, - { INDEX_op_sub2_i32, { "r", "r", "rI", "rI", "rIN", "rIK" } }, - { INDEX_op_brcond2_i32, { "r", "r", "rIN", "rIN" } }, - { INDEX_op_setcond2_i32, { "r", "r", "r", "rIN", "rIN" } }, - -#if TARGET_LONG_BITS == 32 - { INDEX_op_qemu_ld_i32, { "r", "l" } }, - { INDEX_op_qemu_ld_i64, { "r", "r", "l" } }, - { INDEX_op_qemu_st_i32, { "s", "s" } }, - { INDEX_op_qemu_st_i64, { "s", "s", "s" } }, -#else - { INDEX_op_qemu_ld_i32, { "r", "l", "l" } }, - { INDEX_op_qemu_ld_i64, { "r", "r", "l", "l" } }, - { INDEX_op_qemu_st_i32, { "s", "s", "s" } }, - { INDEX_op_qemu_st_i64, { "s", "s", "s", "s" } }, -#endif - - { INDEX_op_bswap16_i32, { "r", "r" } }, - { INDEX_op_bswap32_i32, { "r", "r" } }, - - { INDEX_op_ext8s_i32, { "r", "r" } }, - { INDEX_op_ext16s_i32, { "r", "r" } }, - { INDEX_op_ext16u_i32, { "r", "r" } }, - - { INDEX_op_deposit_i32, { "r", "0", "rZ" } }, - { INDEX_op_extract_i32, { "r", "r" } }, - { INDEX_op_sextract_i32, { "r", "r" } }, - - { INDEX_op_div_i32, { "r", "r", "r" } }, - { INDEX_op_divu_i32, { "r", "r", "r" } }, - - { INDEX_op_mb, { } }, - { -1 }, -}; - static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op) { - int i, n = ARRAY_SIZE(arm_op_defs); + static const TCGTargetOpDef r = { 0, { "r" } }; + static const TCGTargetOpDef r_r = { 0, { "r", "r" } }; + static const TCGTargetOpDef s_s = { 0, { "s", "s" } }; + static const TCGTargetOpDef r_l = { 0, { "r", "l" } }; + static const TCGTargetOpDef r_r_r = { 0, { "r", "r", "r" } }; + static const TCGTargetOpDef r_r_l = { 0, { "r", "r", "l" } }; + static const TCGTargetOpDef r_l_l = { 0, { "r", "l", "l" } }; + static const TCGTargetOpDef s_s_s = { 0, { "s", "s", "s" } }; + static const TCGTargetOpDef r_r_ri = { 0, { "r", "r", "ri" } }; + static const TCGTargetOpDef r_r_rI = { 0, { "r", "r", "rI" } }; + static const TCGTargetOpDef r_r_rIN = { 0, { "r", "r", "rIN" } }; + static const TCGTargetOpDef r_r_rIK = { 0, { "r", "r", "rIK" } }; + static const TCGTargetOpDef r_r_r_r = { 0, { "r", "r", "r", "r" } }; + static const TCGTargetOpDef r_r_l_l = { 0, { "r", "r", "l", "l" } }; + static const TCGTargetOpDef s_s_s_s = { 0, { "s", "s", "s", "s" } }; + static const TCGTargetOpDef br = { 0, { "r", "rIN" } }; + static const TCGTargetOpDef dep = { 0, { "r", "0", "rZ" } }; + static const TCGTargetOpDef movc = { 0, { "r", "r", "rIN", "rIK", "0" } }; + static const TCGTargetOpDef add2 = { 0, { "r", "r", "r", "r", "rIN", "rIK" } }; + static const TCGTargetOpDef sub2 = { 0, { "r", "r", "rI", "rI", "rIN", "rIK" } }; + static const TCGTargetOpDef br2 = { 0, { "r", "r", "rIN", "rIN" } }; + static const TCGTargetOpDef setc2 = { 0, { "r", "r", "r", "rIN", "rIN" } }; - for (i = 0; i < n; ++i) { - if (arm_op_defs[i].op == op) { - return &arm_op_defs[i]; - } + switch (op) { + case INDEX_op_goto_ptr: + return &r; + case INDEX_op_ld8u_i32: + case INDEX_op_ld8s_i32: + case INDEX_op_ld16u_i32: + case INDEX_op_ld16s_i32: + case INDEX_op_ld_i32: + case INDEX_op_st8_i32: + case INDEX_op_st16_i32: + case INDEX_op_st_i32: + case INDEX_op_neg_i32: + case INDEX_op_not_i32: + case INDEX_op_bswap16_i32: + case INDEX_op_bswap32_i32: + case INDEX_op_ext8s_i32: + case INDEX_op_ext16s_i32: + case INDEX_op_ext16u_i32: + case INDEX_op_extract_i32: + case INDEX_op_sextract_i32: + return &r_r; + case INDEX_op_add_i32: + case INDEX_op_sub_i32: + case INDEX_op_setcond_i32: + return &r_r_rIN; + case INDEX_op_and_i32: + case INDEX_op_andc_i32: + case INDEX_op_clz_i32: + case INDEX_op_ctz_i32: + return &r_r_rIK; + case INDEX_op_mul_i32: + case INDEX_op_div_i32: + case INDEX_op_divu_i32: + return &r_r_r; + case INDEX_op_mulu2_i32: + case INDEX_op_muls2_i32: + return &r_r_r_r; + case INDEX_op_or_i32: + case INDEX_op_xor_i32: + return &r_r_rI; + case INDEX_op_shl_i32: + case INDEX_op_shr_i32: + case INDEX_op_sar_i32: + case INDEX_op_rotl_i32: + case INDEX_op_rotr_i32: + return &r_r_ri; + case INDEX_op_brcond_i32: + return &br; + case INDEX_op_deposit_i32: + return &dep; + case INDEX_op_movcond_i32: + return &movc; + case INDEX_op_add2_i32: + return &add2; + case INDEX_op_sub2_i32: + return &sub2; + case INDEX_op_brcond2_i32: + return &br2; + case INDEX_op_setcond2_i32: + return &setc2; + case INDEX_op_qemu_ld_i32: + return TARGET_LONG_BITS == 32 ? &r_l : &r_l_l; + case INDEX_op_qemu_ld_i64: + return TARGET_LONG_BITS == 32 ? &r_r_l : &r_r_l_l; + case INDEX_op_qemu_st_i32: + return TARGET_LONG_BITS == 32 ? &s_s : &s_s_s; + case INDEX_op_qemu_st_i64: + return TARGET_LONG_BITS == 32 ? &s_s_s : &s_s_s_s; + default: + return NULL; } - return NULL; } static void tcg_target_init(TCGContext *s)