From 31f42b9f2c0dbcb89166ebb0d4a58cd180920dfd Mon Sep 17 00:00:00 2001
From: Aleksandar Markovic <amarkovic@wavecomp.com>
Date: Mon, 27 Aug 2018 04:11:09 -0400
Subject: [PATCH] target/mips: Add preprocessor constants for nanoMIPS

Add ISA_NANOMIPS32 and CPU_NANOMIPS32 preprocessor constants.

Backports commit fa7c0c9f5bc12970858a89f46dd5012c01545b80 from qemu
---
 qemu/target/mips/mips-defs.h | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/qemu/target/mips/mips-defs.h b/qemu/target/mips/mips-defs.h
index 047554ee..71f2a518 100644
--- a/qemu/target/mips/mips-defs.h
+++ b/qemu/target/mips/mips-defs.h
@@ -35,6 +35,7 @@
 #define   ISA_MIPS64R5  0x00001000
 #define   ISA_MIPS32R6  0x00002000
 #define   ISA_MIPS64R6  0x00004000
+#define   ISA_NANOMIPS32  0x00008000
 
 /* MIPS ASEs. */
 #define   ASE_MIPS16    0x00010000
@@ -83,6 +84,9 @@
 #define CPU_MIPS32R6 (CPU_MIPS32R5 | ISA_MIPS32R6)
 #define CPU_MIPS64R6 (CPU_MIPS64R5 | CPU_MIPS32R6 | ISA_MIPS64R6)
 
+/* Wave Computing: "nanoMIPS" */
+#define CPU_NANOMIPS32 (CPU_MIPS32R6 | ISA_NANOMIPS32)
+
 /* Strictly follow the architecture standard:
    - Disallow "special" instruction handling for PMON/SPIM.
    Note that we still maintain Count/Compare to match the host clock. */