From 32b7cee81e0d5109c188b6e329822ef1fa5a7165 Mon Sep 17 00:00:00 2001
From: Pranith Kumar <bobby.prani@gmail.com>
Date: Mon, 26 Feb 2018 03:26:30 -0500
Subject: [PATCH] target-aarch64: Generate fences for aarch64

Backports commit ce1bd93f94e8d4b7117744e49652d2f907bed99f from qemu
---
 qemu/target-arm/translate-a64.c | 29 ++++++++++++++++++++++++++++-
 1 file changed, 28 insertions(+), 1 deletion(-)

diff --git a/qemu/target-arm/translate-a64.c b/qemu/target-arm/translate-a64.c
index 8f2463fa..e6ac1495 100644
--- a/qemu/target-arm/translate-a64.c
+++ b/qemu/target-arm/translate-a64.c
@@ -1335,6 +1335,9 @@ static void gen_clrex(DisasContext *s, uint32_t insn)
 static void handle_sync(DisasContext *s, uint32_t insn,
                         unsigned int op1, unsigned int op2, unsigned int crm)
 {
+    TCGBar bar;
+    TCGContext *tcg_ctx = s->uc->tcg_ctx;
+
     if (op1 != 3) {
         unallocated_encoding(s);
         return;
@@ -1346,7 +1349,18 @@ static void handle_sync(DisasContext *s, uint32_t insn,
         return;
     case 4: /* DSB */
     case 5: /* DMB */
-        /* We don't emulate caches so barriers are no-ops */
+        switch (crm & 3) {
+        case 1: /* MBReqTypes_Reads */
+            bar = TCG_BAR_SC | TCG_MO_LD_LD | TCG_MO_LD_ST;
+            break;
+        case 2: /* MBReqTypes_Writes */
+            bar = TCG_BAR_SC | TCG_MO_ST_ST;
+            break;
+        default: /* MBReqTypes_All */
+            bar = TCG_BAR_SC | TCG_MO_ALL;
+            break;
+        }
+        tcg_gen_mb(tcg_ctx, bar);
         return;
     case 6: /* ISB */
         /* We need to break the TB after this insn to execute
@@ -1952,6 +1966,7 @@ static void disas_ldst_excl(DisasContext *s, uint32_t insn)
     int is_excl = !extract32(insn, 23, 1);
     int size = extract32(insn, 30, 2);
     TCGv_i64 tcg_addr;
+    TCGContext *tcg_ctx = s->uc->tcg_ctx;
 
     if ((!is_excl && !is_pair && !is_lasr) ||
         (!is_excl && is_pair) ||
@@ -1973,7 +1988,13 @@ static void disas_ldst_excl(DisasContext *s, uint32_t insn)
         if (!is_store) {
             s->is_ldex = true;
             gen_load_exclusive(s, rt, rt2, tcg_addr, size, is_pair);
+            if (is_lasr) {
+                tcg_gen_mb(tcg_ctx, TCG_MO_ALL | TCG_BAR_LDAQ);
+            }
         } else {
+            if (is_lasr) {
+                tcg_gen_mb(tcg_ctx, TCG_MO_ALL | TCG_BAR_STRL);
+            }
             gen_store_exclusive(s, rs, rt, rt2, tcg_addr, size, is_pair);
         }
     } else {
@@ -1982,11 +2003,17 @@ static void disas_ldst_excl(DisasContext *s, uint32_t insn)
 
         /* Generate ISS for non-exclusive accesses including LASR.  */
         if (is_store) {
+            if (is_lasr) {
+                tcg_gen_mb(tcg_ctx, TCG_MO_ALL | TCG_BAR_STRL);
+            }
             do_gpr_st(s, tcg_rt, tcg_addr, size,
                       true, rt, iss_sf, is_lasr);
         } else {
             do_gpr_ld(s, tcg_rt, tcg_addr, size, false, false,
                       true, rt, iss_sf, is_lasr);
+            if (is_lasr) {
+                tcg_gen_mb(tcg_ctx, TCG_MO_ALL | TCG_BAR_LDAQ);
+            }
         }
     }
 }