diff --git a/qemu/target-mips/translate_init.c b/qemu/target-mips/translate_init.c
index 405d1e3f..e425620e 100644
--- a/qemu/target-mips/translate_init.c
+++ b/qemu/target-mips/translate_init.c
@@ -429,6 +429,65 @@ static const mips_def_t mips_defs[] =
         CPU_MIPS32R2 | ASE_MIPS16 | ASE_DSP | ASE_DSPR2,
         MMU_TYPE_R4000,
     },
+    {
+        "M14K",
+        0x00019b00,
+        /* Config1 implemented, fixed mapping MMU,
+           no virtual icache, uncached coherency. */
+        MIPS_CONFIG0 | (0x2 << CP0C0_KU) | (0x2 << CP0C0_K23) |
+                       (0x1 << CP0C0_AR) | (MMU_TYPE_FMT << CP0C0_MT),
+        MIPS_CONFIG1,
+        MIPS_CONFIG2,
+        MIPS_CONFIG3 | (0x2 << CP0C3_ISA) | (1 << CP0C3_VInt),
+        0, 0,
+        0, 0,
+        0,
+        0,
+        0,
+        4,
+        32,
+        2,
+        0x1258FF17,
+        0,
+        0,
+        0,
+        0,
+        32,
+        32,
+        0,0, 0,0, 0,0, 0,0, 0,0, 0,0,
+        CPU_MIPS32R2 | ASE_MICROMIPS,
+        MMU_TYPE_FMT,
+    },
+    {
+        "M14Kc",
+        /* This is the TLB-based MMU core.  */
+        0x00019c00,
+        MIPS_CONFIG0 | (0x1 << CP0C0_AR) |
+                       (MMU_TYPE_R4000 << CP0C0_MT),
+        MIPS_CONFIG1 | (15 << CP0C1_MMU) |
+                       (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) |
+                       (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA),
+        MIPS_CONFIG2,
+        MIPS_CONFIG3 | (0x2 << CP0C3_ISA) | (0 << CP0C3_VInt),
+        0, 0,
+        0, 0,
+        0,
+        0,
+        0,
+        4,
+        32,
+        2,
+        0x1278FF17,
+        0,
+        0,
+        0,
+        0,
+        32,
+        32,
+        0,0, 0,0, 0,0, 0,0, 0,0, 0,0,
+        CPU_MIPS32R2 | ASE_MICROMIPS,
+        MMU_TYPE_R4000,
+    },
     {
         /* A generic CPU providing MIPS32 Release 5 features.
            FIXME: Eventually this should be replaced by a real CPU model. */